projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: hide away VBT private data in a separate header
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_vbt_defs.h
CommitLineData
72341af4
JN		 1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/*
29 * This information is private to VBT parsing in intel_bios.c.
30 *
31 * Please do NOT include anywhere else.
32 */
33#ifndef _INTEL_BIOS_PRIVATE
34#error "intel_vbt_defs.h is private to intel_bios.c"
35#endif
36
37#ifndef _INTEL_VBT_DEFS_H_
38#define _INTEL_VBT_DEFS_H_
39
40#include "intel_bios.h"
41
42/**
43 * struct vbt_header - VBT Header structure
44 * @signature: VBT signature, always starts with "$VBT"
45 * @version: Version of this structure
46 * @header_size: Size of this structure
47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks)
48 * @vbt_checksum: Checksum
49 * @reserved0: Reserved
50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT
51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT
52 */
53struct vbt_header {
54 u8 signature[20];
55 u16 version;
56 u16 header_size;
57 u16 vbt_size;
58 u8 vbt_checksum;
59 u8 reserved0;
60 u32 bdb_offset;
61 u32 aim_offset[4];
62} __packed;
63
64/**
65 * struct bdb_header - BDB Header structure
66 * @signature: BDB signature "BIOS_DATA_BLOCK"
67 * @version: Version of the data block definitions
68 * @header_size: Size of this structure
69 * @bdb_size: Size of BDB (BDB Header and data blocks)
70 */
71struct bdb_header {
72 u8 signature[16];
73 u16 version;
74 u16 header_size;
75 u16 bdb_size;
76} __packed;
77
78/* strictly speaking, this is a "skip" block, but it has interesting info */
79struct vbios_data {
80 u8 type; /* 0 == desktop, 1 == mobile */
81 u8 relstage;
82 u8 chipset;
83 u8 lvds_present:1;
84 u8 tv_present:1;
85 u8 rsvd2:6; /* finish byte */
86 u8 rsvd3[4];
87 u8 signon[155];
88 u8 copyright[61];
89 u16 code_segment;
90 u8 dos_boot_mode;
91 u8 bandwidth_percent;
92 u8 rsvd4; /* popup memory size */
93 u8 resize_pci_bios;
94 u8 rsvd5; /* is crt already on ddc2 */
95} __packed;
96
97/*
98 * There are several types of BIOS data blocks (BDBs), each block has
99 * an ID and size in the first 3 bytes (ID in first, size in next 2).
100 * Known types are listed below.
101 */
102#define BDB_GENERAL_FEATURES 1
103#define BDB_GENERAL_DEFINITIONS 2
104#define BDB_OLD_TOGGLE_LIST 3
105#define BDB_MODE_SUPPORT_LIST 4
106#define BDB_GENERIC_MODE_TABLE 5
107#define BDB_EXT_MMIO_REGS 6
108#define BDB_SWF_IO 7
109#define BDB_SWF_MMIO 8
110#define BDB_PSR 9
111#define BDB_MODE_REMOVAL_TABLE 10
112#define BDB_CHILD_DEVICE_TABLE 11
113#define BDB_DRIVER_FEATURES 12
114#define BDB_DRIVER_PERSISTENCE 13
115#define BDB_EXT_TABLE_PTRS 14
116#define BDB_DOT_CLOCK_OVERRIDE 15
117#define BDB_DISPLAY_SELECT 16
118/* 17 rsvd */
119#define BDB_DRIVER_ROTATION 18
120#define BDB_DISPLAY_REMOVE 19
121#define BDB_OEM_CUSTOM 20
122#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
123#define BDB_SDVO_LVDS_OPTIONS 22
124#define BDB_SDVO_PANEL_DTDS 23
125#define BDB_SDVO_LVDS_PNP_IDS 24
126#define BDB_SDVO_LVDS_POWER_SEQ 25
127#define BDB_TV_OPTIONS 26
128#define BDB_EDP 27
129#define BDB_LVDS_OPTIONS 40
130#define BDB_LVDS_LFP_DATA_PTRS 41
131#define BDB_LVDS_LFP_DATA 42
132#define BDB_LVDS_BACKLIGHT 43
133#define BDB_LVDS_POWER 44
134#define BDB_MIPI_CONFIG 52
135#define BDB_MIPI_SEQUENCE 53
136#define BDB_SKIP 254 /* VBIOS private block, ignore */
137
138struct bdb_general_features {
139 /* bits 1 */
140 u8 panel_fitting:2;
141 u8 flexaim:1;
142 u8 msg_enable:1;
143 u8 clear_screen:3;
144 u8 color_flip:1;
145
146 /* bits 2 */
147 u8 download_ext_vbt:1;
148 u8 enable_ssc:1;
149 u8 ssc_freq:1;
150 u8 enable_lfp_on_override:1;
151 u8 disable_ssc_ddt:1;
152 u8 rsvd7:1;
153 u8 display_clock_mode:1;
154 u8 rsvd8:1; /* finish byte */
155
156 /* bits 3 */
157 u8 disable_smooth_vision:1;
158 u8 single_dvi:1;
159 u8 rsvd9:1;
160 u8 fdi_rx_polarity_inverted:1;
161 u8 rsvd10:4; /* finish byte */
162
163 /* bits 4 */
164 u8 legacy_monitor_detect;
165
166 /* bits 5 */
167 u8 int_crt_support:1;
168 u8 int_tv_support:1;
169 u8 int_efp_support:1;
170 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
171 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
172 u8 rsvd11:3; /* finish byte */
173} __packed;
174
175/* pre-915 */
176#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
177#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
178#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
179#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
180
181/* Pre 915 */
182#define DEVICE_TYPE_NONE 0x00
183#define DEVICE_TYPE_CRT 0x01
184#define DEVICE_TYPE_TV 0x09
185#define DEVICE_TYPE_EFP 0x12
186#define DEVICE_TYPE_LFP 0x22
187/* On 915+ */
188#define DEVICE_TYPE_CRT_DPMS 0x6001
189#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
190#define DEVICE_TYPE_TV_COMPOSITE 0x0209
191#define DEVICE_TYPE_TV_MACROVISION 0x0289
192#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
193#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
194#define DEVICE_TYPE_TV_SCART 0x0209
195#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
196#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
197#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
198#define DEVICE_TYPE_EFP_DVI_I 0x6053
199#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
200#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
201#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
202#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
203#define DEVICE_TYPE_LFP_PANELLINK 0x5012
204#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
205#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
206#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
207#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
208
209#define DEVICE_CFG_NONE 0x00
210#define DEVICE_CFG_12BIT_DVOB 0x01
211#define DEVICE_CFG_12BIT_DVOC 0x02
212#define DEVICE_CFG_24BIT_DVOBC 0x09
213#define DEVICE_CFG_24BIT_DVOCB 0x0a
214#define DEVICE_CFG_DUAL_DVOB 0x11
215#define DEVICE_CFG_DUAL_DVOC 0x12
216#define DEVICE_CFG_DUAL_DVOBC 0x13
217#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
218#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
219
220#define DEVICE_WIRE_NONE 0x00
221#define DEVICE_WIRE_DVOB 0x01
222#define DEVICE_WIRE_DVOC 0x02
223#define DEVICE_WIRE_DVOBC 0x03
224#define DEVICE_WIRE_DVOBB 0x05
225#define DEVICE_WIRE_DVOCC 0x06
226#define DEVICE_WIRE_DVOB_MASTER 0x0d
227#define DEVICE_WIRE_DVOC_MASTER 0x0e
228
229#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
230#define DEVICE_PORT_DVOB 0x01
231#define DEVICE_PORT_DVOC 0x02
232
233/*
234 * We used to keep this struct but without any version control. We should avoid
235 * using it in the future, but it should be safe to keep using it in the old
236 * code. Do not change; we rely on its size.
237 */
238struct old_child_dev_config {
239 u16 handle;
240 u16 device_type;
241 u8 device_id[10]; /* ascii string */
242 u16 addin_offset;
243 u8 dvo_port; /* See Device_PORT_* above */
244 u8 i2c_pin;
245 u8 slave_addr;
246 u8 ddc_pin;
247 u16 edid_ptr;
248 u8 dvo_cfg; /* See DEVICE_CFG_* above */
249 u8 dvo2_port;
250 u8 i2c2_pin;
251 u8 slave2_addr;
252 u8 ddc2_pin;
253 u8 capabilities;
254 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
255 u8 dvo2_wiring;
256 u16 extended_type;
257 u8 dvo_function;
258} __packed;
259
260/* This one contains field offsets that are known to be common for all BDB
261 * versions. Notice that the meaning of the contents contents may still change,
262 * but at least the offsets are consistent. */
263
264/* Definitions for flags_1 */
265#define IBOOST_ENABLE (1<<3)
266
267struct common_child_dev_config {
268 u16 handle;
269 u16 device_type;
270 u8 not_common1[12];
271 u8 dvo_port;
272 u8 not_common2[2];
273 u8 ddc_pin;
274 u16 edid_ptr;
275 u8 obsolete;
276 u8 flags_1;
277 u8 not_common3[13];
278 u8 iboost_level;
279} __packed;
280
281
282/* This field changes depending on the BDB version, so the most reliable way to
283 * read it is by checking the BDB version and reading the raw pointer. */
284union child_device_config {
285 /* This one is safe to be used anywhere, but the code should still check
286 * the BDB version. */
287 u8 raw[33];
288 /* This one should only be kept for legacy code. */
289 struct old_child_dev_config old;
290 /* This one should also be safe to use anywhere, even without version
291 * checks. */
292 struct common_child_dev_config common;
293} __packed;
294
295struct bdb_general_definitions {
296 /* DDC GPIO */
297 u8 crt_ddc_gmbus_pin;
298
299 /* DPMS bits */
300 u8 dpms_acpi:1;
301 u8 skip_boot_crt_detect:1;
302 u8 dpms_aim:1;
303 u8 rsvd1:5; /* finish byte */
304
305 /* boot device bits */
306 u8 boot_display[2];
307 u8 child_dev_size;
308
309 /*
310 * Device info:
311 * If TV is present, it'll be at devices[0].
312 * LVDS will be next, either devices[0] or [1], if present.
313 * On some platforms the number of device is 6. But could be as few as
314 * 4 if both TV and LVDS are missing.
315 * And the device num is related with the size of general definition
316 * block. It is obtained by using the following formula:
317 * number = (block_size - sizeof(bdb_general_definitions))/
318 * defs->child_dev_size;
319 */
320 uint8_t devices[0];
321} __packed;
322
323/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
324#define MODE_MASK 0x3
325
326struct bdb_lvds_options {
327 u8 panel_type;
328 u8 rsvd1;
329 /* LVDS capabilities, stored in a dword */
330 u8 pfit_mode:2;
331 u8 pfit_text_mode_enhanced:1;
332 u8 pfit_gfx_mode_enhanced:1;
333 u8 pfit_ratio_auto:1;
334 u8 pixel_dither:1;
335 u8 lvds_edid:1;
336 u8 rsvd2:1;
337 u8 rsvd4;
338 /* LVDS Panel channel bits stored here */
339 u32 lvds_panel_channel_bits;
340 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
341 u16 ssc_bits;
342 u16 ssc_freq;
343 u16 ssc_ddt;
344 /* Panel color depth defined here */
345 u16 panel_color_depth;
346 /* LVDS panel type bits stored here */
347 u32 dps_panel_type_bits;
348 /* LVDS backlight control type bits stored here */
349 u32 blt_control_type_bits;
350} __packed;
351
352/* LFP pointer table contains entries to the struct below */
353struct bdb_lvds_lfp_data_ptr {
354 u16 fp_timing_offset; /* offsets are from start of bdb */
355 u8 fp_table_size;
356 u16 dvo_timing_offset;
357 u8 dvo_table_size;
358 u16 panel_pnp_id_offset;
359 u8 pnp_table_size;
360} __packed;
361
362struct bdb_lvds_lfp_data_ptrs {
363 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
364 struct bdb_lvds_lfp_data_ptr ptr[16];
365} __packed;
366
367/* LFP data has 3 blocks per entry */
368struct lvds_fp_timing {
369 u16 x_res;
370 u16 y_res;
371 u32 lvds_reg;
372 u32 lvds_reg_val;
373 u32 pp_on_reg;
374 u32 pp_on_reg_val;
375 u32 pp_off_reg;
376 u32 pp_off_reg_val;
377 u32 pp_cycle_reg;
378 u32 pp_cycle_reg_val;
379 u32 pfit_reg;
380 u32 pfit_reg_val;
381 u16 terminator;
382} __packed;
383
384struct lvds_dvo_timing {
385 u16 clock; /**< In 10khz */
386 u8 hactive_lo;
387 u8 hblank_lo;
388 u8 hblank_hi:4;
389 u8 hactive_hi:4;
390 u8 vactive_lo;
391 u8 vblank_lo;
392 u8 vblank_hi:4;
393 u8 vactive_hi:4;
394 u8 hsync_off_lo;
395 u8 hsync_pulse_width;
396 u8 vsync_pulse_width:4;
397 u8 vsync_off:4;
398 u8 rsvd0:6;
399 u8 hsync_off_hi:2;
400 u8 h_image;
401 u8 v_image;
402 u8 max_hv;
403 u8 h_border;
404 u8 v_border;
405 u8 rsvd1:3;
406 u8 digital:2;
407 u8 vsync_positive:1;
408 u8 hsync_positive:1;
409 u8 rsvd2:1;
410} __packed;
411
412struct lvds_pnp_id {
413 u16 mfg_name;
414 u16 product_code;
415 u32 serial;
416 u8 mfg_week;
417 u8 mfg_year;
418} __packed;
419
420struct bdb_lvds_lfp_data_entry {
421 struct lvds_fp_timing fp_timing;
422 struct lvds_dvo_timing dvo_timing;
423 struct lvds_pnp_id pnp_id;
424} __packed;
425
426struct bdb_lvds_lfp_data {
427 struct bdb_lvds_lfp_data_entry data[16];
428} __packed;
429
430#define BDB_BACKLIGHT_TYPE_NONE 0
431#define BDB_BACKLIGHT_TYPE_PWM 2
432
433struct bdb_lfp_backlight_data_entry {
434 u8 type:2;
435 u8 active_low_pwm:1;
436 u8 obsolete1:5;
437 u16 pwm_freq_hz;
438 u8 min_brightness;
439 u8 obsolete2;
440 u8 obsolete3;
441} __packed;
442
443struct bdb_lfp_backlight_data {
444 u8 entry_size;
445 struct bdb_lfp_backlight_data_entry data[16];
446 u8 level[16];
447} __packed;
448
449struct aimdb_header {
450 char signature[16];
451 char oem_device[20];
452 u16 aimdb_version;
453 u16 aimdb_header_size;
454 u16 aimdb_size;
455} __packed;
456
457struct aimdb_block {
458 u8 aimdb_id;
459 u16 aimdb_size;
460} __packed;
461
462struct vch_panel_data {
463 u16 fp_timing_offset;
464 u8 fp_timing_size;
465 u16 dvo_timing_offset;
466 u8 dvo_timing_size;
467 u16 text_fitting_offset;
468 u8 text_fitting_size;
469 u16 graphics_fitting_offset;
470 u8 graphics_fitting_size;
471} __packed;
472
473struct vch_bdb_22 {
474 struct aimdb_block aimdb_block;
475 struct vch_panel_data panels[16];
476} __packed;
477
478struct bdb_sdvo_lvds_options {
479 u8 panel_backlight;
480 u8 h40_set_panel_type;
481 u8 panel_type;
482 u8 ssc_clk_freq;
483 u16 als_low_trip;
484 u16 als_high_trip;
485 u8 sclalarcoeff_tab_row_num;
486 u8 sclalarcoeff_tab_row_size;
487 u8 coefficient[8];
488 u8 panel_misc_bits_1;
489 u8 panel_misc_bits_2;
490 u8 panel_misc_bits_3;
491 u8 panel_misc_bits_4;
492} __packed;
493
494
495#define BDB_DRIVER_FEATURE_NO_LVDS 0
496#define BDB_DRIVER_FEATURE_INT_LVDS 1
497#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
498#define BDB_DRIVER_FEATURE_EDP 3
499
500struct bdb_driver_features {
501 u8 boot_dev_algorithm:1;
502 u8 block_display_switch:1;
503 u8 allow_display_switch:1;
504 u8 hotplug_dvo:1;
505 u8 dual_view_zoom:1;
506 u8 int15h_hook:1;
507 u8 sprite_in_clone:1;
508 u8 primary_lfp_id:1;
509
510 u16 boot_mode_x;
511 u16 boot_mode_y;
512 u8 boot_mode_bpp;
513 u8 boot_mode_refresh;
514
515 u16 enable_lfp_primary:1;
516 u16 selective_mode_pruning:1;
517 u16 dual_frequency:1;
518 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
519 u16 nt_clone_support:1;
520 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
521 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
522 u16 cui_aspect_scaling:1;
523 u16 preserve_aspect_ratio:1;
524 u16 sdvo_device_power_down:1;
525 u16 crt_hotplug:1;
526 u16 lvds_config:2;
527 u16 tv_hotplug:1;
528 u16 hdmi_config:2;
529
530 u8 static_display:1;
531 u8 reserved2:7;
532 u16 legacy_crt_max_x;
533 u16 legacy_crt_max_y;
534 u8 legacy_crt_max_refresh;
535
536 u8 hdmi_termination;
537 u8 custom_vbt_version;
538 /* Driver features data block */
539 u16 rmpm_enabled:1;
540 u16 s2ddt_enabled:1;
541 u16 dpst_enabled:1;
542 u16 bltclt_enabled:1;
543 u16 adb_enabled:1;
544 u16 drrs_enabled:1;
545 u16 grs_enabled:1;
546 u16 gpmt_enabled:1;
547 u16 tbt_enabled:1;
548 u16 psr_enabled:1;
549 u16 ips_enabled:1;
550 u16 reserved3:4;
551 u16 pc_feature_valid:1;
552} __packed;
553
554#define EDP_18BPP 0
555#define EDP_24BPP 1
556#define EDP_30BPP 2
557#define EDP_RATE_1_62 0
558#define EDP_RATE_2_7 1
559#define EDP_LANE_1 0
560#define EDP_LANE_2 1
561#define EDP_LANE_4 3
562#define EDP_PREEMPHASIS_NONE 0
563#define EDP_PREEMPHASIS_3_5dB 1
564#define EDP_PREEMPHASIS_6dB 2
565#define EDP_PREEMPHASIS_9_5dB 3
566#define EDP_VSWING_0_4V 0
567#define EDP_VSWING_0_6V 1
568#define EDP_VSWING_0_8V 2
569#define EDP_VSWING_1_2V 3
570
571
572struct edp_link_params {
573 u8 rate:4;
574 u8 lanes:4;
575 u8 preemphasis:4;
576 u8 vswing:4;
577} __packed;
578
579struct bdb_edp {
580 struct edp_power_seq power_seqs[16];
581 u32 color_depth;
582 struct edp_link_params link_params[16];
583 u32 sdrrs_msa_timing_delay;
584
585 /* ith bit indicates enabled/disabled for (i+1)th panel */
586 u16 edp_s3d_feature;
587 u16 edp_t3_optimization;
588 u64 edp_vswing_preemph; /* v173 */
589} __packed;
590
591struct psr_table {
592 /* Feature bits */
593 u8 full_link:1;
594 u8 require_aux_to_wakeup:1;
595 u8 feature_bits_rsvd:6;
596
597 /* Wait times */
598 u8 idle_frames:4;
599 u8 lines_to_wait:3;
600 u8 wait_times_rsvd:1;
601
602 /* TP wake up time in multiple of 100 */
603 u16 tp1_wakeup_time;
604 u16 tp2_tp3_wakeup_time;
605} __packed;
606
607struct bdb_psr {
608 struct psr_table psr_table[16];
609} __packed;
610
611/*
612 * Driver<->VBIOS interaction occurs through scratch bits in
613 * GR18 & SWF*.
614 */
615
616/* GR18 bits are set on display switch and hotkey events */
617#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
618#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
619#define GR18_HK_NONE (0x0<<3)
620#define GR18_HK_LFP_STRETCH (0x1<<3)
621#define GR18_HK_TOGGLE_DISP (0x2<<3)
622#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
623#define GR18_HK_POPUP_DISABLED (0x6<<3)
624#define GR18_HK_POPUP_ENABLED (0x7<<3)
625#define GR18_HK_PFIT (0x8<<3)
626#define GR18_HK_APM_CHANGE (0xa<<3)
627#define GR18_HK_MULTIPLE (0xc<<3)
628#define GR18_USER_INT_EN (1<<2)
629#define GR18_A0000_FLUSH_EN (1<<1)
630#define GR18_SMM_EN (1<<0)
631
632/* Set by driver, cleared by VBIOS */
633#define SWF00_YRES_SHIFT 16
634#define SWF00_XRES_SHIFT 0
635#define SWF00_RES_MASK 0xffff
636
637/* Set by VBIOS at boot time and driver at runtime */
638#define SWF01_TV2_FORMAT_SHIFT 8
639#define SWF01_TV1_FORMAT_SHIFT 0
640#define SWF01_TV_FORMAT_MASK 0xffff
641
642#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
643#define SWF10_GTT_OVERRIDE_EN (1<<28)
644#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
645#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
646#define SWF10_OLD_TOGGLE 0x0
647#define SWF10_TOGGLE_LIST_1 0x1
648#define SWF10_TOGGLE_LIST_2 0x2
649#define SWF10_TOGGLE_LIST_3 0x3
650#define SWF10_TOGGLE_LIST_4 0x4
651#define SWF10_PANNING_EN (1<<23)
652#define SWF10_DRIVER_LOADED (1<<22)
653#define SWF10_EXTENDED_DESKTOP (1<<21)
654#define SWF10_EXCLUSIVE_MODE (1<<20)
655#define SWF10_OVERLAY_EN (1<<19)
656#define SWF10_PLANEB_HOLDOFF (1<<18)
657#define SWF10_PLANEA_HOLDOFF (1<<17)
658#define SWF10_VGA_HOLDOFF (1<<16)
659#define SWF10_ACTIVE_DISP_MASK 0xffff
660#define SWF10_PIPEB_LFP2 (1<<15)
661#define SWF10_PIPEB_EFP2 (1<<14)
662#define SWF10_PIPEB_TV2 (1<<13)
663#define SWF10_PIPEB_CRT2 (1<<12)
664#define SWF10_PIPEB_LFP (1<<11)
665#define SWF10_PIPEB_EFP (1<<10)
666#define SWF10_PIPEB_TV (1<<9)
667#define SWF10_PIPEB_CRT (1<<8)
668#define SWF10_PIPEA_LFP2 (1<<7)
669#define SWF10_PIPEA_EFP2 (1<<6)
670#define SWF10_PIPEA_TV2 (1<<5)
671#define SWF10_PIPEA_CRT2 (1<<4)
672#define SWF10_PIPEA_LFP (1<<3)
673#define SWF10_PIPEA_EFP (1<<2)
674#define SWF10_PIPEA_TV (1<<1)
675#define SWF10_PIPEA_CRT (1<<0)
676
677#define SWF11_MEMORY_SIZE_SHIFT 16
678#define SWF11_SV_TEST_EN (1<<15)
679#define SWF11_IS_AGP (1<<14)
680#define SWF11_DISPLAY_HOLDOFF (1<<13)
681#define SWF11_DPMS_REDUCED (1<<12)
682#define SWF11_IS_VBE_MODE (1<<11)
683#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
684#define SWF11_DPMS_MASK 0x07
685#define SWF11_DPMS_OFF (1<<2)
686#define SWF11_DPMS_SUSPEND (1<<1)
687#define SWF11_DPMS_STANDBY (1<<0)
688#define SWF11_DPMS_ON 0
689
690#define SWF14_GFX_PFIT_EN (1<<31)
691#define SWF14_TEXT_PFIT_EN (1<<30)
692#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
693#define SWF14_POPUP_EN (1<<28)
694#define SWF14_DISPLAY_HOLDOFF (1<<27)
695#define SWF14_DISP_DETECT_EN (1<<26)
696#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
697#define SWF14_DRIVER_STATUS (1<<24)
698#define SWF14_OS_TYPE_WIN9X (1<<23)
699#define SWF14_OS_TYPE_WINNT (1<<22)
700/* 21:19 rsvd */
701#define SWF14_PM_TYPE_MASK 0x00070000
702#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
703#define SWF14_PM_ACPI (0x3 << 16)
704#define SWF14_PM_APM_12 (0x2 << 16)
705#define SWF14_PM_APM_11 (0x1 << 16)
706#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
707 /* if GR18 indicates a display switch */
708#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
709#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
710#define SWF14_DS_PIPEB_TV2_EN (1<<13)
711#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
712#define SWF14_DS_PIPEB_LFP_EN (1<<11)
713#define SWF14_DS_PIPEB_EFP_EN (1<<10)
714#define SWF14_DS_PIPEB_TV_EN (1<<9)
715#define SWF14_DS_PIPEB_CRT_EN (1<<8)
716#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
717#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
718#define SWF14_DS_PIPEA_TV2_EN (1<<5)
719#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
720#define SWF14_DS_PIPEA_LFP_EN (1<<3)
721#define SWF14_DS_PIPEA_EFP_EN (1<<2)
722#define SWF14_DS_PIPEA_TV_EN (1<<1)
723#define SWF14_DS_PIPEA_CRT_EN (1<<0)
724 /* if GR18 indicates a panel fitting request */
725#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
726 /* if GR18 indicates an APM change request */
727#define SWF14_APM_HIBERNATE 0x4
728#define SWF14_APM_SUSPEND 0x3
729#define SWF14_APM_STANDBY 0x1
730#define SWF14_APM_RESTORE 0x0
731
732/* Add the device class for LFP, TV, HDMI */
733#define DEVICE_TYPE_INT_LFP 0x1022
734#define DEVICE_TYPE_INT_TV 0x1009
735#define DEVICE_TYPE_HDMI 0x60D2
736#define DEVICE_TYPE_DP 0x68C6
737#define DEVICE_TYPE_eDP 0x78C6
738
739#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
740#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
741#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
742#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
743#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
744#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
745#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
746#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
747#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
748#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
749#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
750#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
751#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
752#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
753#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
754
755/*
756 * Bits we care about when checking for DEVICE_TYPE_eDP
757 * Depending on the system, the other bits may or may not
758 * be set for eDP outputs.
759 */
760#define DEVICE_TYPE_eDP_BITS \
761 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
762 DEVICE_TYPE_MIPI_OUTPUT | \
763 DEVICE_TYPE_COMPOSITE_OUTPUT | \
764 DEVICE_TYPE_DUAL_CHANNEL | \
765 DEVICE_TYPE_LVDS_SINGALING | \
766 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
767 DEVICE_TYPE_VIDEO_SIGNALING | \
768 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
769 DEVICE_TYPE_ANALOG_OUTPUT)
770
771/* define the DVO port for HDMI output type */
772#define DVO_B 1
773#define DVO_C 2
774#define DVO_D 3
775
776/* Possible values for the "DVO Port" field for versions >= 155: */
777#define DVO_PORT_HDMIA 0
778#define DVO_PORT_HDMIB 1
779#define DVO_PORT_HDMIC 2
780#define DVO_PORT_HDMID 3
781#define DVO_PORT_LVDS 4
782#define DVO_PORT_TV 5
783#define DVO_PORT_CRT 6
784#define DVO_PORT_DPB 7
785#define DVO_PORT_DPC 8
786#define DVO_PORT_DPD 9
787#define DVO_PORT_DPA 10
788#define DVO_PORT_DPE 11
789#define DVO_PORT_HDMIE 12
790#define DVO_PORT_MIPIA 21
791#define DVO_PORT_MIPIB 22
792#define DVO_PORT_MIPIC 23
793#define DVO_PORT_MIPID 24
794
795/* Block 52 contains MIPI configuration block
796 * 6 * bdb_mipi_config, followed by 6 pps data block
797 * block below
798 */
799#define MAX_MIPI_CONFIGURATIONS 6
800
801struct bdb_mipi_config {
802 struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
803 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
804} __packed;
805
806/* Block 53 contains MIPI sequences as needed by the panel
807 * for enabling it. This block can be variable in size and
808 * can be maximum of 6 blocks
809 */
810struct bdb_mipi_sequence {
811 u8 version;
812 u8 data[0];
813} __packed;
814
815enum mipi_gpio_pin_index {
816 MIPI_GPIO_UNDEFINED = 0,
817 MIPI_GPIO_PANEL_ENABLE,
818 MIPI_GPIO_BL_ENABLE,
819 MIPI_GPIO_PWM_ENABLE,
820 MIPI_GPIO_RESET_N,
821 MIPI_GPIO_PWR_DOWN_R,
822 MIPI_GPIO_STDBY_RST_N,
823 MIPI_GPIO_MAX
824};
825
826#endif /* _INTEL_VBT_DEFS_H_ */
Linux kernel - Deliverables
This page took 0.072119 seconds and 5 git commands to generate.