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3d1b35a3 AY |
1 | /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. |
2 | * | |
b21f4b65 | 3 | * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now) |
3d1b35a3 AY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #include <linux/module.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/component.h> | |
12 | #include <linux/mfd/syscon.h> | |
13 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
b21f4b65 | 14 | #include <drm/bridge/dw_hdmi.h> |
3d1b35a3 AY |
15 | #include <video/imx-ipu-v3.h> |
16 | #include <linux/regmap.h> | |
17 | #include <drm/drm_of.h> | |
18 | #include <drm/drmP.h> | |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_edid.h> | |
21 | #include <drm/drm_encoder_slave.h> | |
22 | ||
23 | #include "imx-drm.h" | |
3d1b35a3 | 24 | |
b21f4b65 | 25 | struct imx_hdmi { |
3d1b35a3 AY |
26 | struct device *dev; |
27 | struct drm_encoder encoder; | |
28 | struct regmap *regmap; | |
29 | }; | |
30 | ||
b21f4b65 | 31 | static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = { |
aaa757a0 AY |
32 | { |
33 | 45250000, { | |
34 | { 0x01e0, 0x0000 }, | |
35 | { 0x21e1, 0x0000 }, | |
36 | { 0x41e2, 0x0000 } | |
37 | }, | |
38 | }, { | |
39 | 92500000, { | |
40 | { 0x0140, 0x0005 }, | |
41 | { 0x2141, 0x0005 }, | |
42 | { 0x4142, 0x0005 }, | |
43 | }, | |
44 | }, { | |
45 | 148500000, { | |
46 | { 0x00a0, 0x000a }, | |
47 | { 0x20a1, 0x000a }, | |
48 | { 0x40a2, 0x000a }, | |
49 | }, | |
50 | }, { | |
a5f4185c | 51 | 216000000, { |
aaa757a0 AY |
52 | { 0x00a0, 0x000a }, |
53 | { 0x2001, 0x000f }, | |
54 | { 0x4002, 0x000f }, | |
55 | }, | |
a5f4185c LS |
56 | }, { |
57 | ~0UL, { | |
58 | { 0x0000, 0x0000 }, | |
59 | { 0x0000, 0x0000 }, | |
60 | { 0x0000, 0x0000 }, | |
61 | }, | |
aaa757a0 AY |
62 | } |
63 | }; | |
64 | ||
b21f4b65 | 65 | static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { |
aaa757a0 AY |
66 | /* pixelclk bpp8 bpp10 bpp12 */ |
67 | { | |
68 | 54000000, { 0x091c, 0x091c, 0x06dc }, | |
69 | }, { | |
70 | 58400000, { 0x091c, 0x06dc, 0x06dc }, | |
71 | }, { | |
72 | 72000000, { 0x06dc, 0x06dc, 0x091c }, | |
73 | }, { | |
74 | 74250000, { 0x06dc, 0x0b5c, 0x091c }, | |
75 | }, { | |
76 | 118800000, { 0x091c, 0x091c, 0x06dc }, | |
77 | }, { | |
78 | 216000000, { 0x06dc, 0x0b5c, 0x091c }, | |
6e8958ec PZ |
79 | }, { |
80 | ~0UL, { 0x0000, 0x0000, 0x0000 }, | |
81 | }, | |
aaa757a0 AY |
82 | }; |
83 | ||
36b8ae0d RK |
84 | /* |
85 | * Resistance term 133Ohm Cfg | |
86 | * PREEMP config 0.00 | |
87 | * TX/CK level 10 | |
88 | */ | |
034705a4 YY |
89 | static const struct dw_hdmi_phy_config imx_phy_config[] = { |
90 | /*pixelclk symbol term vlev */ | |
a5f4185c | 91 | { 216000000, 0x800d, 0x0005, 0x01ad}, |
034705a4 | 92 | { ~0UL, 0x0000, 0x0000, 0x0000} |
aaa757a0 AY |
93 | }; |
94 | ||
b21f4b65 | 95 | static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi) |
3d1b35a3 AY |
96 | { |
97 | struct device_node *np = hdmi->dev->of_node; | |
98 | ||
99 | hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
100 | if (IS_ERR(hdmi->regmap)) { | |
101 | dev_err(hdmi->dev, "Unable to get gpr\n"); | |
102 | return PTR_ERR(hdmi->regmap); | |
103 | } | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
b21f4b65 | 108 | static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder) |
3d1b35a3 AY |
109 | { |
110 | } | |
111 | ||
b21f4b65 AY |
112 | static bool dw_hdmi_imx_encoder_mode_fixup(struct drm_encoder *encoder, |
113 | const struct drm_display_mode *mode, | |
114 | struct drm_display_mode *adj_mode) | |
3d1b35a3 AY |
115 | { |
116 | return true; | |
117 | } | |
118 | ||
b21f4b65 AY |
119 | static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder, |
120 | struct drm_display_mode *mode, | |
121 | struct drm_display_mode *adj_mode) | |
3d1b35a3 AY |
122 | { |
123 | } | |
124 | ||
b21f4b65 | 125 | static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder) |
3d1b35a3 | 126 | { |
b21f4b65 | 127 | struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); |
3d1b35a3 AY |
128 | int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); |
129 | ||
130 | regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, | |
131 | IMX6Q_GPR3_HDMI_MUX_CTL_MASK, | |
132 | mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); | |
133 | } | |
134 | ||
b21f4b65 | 135 | static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder) |
3d1b35a3 | 136 | { |
2872c807 | 137 | imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_RGB888_1X24); |
3d1b35a3 AY |
138 | } |
139 | ||
b21f4b65 AY |
140 | static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = { |
141 | .mode_fixup = dw_hdmi_imx_encoder_mode_fixup, | |
142 | .mode_set = dw_hdmi_imx_encoder_mode_set, | |
143 | .prepare = dw_hdmi_imx_encoder_prepare, | |
144 | .commit = dw_hdmi_imx_encoder_commit, | |
145 | .disable = dw_hdmi_imx_encoder_disable, | |
3d1b35a3 AY |
146 | }; |
147 | ||
b21f4b65 | 148 | static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { |
3d1b35a3 AY |
149 | .destroy = drm_encoder_cleanup, |
150 | }; | |
151 | ||
081c80e8 PZ |
152 | static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con, |
153 | struct drm_display_mode *mode) | |
154 | { | |
155 | if (mode->clock < 13500) | |
156 | return MODE_CLOCK_LOW; | |
a5f4185c LS |
157 | /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */ |
158 | if (mode->clock > 216000) | |
081c80e8 PZ |
159 | return MODE_CLOCK_HIGH; |
160 | ||
161 | return MODE_OK; | |
162 | } | |
163 | ||
164 | static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con, | |
165 | struct drm_display_mode *mode) | |
166 | { | |
167 | if (mode->clock < 13500) | |
168 | return MODE_CLOCK_LOW; | |
a5f4185c LS |
169 | /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ |
170 | if (mode->clock > 216000) | |
081c80e8 PZ |
171 | return MODE_CLOCK_HIGH; |
172 | ||
173 | return MODE_OK; | |
174 | } | |
175 | ||
b21f4b65 | 176 | static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { |
081c80e8 PZ |
177 | .mpll_cfg = imx_mpll_cfg, |
178 | .cur_ctr = imx_cur_ctr, | |
034705a4 | 179 | .phy_config = imx_phy_config, |
081c80e8 PZ |
180 | .dev_type = IMX6Q_HDMI, |
181 | .mode_valid = imx6q_hdmi_mode_valid, | |
3d1b35a3 AY |
182 | }; |
183 | ||
b21f4b65 | 184 | static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { |
aaa757a0 AY |
185 | .mpll_cfg = imx_mpll_cfg, |
186 | .cur_ctr = imx_cur_ctr, | |
034705a4 | 187 | .phy_config = imx_phy_config, |
3d1b35a3 | 188 | .dev_type = IMX6DL_HDMI, |
081c80e8 | 189 | .mode_valid = imx6dl_hdmi_mode_valid, |
3d1b35a3 AY |
190 | }; |
191 | ||
b21f4b65 | 192 | static const struct of_device_id dw_hdmi_imx_dt_ids[] = { |
3d1b35a3 AY |
193 | { .compatible = "fsl,imx6q-hdmi", |
194 | .data = &imx6q_hdmi_drv_data | |
195 | }, { | |
196 | .compatible = "fsl,imx6dl-hdmi", | |
197 | .data = &imx6dl_hdmi_drv_data | |
198 | }, | |
199 | {}, | |
200 | }; | |
b21f4b65 | 201 | MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids); |
3d1b35a3 | 202 | |
b21f4b65 AY |
203 | static int dw_hdmi_imx_bind(struct device *dev, struct device *master, |
204 | void *data) | |
3d1b35a3 AY |
205 | { |
206 | struct platform_device *pdev = to_platform_device(dev); | |
b21f4b65 | 207 | const struct dw_hdmi_plat_data *plat_data; |
3d1b35a3 AY |
208 | const struct of_device_id *match; |
209 | struct drm_device *drm = data; | |
210 | struct drm_encoder *encoder; | |
b21f4b65 | 211 | struct imx_hdmi *hdmi; |
3d1b35a3 AY |
212 | struct resource *iores; |
213 | int irq; | |
214 | int ret; | |
215 | ||
216 | if (!pdev->dev.of_node) | |
217 | return -ENODEV; | |
218 | ||
219 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); | |
220 | if (!hdmi) | |
221 | return -ENOMEM; | |
222 | ||
b21f4b65 | 223 | match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node); |
3d1b35a3 AY |
224 | plat_data = match->data; |
225 | hdmi->dev = &pdev->dev; | |
226 | encoder = &hdmi->encoder; | |
227 | ||
228 | irq = platform_get_irq(pdev, 0); | |
229 | if (irq < 0) | |
230 | return irq; | |
231 | ||
232 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
233 | if (!iores) | |
234 | return -ENXIO; | |
235 | ||
236 | platform_set_drvdata(pdev, hdmi); | |
237 | ||
238 | encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); | |
239 | /* | |
240 | * If we failed to find the CRTC(s) which this encoder is | |
241 | * supposed to be connected to, it's because the CRTC has | |
242 | * not been registered yet. Defer probing, and hope that | |
243 | * the required CRTC is added later. | |
244 | */ | |
245 | if (encoder->possible_crtcs == 0) | |
246 | return -EPROBE_DEFER; | |
247 | ||
b21f4b65 | 248 | ret = dw_hdmi_imx_parse_dt(hdmi); |
3d1b35a3 AY |
249 | if (ret < 0) |
250 | return ret; | |
251 | ||
b21f4b65 AY |
252 | drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs); |
253 | drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, | |
13a3d91f | 254 | DRM_MODE_ENCODER_TMDS, NULL); |
3d1b35a3 | 255 | |
b21f4b65 | 256 | return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); |
3d1b35a3 AY |
257 | } |
258 | ||
b21f4b65 AY |
259 | static void dw_hdmi_imx_unbind(struct device *dev, struct device *master, |
260 | void *data) | |
3d1b35a3 | 261 | { |
b21f4b65 | 262 | return dw_hdmi_unbind(dev, master, data); |
3d1b35a3 AY |
263 | } |
264 | ||
b21f4b65 AY |
265 | static const struct component_ops dw_hdmi_imx_ops = { |
266 | .bind = dw_hdmi_imx_bind, | |
267 | .unbind = dw_hdmi_imx_unbind, | |
3d1b35a3 AY |
268 | }; |
269 | ||
b21f4b65 | 270 | static int dw_hdmi_imx_probe(struct platform_device *pdev) |
3d1b35a3 | 271 | { |
b21f4b65 | 272 | return component_add(&pdev->dev, &dw_hdmi_imx_ops); |
3d1b35a3 AY |
273 | } |
274 | ||
b21f4b65 | 275 | static int dw_hdmi_imx_remove(struct platform_device *pdev) |
3d1b35a3 | 276 | { |
b21f4b65 | 277 | component_del(&pdev->dev, &dw_hdmi_imx_ops); |
3d1b35a3 AY |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
b21f4b65 AY |
282 | static struct platform_driver dw_hdmi_imx_platform_driver = { |
283 | .probe = dw_hdmi_imx_probe, | |
284 | .remove = dw_hdmi_imx_remove, | |
3d1b35a3 | 285 | .driver = { |
b21f4b65 AY |
286 | .name = "dwhdmi-imx", |
287 | .of_match_table = dw_hdmi_imx_dt_ids, | |
3d1b35a3 AY |
288 | }, |
289 | }; | |
290 | ||
b21f4b65 | 291 | module_platform_driver(dw_hdmi_imx_platform_driver); |
3d1b35a3 AY |
292 | |
293 | MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); | |
294 | MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); | |
295 | MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension"); | |
296 | MODULE_LICENSE("GPL"); | |
b21f4b65 | 297 | MODULE_ALIAS("platform:dwhdmi-imx"); |