[deliverable/linux.git] / drivers / gpu / drm / imx / dw_hdmi-imx.c

/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
 *
 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <drm/bridge/dw_hdmi.h>
#include <video/imx-ipu-v3.h>
#include <linux/regmap.h>
#include <drm/drm_of.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder_slave.h>

#include "imx-drm.h"

#define imx_enc_to_imx_hdmi(x) container_of(x, struct imx_hdmi, imx_encoder)

struct imx_hdmi {
	struct device *dev;
	struct imx_drm_encoder imx_encoder;
	struct regmap *regmap;
};

static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
	{
		45250000, {
			{ 0x01e0, 0x0000 },
			{ 0x21e1, 0x0000 },
			{ 0x41e2, 0x0000 }
		},
	}, {
		92500000, {
			{ 0x0140, 0x0005 },
			{ 0x2141, 0x0005 },
			{ 0x4142, 0x0005 },
	},
	}, {
		148500000, {
			{ 0x00a0, 0x000a },
			{ 0x20a1, 0x000a },
			{ 0x40a2, 0x000a },
		},
	}, {
		216000000, {
			{ 0x00a0, 0x000a },
			{ 0x2001, 0x000f },
			{ 0x4002, 0x000f },
		},
	}, {
		~0UL, {
			{ 0x0000, 0x0000 },
			{ 0x0000, 0x0000 },
			{ 0x0000, 0x0000 },
		},
	}
};

static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
	/*      pixelclk     bpp8    bpp10   bpp12 */
	{
		54000000, { 0x091c, 0x091c, 0x06dc },
	}, {
		58400000, { 0x091c, 0x06dc, 0x06dc },
	}, {
		72000000, { 0x06dc, 0x06dc, 0x091c },
	}, {
		74250000, { 0x06dc, 0x0b5c, 0x091c },
	}, {
		118800000, { 0x091c, 0x091c, 0x06dc },
	}, {
		216000000, { 0x06dc, 0x0b5c, 0x091c },
	}, {
		~0UL, { 0x0000, 0x0000, 0x0000 },
	},
};

/*
 * Resistance term 133Ohm Cfg
 * PREEMP config 0.00
 * TX/CK level 10
 */
static const struct dw_hdmi_phy_config imx_phy_config[] = {
	/*pixelclk   symbol   term   vlev */
	{ 216000000, 0x800d, 0x0005, 0x01ad},
	{ ~0UL,      0x0000, 0x0000, 0x0000}
};

static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
{
	struct device_node *np = hdmi->dev->of_node;

	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	if (IS_ERR(hdmi->regmap)) {
		dev_err(hdmi->dev, "Unable to get gpr\n");
		return PTR_ERR(hdmi->regmap);
	}

	return 0;
}

static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
{
}

static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
{
	struct imx_drm_encoder *imx_encoder = enc_to_imx_enc(encoder);
	struct imx_hdmi *hdmi = imx_enc_to_imx_hdmi(imx_encoder);
	int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);

	regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
			   IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
			   mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
}

static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
	.enable     = dw_hdmi_imx_encoder_enable,
	.disable    = dw_hdmi_imx_encoder_disable,
};

static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
	.destroy = drm_encoder_cleanup,
};

static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
						  struct drm_display_mode *mode)
{
	if (mode->clock < 13500)
		return MODE_CLOCK_LOW;
	/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
	if (mode->clock > 216000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
						   struct drm_display_mode *mode)
{
	if (mode->clock < 13500)
		return MODE_CLOCK_LOW;
	/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
	if (mode->clock > 216000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
	.mpll_cfg   = imx_mpll_cfg,
	.cur_ctr    = imx_cur_ctr,
	.phy_config = imx_phy_config,
	.dev_type   = IMX6Q_HDMI,
	.mode_valid = imx6q_hdmi_mode_valid,
};

static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
	.mpll_cfg = imx_mpll_cfg,
	.cur_ctr  = imx_cur_ctr,
	.phy_config = imx_phy_config,
	.dev_type = IMX6DL_HDMI,
	.mode_valid = imx6dl_hdmi_mode_valid,
};

static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
	{ .compatible = "fsl,imx6q-hdmi",
	  .data = &imx6q_hdmi_drv_data
	}, {
	  .compatible = "fsl,imx6dl-hdmi",
	  .data = &imx6dl_hdmi_drv_data
	},
	{},
};
MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);

static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	const struct dw_hdmi_plat_data *plat_data;
	const struct of_device_id *match;
	struct drm_device *drm = data;
	struct drm_encoder *encoder;
	struct imx_hdmi *hdmi;
	struct resource *iores;
	int irq;
	int ret;

	if (!pdev->dev.of_node)
		return -ENODEV;

	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
	if (!hdmi)
		return -ENOMEM;

	match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
	plat_data = match->data;
	hdmi->dev = &pdev->dev;
	encoder = &hdmi->imx_encoder.encoder;
	hdmi->imx_encoder.bus_format = MEDIA_BUS_FMT_RGB888_1X24;
	hdmi->imx_encoder.di_hsync_pin = 2;
	hdmi->imx_encoder.di_vsync_pin = 3;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores)
		return -ENXIO;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
	/*
	 * If we failed to find the CRTC(s) which this encoder is
	 * supposed to be connected to, it's because the CRTC has
	 * not been registered yet.  Defer probing, and hope that
	 * the required CRTC is added later.
	 */
	if (encoder->possible_crtcs == 0)
		return -EPROBE_DEFER;

	ret = dw_hdmi_imx_parse_dt(hdmi);
	if (ret < 0)
		return ret;

	drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
	drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
			 DRM_MODE_ENCODER_TMDS, NULL);

	ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);

	/*
	 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
	 * which would have called the encoder cleanup.  Do it manually.
	 */
	if (ret)
		drm_encoder_cleanup(encoder);

	return ret;
}

static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
			       void *data)
{
	return dw_hdmi_unbind(dev, master, data);
}

static const struct component_ops dw_hdmi_imx_ops = {
	.bind	= dw_hdmi_imx_bind,
	.unbind	= dw_hdmi_imx_unbind,
};

static int dw_hdmi_imx_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &dw_hdmi_imx_ops);
}

static int dw_hdmi_imx_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &dw_hdmi_imx_ops);

	return 0;
}

static struct platform_driver dw_hdmi_imx_platform_driver = {
	.probe  = dw_hdmi_imx_probe,
	.remove = dw_hdmi_imx_remove,
	.driver = {
		.name = "dwhdmi-imx",
		.of_match_table = dw_hdmi_imx_dt_ids,
	},
};

module_platform_driver(dw_hdmi_imx_platform_driver);

MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:dwhdmi-imx");
Commit	Line	Data
3d1b35a3 AY	1	/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3d1b35a3 AY	2	*
b21f4b65	3	* derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
3d1b35a3 AY	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9	#include <linux/module.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/component.h>
	12	#include <linux/mfd/syscon.h>
	13	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
b21f4b65	14	#include <drm/bridge/dw_hdmi.h>
3d1b35a3 AY	15	#include <video/imx-ipu-v3.h>
	16	#include <linux/regmap.h>
	17	#include <drm/drm_of.h>
	18	#include <drm/drmP.h>
	19	#include <drm/drm_crtc_helper.h>
	20	#include <drm/drm_edid.h>
	21	#include <drm/drm_encoder_slave.h>
	22
	23	#include "imx-drm.h"
3d1b35a3	24
032003c5 LY	25	#define imx_enc_to_imx_hdmi(x) container_of(x, struct imx_hdmi, imx_encoder)
032003c5 LY	26
b21f4b65	27	struct imx_hdmi {
3d1b35a3	28	struct device *dev;
032003c5	29	struct imx_drm_encoder imx_encoder;
3d1b35a3 AY	30	struct regmap *regmap;
	31	};
	32
b21f4b65	33	static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
aaa757a0 AY	34	{
	35	45250000, {
	36	{ 0x01e0, 0x0000 },
	37	{ 0x21e1, 0x0000 },
	38	{ 0x41e2, 0x0000 }
	39	},
	40	}, {
	41	92500000, {
	42	{ 0x0140, 0x0005 },
	43	{ 0x2141, 0x0005 },
	44	{ 0x4142, 0x0005 },
	45	},
	46	}, {
	47	148500000, {
	48	{ 0x00a0, 0x000a },
	49	{ 0x20a1, 0x000a },
	50	{ 0x40a2, 0x000a },
	51	},
	52	}, {
a5f4185c	53	216000000, {
aaa757a0 AY	54	{ 0x00a0, 0x000a },
	55	{ 0x2001, 0x000f },
	56	{ 0x4002, 0x000f },
	57	},
a5f4185c LS	58	}, {
	59	~0UL, {
	60	{ 0x0000, 0x0000 },
	61	{ 0x0000, 0x0000 },
	62	{ 0x0000, 0x0000 },
	63	},
aaa757a0 AY	64	}
	65	};
	66
b21f4b65	67	static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
aaa757a0 AY	68	/* pixelclk bpp8 bpp10 bpp12 */
	69	{
	70	54000000, { 0x091c, 0x091c, 0x06dc },
	71	}, {
	72	58400000, { 0x091c, 0x06dc, 0x06dc },
	73	}, {
	74	72000000, { 0x06dc, 0x06dc, 0x091c },
	75	}, {
	76	74250000, { 0x06dc, 0x0b5c, 0x091c },
	77	}, {
	78	118800000, { 0x091c, 0x091c, 0x06dc },
	79	}, {
	80	216000000, { 0x06dc, 0x0b5c, 0x091c },
6e8958ec PZ	81	}, {
	82	~0UL, { 0x0000, 0x0000, 0x0000 },
	83	},
aaa757a0 AY	84	};
aaa757a0 AY	85
36b8ae0d RK	86	/*
	87	* Resistance term 133Ohm Cfg
	88	* PREEMP config 0.00
	89	* TX/CK level 10
	90	*/
034705a4 YY	91	static const struct dw_hdmi_phy_config imx_phy_config[] = {
034705a4 YY	92	/pixelclk symbol term vlev /
a5f4185c	93	{ 216000000, 0x800d, 0x0005, 0x01ad},
034705a4	94	{ ~0UL, 0x0000, 0x0000, 0x0000}
aaa757a0 AY	95	};
aaa757a0 AY	96
b21f4b65	97	static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
3d1b35a3 AY	98	{
	99	struct device_node *np = hdmi->dev->of_node;
	100
	101	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	102	if (IS_ERR(hdmi->regmap)) {
	103	dev_err(hdmi->dev, "Unable to get gpr\n");
	104	return PTR_ERR(hdmi->regmap);
	105	}
	106
	107	return 0;
	108	}
	109
b21f4b65	110	static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
3d1b35a3 AY	111	{
	112	}
	113
f6e396e5	114	static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
3d1b35a3	115	{
032003c5 LY	116	struct imx_drm_encoder *imx_encoder = enc_to_imx_enc(encoder);
032003c5 LY	117	struct imx_hdmi *hdmi = imx_enc_to_imx_hdmi(imx_encoder);
53141e42	118	int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
3d1b35a3 AY	119
	120	regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
	121	IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
	122	mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
	123	}
	124
7ae847dd	125	static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
f6e396e5	126	.enable = dw_hdmi_imx_encoder_enable,
b21f4b65	127	.disable = dw_hdmi_imx_encoder_disable,
3d1b35a3 AY	128	};
3d1b35a3 AY	129
7ae847dd	130	static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
3d1b35a3 AY	131	.destroy = drm_encoder_cleanup,
	132	};
	133
081c80e8 PZ	134	static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
	135	struct drm_display_mode *mode)
	136	{
	137	if (mode->clock < 13500)
	138	return MODE_CLOCK_LOW;
a5f4185c LS	139	/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
a5f4185c LS	140	if (mode->clock > 216000)
081c80e8 PZ	141	return MODE_CLOCK_HIGH;
	142
	143	return MODE_OK;
	144	}
	145
	146	static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
	147	struct drm_display_mode *mode)
	148	{
	149	if (mode->clock < 13500)
	150	return MODE_CLOCK_LOW;
a5f4185c LS	151	/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
a5f4185c LS	152	if (mode->clock > 216000)
081c80e8 PZ	153	return MODE_CLOCK_HIGH;
	154
	155	return MODE_OK;
	156	}
	157
b21f4b65	158	static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
081c80e8 PZ	159	.mpll_cfg = imx_mpll_cfg,
081c80e8 PZ	160	.cur_ctr = imx_cur_ctr,
034705a4	161	.phy_config = imx_phy_config,
081c80e8 PZ	162	.dev_type = IMX6Q_HDMI,
081c80e8 PZ	163	.mode_valid = imx6q_hdmi_mode_valid,
3d1b35a3 AY	164	};
3d1b35a3 AY	165
b21f4b65	166	static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
aaa757a0 AY	167	.mpll_cfg = imx_mpll_cfg,
aaa757a0 AY	168	.cur_ctr = imx_cur_ctr,
034705a4	169	.phy_config = imx_phy_config,
3d1b35a3	170	.dev_type = IMX6DL_HDMI,
081c80e8	171	.mode_valid = imx6dl_hdmi_mode_valid,
3d1b35a3 AY	172	};
3d1b35a3 AY	173
b21f4b65	174	static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
3d1b35a3 AY	175	{ .compatible = "fsl,imx6q-hdmi",
	176	.data = &imx6q_hdmi_drv_data
	177	}, {
	178	.compatible = "fsl,imx6dl-hdmi",
	179	.data = &imx6dl_hdmi_drv_data
	180	},
	181	{},
	182	};
b21f4b65	183	MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
3d1b35a3	184
b21f4b65 AY	185	static int dw_hdmi_imx_bind(struct device dev, struct device master,
b21f4b65 AY	186	void *data)
3d1b35a3 AY	187	{
3d1b35a3 AY	188	struct platform_device *pdev = to_platform_device(dev);
b21f4b65	189	const struct dw_hdmi_plat_data *plat_data;
3d1b35a3 AY	190	const struct of_device_id *match;
	191	struct drm_device *drm = data;
	192	struct drm_encoder *encoder;
b21f4b65	193	struct imx_hdmi *hdmi;
3d1b35a3 AY	194	struct resource *iores;
	195	int irq;
	196	int ret;
	197
	198	if (!pdev->dev.of_node)
	199	return -ENODEV;
	200
	201	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
	202	if (!hdmi)
	203	return -ENOMEM;
	204
b21f4b65	205	match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
3d1b35a3 AY	206	plat_data = match->data;
3d1b35a3 AY	207	hdmi->dev = &pdev->dev;
032003c5 LY	208	encoder = &hdmi->imx_encoder.encoder;
	209	hdmi->imx_encoder.bus_format = MEDIA_BUS_FMT_RGB888_1X24;
	210	hdmi->imx_encoder.di_hsync_pin = 2;
	211	hdmi->imx_encoder.di_vsync_pin = 3;
3d1b35a3 AY	212
	213	irq = platform_get_irq(pdev, 0);
	214	if (irq < 0)
	215	return irq;
	216
	217	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	218	if (!iores)
	219	return -ENXIO;
	220
3d1b35a3 AY	221	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
	222	/*
	223	* If we failed to find the CRTC(s) which this encoder is
	224	* supposed to be connected to, it's because the CRTC has
	225	* not been registered yet. Defer probing, and hope that
	226	* the required CRTC is added later.
	227	*/
	228	if (encoder->possible_crtcs == 0)
	229	return -EPROBE_DEFER;
	230
b21f4b65	231	ret = dw_hdmi_imx_parse_dt(hdmi);
3d1b35a3 AY	232	if (ret < 0)
	233	return ret;
	234
b21f4b65 AY	235	drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
b21f4b65 AY	236	drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
13a3d91f	237	DRM_MODE_ENCODER_TMDS, NULL);
3d1b35a3	238
788c8ddb DA	239	ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
	240
	241	/*
	242	* If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
	243	* which would have called the encoder cleanup. Do it manually.
	244	*/
	245	if (ret)
	246	drm_encoder_cleanup(encoder);
	247
	248	return ret;
3d1b35a3 AY	249	}
3d1b35a3 AY	250
b21f4b65 AY	251	static void dw_hdmi_imx_unbind(struct device dev, struct device master,
b21f4b65 AY	252	void *data)
3d1b35a3	253	{
b21f4b65	254	return dw_hdmi_unbind(dev, master, data);
3d1b35a3 AY	255	}
3d1b35a3 AY	256
b21f4b65 AY	257	static const struct component_ops dw_hdmi_imx_ops = {
	258	.bind = dw_hdmi_imx_bind,
	259	.unbind = dw_hdmi_imx_unbind,
3d1b35a3 AY	260	};
3d1b35a3 AY	261
b21f4b65	262	static int dw_hdmi_imx_probe(struct platform_device *pdev)
3d1b35a3	263	{
b21f4b65	264	return component_add(&pdev->dev, &dw_hdmi_imx_ops);
3d1b35a3 AY	265	}
3d1b35a3 AY	266
b21f4b65	267	static int dw_hdmi_imx_remove(struct platform_device *pdev)
3d1b35a3	268	{
b21f4b65	269	component_del(&pdev->dev, &dw_hdmi_imx_ops);
3d1b35a3 AY	270
	271	return 0;
	272	}
	273
b21f4b65 AY	274	static struct platform_driver dw_hdmi_imx_platform_driver = {
	275	.probe = dw_hdmi_imx_probe,
	276	.remove = dw_hdmi_imx_remove,
3d1b35a3	277	.driver = {
b21f4b65 AY	278	.name = "dwhdmi-imx",
b21f4b65 AY	279	.of_match_table = dw_hdmi_imx_dt_ids,
3d1b35a3 AY	280	},
	281	};
	282
b21f4b65	283	module_platform_driver(dw_hdmi_imx_platform_driver);
3d1b35a3 AY	284
	285	MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
	286	MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
	287	MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
	288	MODULE_LICENSE("GPL");
b21f4b65	289	MODULE_ALIAS("platform:dwhdmi-imx");