Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | /* |
2 | * i.MX drm driver - LVDS display bridge | |
3 | * | |
4 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
ac4c1a9b SH |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
17b5001b | 18 | #include <linux/component.h> |
ac4c1a9b SH |
19 | #include <drm/drmP.h> |
20 | #include <drm/drm_fb_helper.h> | |
21 | #include <drm/drm_crtc_helper.h> | |
53141e42 | 22 | #include <drm/drm_of.h> |
751e2676 | 23 | #include <drm/drm_panel.h> |
ac4c1a9b SH |
24 | #include <linux/mfd/syscon.h> |
25 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
ac4c1a9b | 26 | #include <linux/of_device.h> |
751e2676 | 27 | #include <linux/of_graph.h> |
ac4c1a9b SH |
28 | #include <video/of_videomode.h> |
29 | #include <linux/regmap.h> | |
30 | #include <linux/videodev2.h> | |
31 | ||
32 | #include "imx-drm.h" | |
33 | ||
34 | #define DRIVER_NAME "imx-ldb" | |
35 | ||
36 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
37 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
38 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
39 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
40 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
41 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
42 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
43 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
44 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
45 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
46 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
47 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
48 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
49 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
50 | ||
51 | #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector) | |
52 | #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder) | |
53 | ||
54 | struct imx_ldb; | |
55 | ||
56 | struct imx_ldb_channel { | |
57 | struct imx_ldb *ldb; | |
58 | struct drm_connector connector; | |
ac4c1a9b | 59 | struct drm_encoder encoder; |
751e2676 | 60 | struct drm_panel *panel; |
1b3f7675 | 61 | struct device_node *child; |
ac4c1a9b SH |
62 | int chno; |
63 | void *edid; | |
64 | int edid_len; | |
65 | struct drm_display_mode mode; | |
66 | int mode_valid; | |
5e501ed7 | 67 | int bus_format; |
ac4c1a9b SH |
68 | }; |
69 | ||
70 | struct bus_mux { | |
71 | int reg; | |
72 | int shift; | |
73 | int mask; | |
74 | }; | |
75 | ||
76 | struct imx_ldb { | |
77 | struct regmap *regmap; | |
78 | struct device *dev; | |
79 | struct imx_ldb_channel channel[2]; | |
80 | struct clk *clk[2]; /* our own clock */ | |
81 | struct clk *clk_sel[4]; /* parent of display clock */ | |
3973aff0 | 82 | struct clk *clk_parent[4]; /* original parent of clk_sel */ |
ac4c1a9b SH |
83 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ |
84 | u32 ldb_ctrl; | |
85 | const struct bus_mux *lvds_mux; | |
86 | }; | |
87 | ||
88 | static enum drm_connector_status imx_ldb_connector_detect( | |
89 | struct drm_connector *connector, bool force) | |
90 | { | |
91 | return connector_status_connected; | |
92 | } | |
93 | ||
ac4c1a9b SH |
94 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
95 | { | |
96 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
97 | int num_modes = 0; | |
98 | ||
751e2676 PZ |
99 | if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && |
100 | imx_ldb_ch->panel->funcs->get_modes) { | |
5e501ed7 PZ |
101 | struct drm_display_info *di = &connector->display_info; |
102 | ||
751e2676 | 103 | num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); |
5e501ed7 PZ |
104 | if (!imx_ldb_ch->bus_format && di->num_bus_formats) |
105 | imx_ldb_ch->bus_format = di->bus_formats[0]; | |
751e2676 PZ |
106 | if (num_modes > 0) |
107 | return num_modes; | |
108 | } | |
109 | ||
ac4c1a9b SH |
110 | if (imx_ldb_ch->edid) { |
111 | drm_mode_connector_update_edid_property(connector, | |
112 | imx_ldb_ch->edid); | |
113 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
114 | } | |
115 | ||
116 | if (imx_ldb_ch->mode_valid) { | |
117 | struct drm_display_mode *mode; | |
118 | ||
119 | mode = drm_mode_create(connector->dev); | |
9f9b036f FE |
120 | if (!mode) |
121 | return -EINVAL; | |
ac4c1a9b SH |
122 | drm_mode_copy(mode, &imx_ldb_ch->mode); |
123 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
124 | drm_mode_probed_add(connector, mode); | |
125 | num_modes++; | |
126 | } | |
127 | ||
128 | return num_modes; | |
129 | } | |
130 | ||
ac4c1a9b SH |
131 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
132 | struct drm_connector *connector) | |
133 | { | |
134 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
135 | ||
136 | return &imx_ldb_ch->encoder; | |
137 | } | |
138 | ||
139 | static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode) | |
140 | { | |
141 | } | |
142 | ||
ac4c1a9b SH |
143 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, |
144 | unsigned long serial_clk, unsigned long di_clk) | |
145 | { | |
146 | int ret; | |
147 | ||
148 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
149 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
150 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
151 | ||
152 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
153 | clk_get_rate(ldb->clk_pll[chno])); | |
154 | ||
155 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
156 | clk_get_rate(ldb->clk[chno]), | |
157 | (long int)di_clk); | |
158 | clk_set_rate(ldb->clk[chno], di_clk); | |
159 | ||
160 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
161 | clk_get_rate(ldb->clk[chno])); | |
162 | ||
163 | /* set display clock mux to LDB input clock */ | |
164 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 165 | if (ret) |
e5e1b166 AO |
166 | dev_err(ldb->dev, |
167 | "unable to set di%d parent clock to ldb_di%d\n", mux, | |
168 | chno); | |
ac4c1a9b SH |
169 | } |
170 | ||
171 | static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) | |
172 | { | |
173 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
174 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
5e501ed7 | 175 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; |
2872c807 | 176 | u32 bus_format; |
ac4c1a9b | 177 | |
5e501ed7 PZ |
178 | switch (imx_ldb_ch->bus_format) { |
179 | default: | |
180 | dev_warn(ldb->dev, | |
181 | "could not determine data mapping, default to 18-bit \"spwg\"\n"); | |
182 | /* fallthrough */ | |
183 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
184 | bus_format = MEDIA_BUS_FMT_RGB666_1X18; | |
000d73fc | 185 | break; |
5e501ed7 PZ |
186 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: |
187 | bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
188 | if (imx_ldb_ch->chno == 0 || dual) | |
189 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; | |
190 | if (imx_ldb_ch->chno == 1 || dual) | |
191 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; | |
000d73fc | 192 | break; |
5e501ed7 | 193 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: |
2872c807 | 194 | bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
5e501ed7 PZ |
195 | if (imx_ldb_ch->chno == 0 || dual) |
196 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | | |
197 | LDB_BIT_MAP_CH0_JEIDA; | |
198 | if (imx_ldb_ch->chno == 1 || dual) | |
199 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | | |
200 | LDB_BIT_MAP_CH1_JEIDA; | |
201 | break; | |
000d73fc MN |
202 | } |
203 | ||
2872c807 | 204 | imx_drm_set_bus_format(encoder, bus_format); |
ac4c1a9b SH |
205 | } |
206 | ||
207 | static void imx_ldb_encoder_commit(struct drm_encoder *encoder) | |
208 | { | |
209 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
210 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
211 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
53141e42 | 212 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b | 213 | |
751e2676 PZ |
214 | drm_panel_prepare(imx_ldb_ch->panel); |
215 | ||
ac4c1a9b SH |
216 | if (dual) { |
217 | clk_prepare_enable(ldb->clk[0]); | |
218 | clk_prepare_enable(ldb->clk[1]); | |
219 | } | |
220 | ||
221 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
222 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
223 | if (mux == 0 || ldb->lvds_mux) | |
224 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
225 | else if (mux == 1) | |
226 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
227 | } | |
228 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
229 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
230 | if (mux == 1 || ldb->lvds_mux) | |
231 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
232 | else if (mux == 0) | |
233 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
234 | } | |
235 | ||
236 | if (ldb->lvds_mux) { | |
237 | const struct bus_mux *lvds_mux = NULL; | |
238 | ||
239 | if (imx_ldb_ch == &ldb->channel[0]) | |
240 | lvds_mux = &ldb->lvds_mux[0]; | |
241 | else if (imx_ldb_ch == &ldb->channel[1]) | |
242 | lvds_mux = &ldb->lvds_mux[1]; | |
243 | ||
244 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
245 | mux << lvds_mux->shift); | |
246 | } | |
247 | ||
248 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
751e2676 PZ |
249 | |
250 | drm_panel_enable(imx_ldb_ch->panel); | |
ac4c1a9b SH |
251 | } |
252 | ||
253 | static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |
eb10d635 SL |
254 | struct drm_display_mode *orig_mode, |
255 | struct drm_display_mode *mode) | |
ac4c1a9b SH |
256 | { |
257 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
258 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
259 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
51dac94e PZ |
260 | unsigned long serial_clk; |
261 | unsigned long di_clk = mode->clock * 1000; | |
53141e42 | 262 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b SH |
263 | |
264 | if (mode->clock > 170000) { | |
265 | dev_warn(ldb->dev, | |
266 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
267 | } | |
268 | if (mode->clock > 85000 && !dual) { | |
269 | dev_warn(ldb->dev, | |
270 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
271 | } | |
272 | ||
51dac94e PZ |
273 | if (dual) { |
274 | serial_clk = 3500UL * mode->clock; | |
275 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
276 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
277 | } else { | |
278 | serial_clk = 7000UL * mode->clock; | |
279 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | |
280 | di_clk); | |
281 | } | |
282 | ||
ac4c1a9b SH |
283 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
284 | if (imx_ldb_ch == &ldb->channel[0]) { | |
285 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
286 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
287 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
288 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
289 | } | |
290 | if (imx_ldb_ch == &ldb->channel[1]) { | |
291 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
292 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
293 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
294 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
295 | } | |
296 | } | |
297 | ||
298 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
299 | { | |
300 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
301 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
3973aff0 | 302 | int mux, ret; |
ac4c1a9b SH |
303 | |
304 | /* | |
305 | * imx_ldb_encoder_disable is called by | |
306 | * drm_helper_disable_unused_functions without | |
307 | * the encoder being enabled before. | |
308 | */ | |
309 | if (imx_ldb_ch == &ldb->channel[0] && | |
310 | (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) | |
311 | return; | |
312 | else if (imx_ldb_ch == &ldb->channel[1] && | |
313 | (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) | |
314 | return; | |
315 | ||
751e2676 PZ |
316 | drm_panel_disable(imx_ldb_ch->panel); |
317 | ||
ac4c1a9b SH |
318 | if (imx_ldb_ch == &ldb->channel[0]) |
319 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
320 | else if (imx_ldb_ch == &ldb->channel[1]) | |
321 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
322 | ||
323 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
324 | ||
325 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
326 | clk_disable_unprepare(ldb->clk[0]); | |
327 | clk_disable_unprepare(ldb->clk[1]); | |
328 | } | |
751e2676 | 329 | |
3973aff0 PZ |
330 | if (ldb->lvds_mux) { |
331 | const struct bus_mux *lvds_mux = NULL; | |
332 | ||
333 | if (imx_ldb_ch == &ldb->channel[0]) | |
334 | lvds_mux = &ldb->lvds_mux[0]; | |
335 | else if (imx_ldb_ch == &ldb->channel[1]) | |
336 | lvds_mux = &ldb->lvds_mux[1]; | |
337 | ||
338 | regmap_read(ldb->regmap, lvds_mux->reg, &mux); | |
339 | mux &= lvds_mux->mask; | |
340 | mux >>= lvds_mux->shift; | |
341 | } else { | |
342 | mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; | |
343 | } | |
344 | ||
345 | /* set display clock mux back to original input clock */ | |
346 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); | |
347 | if (ret) | |
348 | dev_err(ldb->dev, | |
349 | "unable to set di%d parent clock to original parent\n", | |
350 | mux); | |
351 | ||
751e2676 | 352 | drm_panel_unprepare(imx_ldb_ch->panel); |
ac4c1a9b SH |
353 | } |
354 | ||
7ae847dd | 355 | static const struct drm_connector_funcs imx_ldb_connector_funcs = { |
ac4c1a9b SH |
356 | .dpms = drm_helper_connector_dpms, |
357 | .fill_modes = drm_helper_probe_single_connector_modes, | |
358 | .detect = imx_ldb_connector_detect, | |
1b3f7675 | 359 | .destroy = imx_drm_connector_destroy, |
ac4c1a9b SH |
360 | }; |
361 | ||
7ae847dd | 362 | static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { |
ac4c1a9b SH |
363 | .get_modes = imx_ldb_connector_get_modes, |
364 | .best_encoder = imx_ldb_connector_best_encoder, | |
ac4c1a9b SH |
365 | }; |
366 | ||
7ae847dd | 367 | static const struct drm_encoder_funcs imx_ldb_encoder_funcs = { |
1b3f7675 | 368 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
369 | }; |
370 | ||
7ae847dd | 371 | static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { |
ac4c1a9b | 372 | .dpms = imx_ldb_encoder_dpms, |
ac4c1a9b SH |
373 | .prepare = imx_ldb_encoder_prepare, |
374 | .commit = imx_ldb_encoder_commit, | |
375 | .mode_set = imx_ldb_encoder_mode_set, | |
376 | .disable = imx_ldb_encoder_disable, | |
377 | }; | |
378 | ||
379 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
380 | { | |
381 | char clkname[16]; | |
382 | ||
98dd3b2a | 383 | snprintf(clkname, sizeof(clkname), "di%d", chno); |
ac4c1a9b SH |
384 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); |
385 | if (IS_ERR(ldb->clk[chno])) | |
386 | return PTR_ERR(ldb->clk[chno]); | |
387 | ||
98dd3b2a | 388 | snprintf(clkname, sizeof(clkname), "di%d_pll", chno); |
ac4c1a9b | 389 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); |
ac4c1a9b | 390 | |
1f933fa8 | 391 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
392 | } |
393 | ||
1b3f7675 RK |
394 | static int imx_ldb_register(struct drm_device *drm, |
395 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 396 | { |
ac4c1a9b | 397 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
1b3f7675 RK |
398 | int ret; |
399 | ||
400 | ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder, | |
401 | imx_ldb_ch->child); | |
402 | if (ret) | |
403 | return ret; | |
ac4c1a9b SH |
404 | |
405 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
406 | if (ret) | |
407 | return ret; | |
1b3f7675 | 408 | |
ac4c1a9b | 409 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 410 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
411 | if (ret) |
412 | return ret; | |
413 | } | |
414 | ||
ac4c1a9b SH |
415 | drm_encoder_helper_add(&imx_ldb_ch->encoder, |
416 | &imx_ldb_encoder_helper_funcs); | |
1b3f7675 | 417 | drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs, |
13a3d91f | 418 | DRM_MODE_ENCODER_LVDS, NULL); |
ac4c1a9b SH |
419 | |
420 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
421 | &imx_ldb_connector_helper_funcs); | |
1b3f7675 RK |
422 | drm_connector_init(drm, &imx_ldb_ch->connector, |
423 | &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); | |
ac4c1a9b | 424 | |
751e2676 PZ |
425 | if (imx_ldb_ch->panel) |
426 | drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector); | |
427 | ||
ac4c1a9b SH |
428 | drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, |
429 | &imx_ldb_ch->encoder); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | enum { | |
435 | LVDS_BIT_MAP_SPWG, | |
436 | LVDS_BIT_MAP_JEIDA | |
437 | }; | |
438 | ||
5e501ed7 PZ |
439 | struct imx_ldb_bit_mapping { |
440 | u32 bus_format; | |
441 | u32 datawidth; | |
442 | const char * const mapping; | |
ac4c1a9b SH |
443 | }; |
444 | ||
5e501ed7 PZ |
445 | static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { |
446 | { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, | |
447 | { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, | |
448 | { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, | |
449 | }; | |
450 | ||
451 | static u32 of_get_bus_format(struct device *dev, struct device_node *np) | |
ac4c1a9b SH |
452 | { |
453 | const char *bm; | |
5e501ed7 | 454 | u32 datawidth = 0; |
ac4c1a9b SH |
455 | int ret, i; |
456 | ||
457 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
458 | if (ret < 0) | |
459 | return ret; | |
460 | ||
5e501ed7 PZ |
461 | of_property_read_u32(np, "fsl,data-width", &datawidth); |
462 | ||
463 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { | |
464 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && | |
465 | datawidth == imx_ldb_bit_mappings[i].datawidth) | |
466 | return imx_ldb_bit_mappings[i].bus_format; | |
467 | } | |
468 | ||
469 | dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); | |
ac4c1a9b | 470 | |
5e501ed7 | 471 | return -ENOENT; |
ac4c1a9b SH |
472 | } |
473 | ||
474 | static struct bus_mux imx6q_lvds_mux[2] = { | |
475 | { | |
476 | .reg = IOMUXC_GPR3, | |
477 | .shift = 6, | |
478 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
479 | }, { | |
480 | .reg = IOMUXC_GPR3, | |
481 | .shift = 8, | |
482 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
483 | } | |
484 | }; | |
485 | ||
486 | /* | |
487 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
488 | * of_match_device will walk through this list and take the first entry | |
489 | * matching any of its compatible values. Therefore, the more generic | |
490 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
491 | */ | |
492 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
493 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
494 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
495 | { } | |
496 | }; | |
497 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
498 | ||
17b5001b | 499 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 500 | { |
1b3f7675 | 501 | struct drm_device *drm = data; |
17b5001b | 502 | struct device_node *np = dev->of_node; |
ac4c1a9b | 503 | const struct of_device_id *of_id = |
17b5001b | 504 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b SH |
505 | struct device_node *child; |
506 | const u8 *edidp; | |
507 | struct imx_ldb *imx_ldb; | |
ac4c1a9b SH |
508 | int dual; |
509 | int ret; | |
510 | int i; | |
511 | ||
17b5001b | 512 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
513 | if (!imx_ldb) |
514 | return -ENOMEM; | |
515 | ||
516 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
517 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 518 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
519 | return PTR_ERR(imx_ldb->regmap); |
520 | } | |
521 | ||
17b5001b | 522 | imx_ldb->dev = dev; |
ac4c1a9b SH |
523 | |
524 | if (of_id) | |
525 | imx_ldb->lvds_mux = of_id->data; | |
526 | ||
527 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
528 | if (dual) | |
529 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
530 | ||
531 | /* | |
4599934d | 532 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
533 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
534 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
535 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
536 | * Map them all to di0_sel...di3_sel. | |
537 | */ | |
538 | for (i = 0; i < 4; i++) { | |
539 | char clkname[16]; | |
540 | ||
541 | sprintf(clkname, "di%d_sel", i); | |
542 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
543 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
544 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
545 | imx_ldb->clk_sel[i] = NULL; | |
546 | break; | |
547 | } | |
3973aff0 PZ |
548 | |
549 | imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); | |
ac4c1a9b SH |
550 | } |
551 | if (i == 0) | |
552 | return ret; | |
553 | ||
554 | for_each_child_of_node(np, child) { | |
555 | struct imx_ldb_channel *channel; | |
751e2676 | 556 | struct device_node *port; |
ac4c1a9b SH |
557 | |
558 | ret = of_property_read_u32(child, "reg", &i); | |
559 | if (ret || i < 0 || i > 1) | |
560 | return -EINVAL; | |
561 | ||
562 | if (dual && i > 0) { | |
17b5001b | 563 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
564 | continue; |
565 | } | |
566 | ||
567 | if (!of_device_is_available(child)) | |
568 | continue; | |
569 | ||
570 | channel = &imx_ldb->channel[i]; | |
571 | channel->ldb = imx_ldb; | |
572 | channel->chno = i; | |
1b3f7675 | 573 | channel->child = child; |
ac4c1a9b | 574 | |
751e2676 PZ |
575 | /* |
576 | * The output port is port@4 with an external 4-port mux or | |
577 | * port@2 with the internal 2-port mux. | |
578 | */ | |
579 | port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2); | |
580 | if (port) { | |
581 | struct device_node *endpoint, *remote; | |
582 | ||
583 | endpoint = of_get_child_by_name(port, "endpoint"); | |
584 | if (endpoint) { | |
585 | remote = of_graph_get_remote_port_parent(endpoint); | |
586 | if (remote) | |
587 | channel->panel = of_drm_find_panel(remote); | |
588 | else | |
589 | return -EPROBE_DEFER; | |
590 | if (!channel->panel) { | |
591 | dev_err(dev, "panel not found: %s\n", | |
592 | remote->full_name); | |
593 | return -EPROBE_DEFER; | |
594 | } | |
595 | } | |
596 | } | |
597 | ||
ac4c1a9b SH |
598 | edidp = of_get_property(child, "edid", &channel->edid_len); |
599 | if (edidp) { | |
600 | channel->edid = kmemdup(edidp, channel->edid_len, | |
601 | GFP_KERNEL); | |
751e2676 | 602 | } else if (!channel->panel) { |
ac4c1a9b SH |
603 | ret = of_get_drm_display_mode(child, &channel->mode, 0); |
604 | if (!ret) | |
605 | channel->mode_valid = 1; | |
606 | } | |
607 | ||
5e501ed7 PZ |
608 | channel->bus_format = of_get_bus_format(dev, child); |
609 | if (channel->bus_format == -EINVAL) { | |
610 | /* | |
611 | * If no bus format was specified in the device tree, | |
612 | * we can still get it from the connected panel later. | |
613 | */ | |
614 | if (channel->panel && channel->panel->funcs && | |
615 | channel->panel->funcs->get_modes) | |
616 | channel->bus_format = 0; | |
617 | } | |
618 | if (channel->bus_format < 0) { | |
619 | dev_err(dev, "could not determine data mapping: %d\n", | |
620 | channel->bus_format); | |
621 | return channel->bus_format; | |
ac4c1a9b SH |
622 | } |
623 | ||
1b3f7675 | 624 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
625 | if (ret) |
626 | return ret; | |
ac4c1a9b SH |
627 | } |
628 | ||
17b5001b | 629 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
630 | |
631 | return 0; | |
632 | } | |
633 | ||
17b5001b RK |
634 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
635 | void *data) | |
ac4c1a9b | 636 | { |
17b5001b | 637 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
638 | int i; |
639 | ||
640 | for (i = 0; i < 2; i++) { | |
641 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 642 | |
d9fdb9fb RK |
643 | if (!channel->connector.funcs) |
644 | continue; | |
645 | ||
1b3f7675 RK |
646 | channel->connector.funcs->destroy(&channel->connector); |
647 | channel->encoder.funcs->destroy(&channel->encoder); | |
f4876ffe PS |
648 | |
649 | kfree(channel->edid); | |
ac4c1a9b | 650 | } |
17b5001b | 651 | } |
ac4c1a9b | 652 | |
17b5001b RK |
653 | static const struct component_ops imx_ldb_ops = { |
654 | .bind = imx_ldb_bind, | |
655 | .unbind = imx_ldb_unbind, | |
656 | }; | |
657 | ||
658 | static int imx_ldb_probe(struct platform_device *pdev) | |
659 | { | |
660 | return component_add(&pdev->dev, &imx_ldb_ops); | |
661 | } | |
662 | ||
663 | static int imx_ldb_remove(struct platform_device *pdev) | |
664 | { | |
665 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
666 | return 0; |
667 | } | |
668 | ||
669 | static struct platform_driver imx_ldb_driver = { | |
670 | .probe = imx_ldb_probe, | |
671 | .remove = imx_ldb_remove, | |
672 | .driver = { | |
673 | .of_match_table = imx_ldb_dt_ids, | |
674 | .name = DRIVER_NAME, | |
ac4c1a9b SH |
675 | }, |
676 | }; | |
677 | ||
678 | module_platform_driver(imx_ldb_driver); | |
679 | ||
680 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
681 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
682 | MODULE_LICENSE("GPL"); | |
bc627387 | 683 | MODULE_ALIAS("platform:" DRIVER_NAME); |