[deliverable/linux.git] / drivers / gpu / drm / imx / imx-ldb.c

/*
 * i.MX drm driver - LVDS display bridge
 *
 * Copyright (C) 2012 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <drm/drmP.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <video/of_videomode.h>
#include <linux/regmap.h>
#include <linux/videodev2.h>

#include "imx-drm.h"

#define DRIVER_NAME "imx-ldb"

#define LDB_CH0_MODE_EN_TO_DI0		(1 << 0)
#define LDB_CH0_MODE_EN_TO_DI1		(3 << 0)
#define LDB_CH0_MODE_EN_MASK		(3 << 0)
#define LDB_CH1_MODE_EN_TO_DI0		(1 << 2)
#define LDB_CH1_MODE_EN_TO_DI1		(3 << 2)
#define LDB_CH1_MODE_EN_MASK		(3 << 2)
#define LDB_SPLIT_MODE_EN		(1 << 4)
#define LDB_DATA_WIDTH_CH0_24		(1 << 5)
#define LDB_BIT_MAP_CH0_JEIDA		(1 << 6)
#define LDB_DATA_WIDTH_CH1_24		(1 << 7)
#define LDB_BIT_MAP_CH1_JEIDA		(1 << 8)
#define LDB_DI0_VS_POL_ACT_LOW		(1 << 9)
#define LDB_DI1_VS_POL_ACT_LOW		(1 << 10)
#define LDB_BGREF_RMODE_INT		(1 << 15)

#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)

struct imx_ldb;

struct imx_ldb_channel {
	struct imx_ldb *ldb;
	struct drm_connector connector;
	struct drm_encoder encoder;
	struct device_node *child;
	int chno;
	void *edid;
	int edid_len;
	struct drm_display_mode mode;
	int mode_valid;
};

struct bus_mux {
	int reg;
	int shift;
	int mask;
};

struct imx_ldb {
	struct regmap *regmap;
	struct device *dev;
	struct imx_ldb_channel channel[2];
	struct clk *clk[2]; /* our own clock */
	struct clk *clk_sel[4]; /* parent of display clock */
	struct clk *clk_pll[2]; /* upstream clock we can adjust */
	u32 ldb_ctrl;
	const struct bus_mux *lvds_mux;
};

static enum drm_connector_status imx_ldb_connector_detect(
		struct drm_connector *connector, bool force)
{
	return connector_status_connected;
}

static int imx_ldb_connector_get_modes(struct drm_connector *connector)
{
	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
	int num_modes = 0;

	if (imx_ldb_ch->edid) {
		drm_mode_connector_update_edid_property(connector,
							imx_ldb_ch->edid);
		num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
	}

	if (imx_ldb_ch->mode_valid) {
		struct drm_display_mode *mode;

		mode = drm_mode_create(connector->dev);
		if (!mode)
			return -EINVAL;
		drm_mode_copy(mode, &imx_ldb_ch->mode);
		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
		drm_mode_probed_add(connector, mode);
		num_modes++;
	}

	return num_modes;
}

static struct drm_encoder *imx_ldb_connector_best_encoder(
		struct drm_connector *connector)
{
	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);

	return &imx_ldb_ch->encoder;
}

static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
{
}

static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
			   const struct drm_display_mode *mode,
			   struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
		unsigned long serial_clk, unsigned long di_clk)
{
	int ret;

	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
			clk_get_rate(ldb->clk_pll[chno]), serial_clk);
	clk_set_rate(ldb->clk_pll[chno], serial_clk);

	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
			clk_get_rate(ldb->clk_pll[chno]));

	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
			clk_get_rate(ldb->clk[chno]),
			(long int)di_clk);
	clk_set_rate(ldb->clk[chno], di_clk);

	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
			clk_get_rate(ldb->clk[chno]));

	/* set display clock mux to LDB input clock */
	ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
	if (ret)
		dev_err(ldb->dev,
			"unable to set di%d parent clock to ldb_di%d\n", mux,
			chno);
}

static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
{
	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	struct drm_display_mode *mode = &encoder->crtc->hwmode;
	u32 pixel_fmt;
	unsigned long serial_clk;
	unsigned long di_clk = mode->clock * 1000;
	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);

	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
		/* dual channel LVDS mode */
		serial_clk = 3500UL * mode->clock;
		imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
		imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
	} else {
		serial_clk = 7000UL * mode->clock;
		imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
				di_clk);
	}

	switch (imx_ldb_ch->chno) {
	case 0:
		pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
			V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
		break;
	case 1:
		pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
			V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
		break;
	default:
		dev_err(ldb->dev, "unable to config di%d panel format\n",
			imx_ldb_ch->chno);
		pixel_fmt = V4L2_PIX_FMT_RGB24;
	}

	imx_drm_panel_format(encoder, pixel_fmt);
}

static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
{
	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);

	if (dual) {
		clk_prepare_enable(ldb->clk[0]);
		clk_prepare_enable(ldb->clk[1]);
	}

	if (imx_ldb_ch == &ldb->channel[0] || dual) {
		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
		if (mux == 0 || ldb->lvds_mux)
			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
		else if (mux == 1)
			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
	}
	if (imx_ldb_ch == &ldb->channel[1] || dual) {
		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
		if (mux == 1 || ldb->lvds_mux)
			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
		else if (mux == 0)
			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
	}

	if (ldb->lvds_mux) {
		const struct bus_mux *lvds_mux = NULL;

		if (imx_ldb_ch == &ldb->channel[0])
			lvds_mux = &ldb->lvds_mux[0];
		else if (imx_ldb_ch == &ldb->channel[1])
			lvds_mux = &ldb->lvds_mux[1];

		regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
				   mux << lvds_mux->shift);
	}

	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
}

static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
			 struct drm_display_mode *orig_mode,
			 struct drm_display_mode *mode)
{
	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;

	if (mode->clock > 170000) {
		dev_warn(ldb->dev,
			 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
	}
	if (mode->clock > 85000 && !dual) {
		dev_warn(ldb->dev,
			 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
	}

	/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
	if (imx_ldb_ch == &ldb->channel[0]) {
		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
			ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
		else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
			ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
	}
	if (imx_ldb_ch == &ldb->channel[1]) {
		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
			ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
		else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
			ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
	}
}

static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
{
	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	struct imx_ldb *ldb = imx_ldb_ch->ldb;

	/*
	 * imx_ldb_encoder_disable is called by
	 * drm_helper_disable_unused_functions without
	 * the encoder being enabled before.
	 */
	if (imx_ldb_ch == &ldb->channel[0] &&
	    (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
		return;
	else if (imx_ldb_ch == &ldb->channel[1] &&
		 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
		return;

	if (imx_ldb_ch == &ldb->channel[0])
		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
	else if (imx_ldb_ch == &ldb->channel[1])
		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;

	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);

	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
		clk_disable_unprepare(ldb->clk[0]);
		clk_disable_unprepare(ldb->clk[1]);
	}
}

static struct drm_connector_funcs imx_ldb_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.detect = imx_ldb_connector_detect,
	.destroy = imx_drm_connector_destroy,
};

static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
	.get_modes = imx_ldb_connector_get_modes,
	.best_encoder = imx_ldb_connector_best_encoder,
};

static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
	.destroy = imx_drm_encoder_destroy,
};

static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
	.dpms = imx_ldb_encoder_dpms,
	.mode_fixup = imx_ldb_encoder_mode_fixup,
	.prepare = imx_ldb_encoder_prepare,
	.commit = imx_ldb_encoder_commit,
	.mode_set = imx_ldb_encoder_mode_set,
	.disable = imx_ldb_encoder_disable,
};

static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
{
	char clkname[16];

	snprintf(clkname, sizeof(clkname), "di%d", chno);
	ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
	if (IS_ERR(ldb->clk[chno]))
		return PTR_ERR(ldb->clk[chno]);

	snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
	ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);

	return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
}

static int imx_ldb_register(struct drm_device *drm,
	struct imx_ldb_channel *imx_ldb_ch)
{
	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	int ret;

	ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
				       imx_ldb_ch->child);
	if (ret)
		return ret;

	ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
	if (ret)
		return ret;

	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
		ret = imx_ldb_get_clk(ldb, 1);
		if (ret)
			return ret;
	}

	drm_encoder_helper_add(&imx_ldb_ch->encoder,
			&imx_ldb_encoder_helper_funcs);
	drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
			 DRM_MODE_ENCODER_LVDS);

	drm_connector_helper_add(&imx_ldb_ch->connector,
			&imx_ldb_connector_helper_funcs);
	drm_connector_init(drm, &imx_ldb_ch->connector,
			   &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);

	drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
			&imx_ldb_ch->encoder);

	return 0;
}

enum {
	LVDS_BIT_MAP_SPWG,
	LVDS_BIT_MAP_JEIDA
};

static const char * const imx_ldb_bit_mappings[] = {
	[LVDS_BIT_MAP_SPWG]  = "spwg",
	[LVDS_BIT_MAP_JEIDA] = "jeida",
};

static const int of_get_data_mapping(struct device_node *np)
{
	const char *bm;
	int ret, i;

	ret = of_property_read_string(np, "fsl,data-mapping", &bm);
	if (ret < 0)
		return ret;

	for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
		if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
			return i;

	return -EINVAL;
}

static struct bus_mux imx6q_lvds_mux[2] = {
	{
		.reg = IOMUXC_GPR3,
		.shift = 6,
		.mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
	}, {
		.reg = IOMUXC_GPR3,
		.shift = 8,
		.mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
	}
};

/*
 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
 * of_match_device will walk through this list and take the first entry
 * matching any of its compatible values. Therefore, the more generic
 * entries (in this case fsl,imx53-ldb) need to be ordered last.
 */
static const struct of_device_id imx_ldb_dt_ids[] = {
	{ .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
	{ .compatible = "fsl,imx53-ldb", .data = NULL, },
	{ }
};
MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);

static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
{
	struct drm_device *drm = data;
	struct device_node *np = dev->of_node;
	const struct of_device_id *of_id =
			of_match_device(imx_ldb_dt_ids, dev);
	struct device_node *child;
	const u8 *edidp;
	struct imx_ldb *imx_ldb;
	int datawidth;
	int mapping;
	int dual;
	int ret;
	int i;

	imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
	if (!imx_ldb)
		return -ENOMEM;

	imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	if (IS_ERR(imx_ldb->regmap)) {
		dev_err(dev, "failed to get parent regmap\n");
		return PTR_ERR(imx_ldb->regmap);
	}

	imx_ldb->dev = dev;

	if (of_id)
		imx_ldb->lvds_mux = of_id->data;

	dual = of_property_read_bool(np, "fsl,dual-channel");
	if (dual)
		imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;

	/*
	 * There are three different possible clock mux configurations:
	 * i.MX53:  ipu1_di0_sel, ipu1_di1_sel
	 * i.MX6q:  ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
	 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
	 * Map them all to di0_sel...di3_sel.
	 */
	for (i = 0; i < 4; i++) {
		char clkname[16];

		sprintf(clkname, "di%d_sel", i);
		imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
		if (IS_ERR(imx_ldb->clk_sel[i])) {
			ret = PTR_ERR(imx_ldb->clk_sel[i]);
			imx_ldb->clk_sel[i] = NULL;
			break;
		}
	}
	if (i == 0)
		return ret;

	for_each_child_of_node(np, child) {
		struct imx_ldb_channel *channel;

		ret = of_property_read_u32(child, "reg", &i);
		if (ret || i < 0 || i > 1)
			return -EINVAL;

		if (dual && i > 0) {
			dev_warn(dev, "dual-channel mode, ignoring second output\n");
			continue;
		}

		if (!of_device_is_available(child))
			continue;

		channel = &imx_ldb->channel[i];
		channel->ldb = imx_ldb;
		channel->chno = i;
		channel->child = child;

		edidp = of_get_property(child, "edid", &channel->edid_len);
		if (edidp) {
			channel->edid = kmemdup(edidp, channel->edid_len,
						GFP_KERNEL);
		} else {
			ret = of_get_drm_display_mode(child, &channel->mode, 0);
			if (!ret)
				channel->mode_valid = 1;
		}

		ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
		if (ret)
			datawidth = 0;
		else if (datawidth != 18 && datawidth != 24)
			return -EINVAL;

		mapping = of_get_data_mapping(child);
		switch (mapping) {
		case LVDS_BIT_MAP_SPWG:
			if (datawidth == 24) {
				if (i == 0 || dual)
					imx_ldb->ldb_ctrl |=
						LDB_DATA_WIDTH_CH0_24;
				if (i == 1 || dual)
					imx_ldb->ldb_ctrl |=
						LDB_DATA_WIDTH_CH1_24;
			}
			break;
		case LVDS_BIT_MAP_JEIDA:
			if (datawidth == 18) {
				dev_err(dev, "JEIDA standard only supported in 24 bit\n");
				return -EINVAL;
			}
			if (i == 0 || dual)
				imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
					LDB_BIT_MAP_CH0_JEIDA;
			if (i == 1 || dual)
				imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
					LDB_BIT_MAP_CH1_JEIDA;
			break;
		default:
			dev_err(dev, "data mapping not specified or invalid\n");
			return -EINVAL;
		}

		ret = imx_ldb_register(drm, channel);
		if (ret)
			return ret;
	}

	dev_set_drvdata(dev, imx_ldb);

	return 0;
}

static void imx_ldb_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
	int i;

	for (i = 0; i < 2; i++) {
		struct imx_ldb_channel *channel = &imx_ldb->channel[i];

		if (!channel->connector.funcs)
			continue;

		channel->connector.funcs->destroy(&channel->connector);
		channel->encoder.funcs->destroy(&channel->encoder);

		kfree(channel->edid);
	}
}

static const struct component_ops imx_ldb_ops = {
	.bind	= imx_ldb_bind,
	.unbind	= imx_ldb_unbind,
};

static int imx_ldb_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &imx_ldb_ops);
}

static int imx_ldb_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &imx_ldb_ops);
	return 0;
}

static struct platform_driver imx_ldb_driver = {
	.probe		= imx_ldb_probe,
	.remove		= imx_ldb_remove,
	.driver		= {
		.of_match_table = imx_ldb_dt_ids,
		.name	= DRIVER_NAME,
	},
};

module_platform_driver(imx_ldb_driver);

MODULE_DESCRIPTION("i.MX LVDS driver");
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
ac4c1a9b SH	1	/*
	2	* i.MX drm driver - LVDS display bridge
	3	*
	4	* Copyright (C) 2012 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
ac4c1a9b SH	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/clk.h>
17b5001b	18	#include <linux/component.h>
ac4c1a9b SH	19	#include <drm/drmP.h>
	20	#include <drm/drm_fb_helper.h>
	21	#include <drm/drm_crtc_helper.h>
	22	#include <linux/mfd/syscon.h>
	23	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_device.h>
	26	#include <video/of_videomode.h>
	27	#include <linux/regmap.h>
	28	#include <linux/videodev2.h>
	29
	30	#include "imx-drm.h"
	31
	32	#define DRIVER_NAME "imx-ldb"
	33
	34	#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
	35	#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
	36	#define LDB_CH0_MODE_EN_MASK (3 << 0)
	37	#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
	38	#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
	39	#define LDB_CH1_MODE_EN_MASK (3 << 2)
	40	#define LDB_SPLIT_MODE_EN (1 << 4)
	41	#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
	42	#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
	43	#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
	44	#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
	45	#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
	46	#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
	47	#define LDB_BGREF_RMODE_INT (1 << 15)
	48
	49	#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
	50	#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
	51
	52	struct imx_ldb;
	53
	54	struct imx_ldb_channel {
	55	struct imx_ldb *ldb;
	56	struct drm_connector connector;
ac4c1a9b	57	struct drm_encoder encoder;
1b3f7675	58	struct device_node *child;
ac4c1a9b SH	59	int chno;
	60	void *edid;
	61	int edid_len;
	62	struct drm_display_mode mode;
	63	int mode_valid;
	64	};
	65
	66	struct bus_mux {
	67	int reg;
	68	int shift;
	69	int mask;
	70	};
	71
	72	struct imx_ldb {
	73	struct regmap *regmap;
	74	struct device *dev;
	75	struct imx_ldb_channel channel[2];
	76	struct clk clk[2]; / our own clock */
	77	struct clk clk_sel[4]; / parent of display clock */
	78	struct clk clk_pll[2]; / upstream clock we can adjust */
	79	u32 ldb_ctrl;
	80	const struct bus_mux *lvds_mux;
	81	};
	82
	83	static enum drm_connector_status imx_ldb_connector_detect(
	84	struct drm_connector *connector, bool force)
	85	{
	86	return connector_status_connected;
	87	}
	88
ac4c1a9b SH	89	static int imx_ldb_connector_get_modes(struct drm_connector *connector)
	90	{
	91	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
	92	int num_modes = 0;
	93
	94	if (imx_ldb_ch->edid) {
	95	drm_mode_connector_update_edid_property(connector,
	96	imx_ldb_ch->edid);
	97	num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
	98	}
	99
	100	if (imx_ldb_ch->mode_valid) {
	101	struct drm_display_mode *mode;
	102
	103	mode = drm_mode_create(connector->dev);
9f9b036f FE	104	if (!mode)
9f9b036f FE	105	return -EINVAL;
ac4c1a9b SH	106	drm_mode_copy(mode, &imx_ldb_ch->mode);
	107	mode->type \|= DRM_MODE_TYPE_DRIVER \| DRM_MODE_TYPE_PREFERRED;
	108	drm_mode_probed_add(connector, mode);
	109	num_modes++;
	110	}
	111
	112	return num_modes;
	113	}
	114
ac4c1a9b SH	115	static struct drm_encoder *imx_ldb_connector_best_encoder(
	116	struct drm_connector *connector)
	117	{
	118	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
	119
	120	return &imx_ldb_ch->encoder;
	121	}
	122
	123	static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
	124	{
	125	}
	126
	127	static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
	128	const struct drm_display_mode *mode,
	129	struct drm_display_mode *adjusted_mode)
	130	{
	131	return true;
	132	}
	133
	134	static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
	135	unsigned long serial_clk, unsigned long di_clk)
	136	{
	137	int ret;
	138
	139	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
	140	clk_get_rate(ldb->clk_pll[chno]), serial_clk);
	141	clk_set_rate(ldb->clk_pll[chno], serial_clk);
	142
	143	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
	144	clk_get_rate(ldb->clk_pll[chno]));
	145
	146	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
	147	clk_get_rate(ldb->clk[chno]),
	148	(long int)di_clk);
	149	clk_set_rate(ldb->clk[chno], di_clk);
	150
	151	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
	152	clk_get_rate(ldb->clk[chno]));
	153
	154	/* set display clock mux to LDB input clock */
	155	ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
49f4a9c8	156	if (ret)
e5e1b166 AO	157	dev_err(ldb->dev,
	158	"unable to set di%d parent clock to ldb_di%d\n", mux,
	159	chno);
ac4c1a9b SH	160	}
	161
	162	static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
	163	{
	164	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	165	struct imx_ldb *ldb = imx_ldb_ch->ldb;
eb10d635	166	struct drm_display_mode *mode = &encoder->crtc->hwmode;
000d73fc	167	u32 pixel_fmt;
ac4c1a9b SH	168	unsigned long serial_clk;
ac4c1a9b SH	169	unsigned long di_clk = mode->clock * 1000;
655b43cc	170	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
ac4c1a9b SH	171
	172	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
	173	/* dual channel LVDS mode */
	174	serial_clk = 3500UL * mode->clock;
	175	imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
	176	imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
	177	} else {
	178	serial_clk = 7000UL * mode->clock;
e5e1b166 AO	179	imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
e5e1b166 AO	180	di_clk);
ac4c1a9b SH	181	}
ac4c1a9b SH	182
000d73fc MN	183	switch (imx_ldb_ch->chno) {
	184	case 0:
	185	pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
	186	V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
	187	break;
	188	case 1:
	189	pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
	190	V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
	191	break;
	192	default:
	193	dev_err(ldb->dev, "unable to config di%d panel format\n",
	194	imx_ldb_ch->chno);
	195	pixel_fmt = V4L2_PIX_FMT_RGB24;
	196	}
	197
f2d66aad	198	imx_drm_panel_format(encoder, pixel_fmt);
ac4c1a9b SH	199	}
	200
	201	static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
	202	{
	203	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	204	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	205	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
655b43cc	206	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
ac4c1a9b SH	207
	208	if (dual) {
	209	clk_prepare_enable(ldb->clk[0]);
	210	clk_prepare_enable(ldb->clk[1]);
	211	}
	212
	213	if (imx_ldb_ch == &ldb->channel[0] \|\| dual) {
	214	ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
	215	if (mux == 0 \|\| ldb->lvds_mux)
	216	ldb->ldb_ctrl \|= LDB_CH0_MODE_EN_TO_DI0;
	217	else if (mux == 1)
	218	ldb->ldb_ctrl \|= LDB_CH0_MODE_EN_TO_DI1;
	219	}
	220	if (imx_ldb_ch == &ldb->channel[1] \|\| dual) {
	221	ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
	222	if (mux == 1 \|\| ldb->lvds_mux)
	223	ldb->ldb_ctrl \|= LDB_CH1_MODE_EN_TO_DI1;
	224	else if (mux == 0)
	225	ldb->ldb_ctrl \|= LDB_CH1_MODE_EN_TO_DI0;
	226	}
	227
	228	if (ldb->lvds_mux) {
	229	const struct bus_mux *lvds_mux = NULL;
	230
	231	if (imx_ldb_ch == &ldb->channel[0])
	232	lvds_mux = &ldb->lvds_mux[0];
	233	else if (imx_ldb_ch == &ldb->channel[1])
	234	lvds_mux = &ldb->lvds_mux[1];
	235
	236	regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
	237	mux << lvds_mux->shift);
	238	}
	239
	240	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
	241	}
	242
	243	static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
eb10d635 SL	244	struct drm_display_mode *orig_mode,
eb10d635 SL	245	struct drm_display_mode *mode)
ac4c1a9b SH	246	{
	247	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	248	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	249	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
	250
	251	if (mode->clock > 170000) {
	252	dev_warn(ldb->dev,
	253	"%s: mode exceeds 170 MHz pixel clock\n", __func__);
	254	}
	255	if (mode->clock > 85000 && !dual) {
	256	dev_warn(ldb->dev,
	257	"%s: mode exceeds 85 MHz pixel clock\n", __func__);
	258	}
	259
	260	/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
	261	if (imx_ldb_ch == &ldb->channel[0]) {
	262	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
	263	ldb->ldb_ctrl \|= LDB_DI0_VS_POL_ACT_LOW;
	264	else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
	265	ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
	266	}
	267	if (imx_ldb_ch == &ldb->channel[1]) {
	268	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
	269	ldb->ldb_ctrl \|= LDB_DI1_VS_POL_ACT_LOW;
	270	else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
	271	ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
	272	}
	273	}
	274
	275	static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
	276	{
	277	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
	278	struct imx_ldb *ldb = imx_ldb_ch->ldb;
	279
	280	/*
	281	* imx_ldb_encoder_disable is called by
	282	* drm_helper_disable_unused_functions without
	283	* the encoder being enabled before.
	284	*/
	285	if (imx_ldb_ch == &ldb->channel[0] &&
	286	(ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
	287	return;
	288	else if (imx_ldb_ch == &ldb->channel[1] &&
	289	(ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
	290	return;
	291
	292	if (imx_ldb_ch == &ldb->channel[0])
	293	ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
	294	else if (imx_ldb_ch == &ldb->channel[1])
	295	ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
	296
	297	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
	298
	299	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
	300	clk_disable_unprepare(ldb->clk[0]);
	301	clk_disable_unprepare(ldb->clk[1]);
	302	}
	303	}
	304
ac4c1a9b SH	305	static struct drm_connector_funcs imx_ldb_connector_funcs = {
	306	.dpms = drm_helper_connector_dpms,
	307	.fill_modes = drm_helper_probe_single_connector_modes,
	308	.detect = imx_ldb_connector_detect,
1b3f7675	309	.destroy = imx_drm_connector_destroy,
ac4c1a9b SH	310	};
	311
	312	static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
	313	.get_modes = imx_ldb_connector_get_modes,
	314	.best_encoder = imx_ldb_connector_best_encoder,
ac4c1a9b SH	315	};
	316
	317	static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
1b3f7675	318	.destroy = imx_drm_encoder_destroy,
ac4c1a9b SH	319	};
	320
	321	static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
	322	.dpms = imx_ldb_encoder_dpms,
	323	.mode_fixup = imx_ldb_encoder_mode_fixup,
	324	.prepare = imx_ldb_encoder_prepare,
	325	.commit = imx_ldb_encoder_commit,
	326	.mode_set = imx_ldb_encoder_mode_set,
	327	.disable = imx_ldb_encoder_disable,
	328	};
	329
	330	static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
	331	{
	332	char clkname[16];
	333
98dd3b2a	334	snprintf(clkname, sizeof(clkname), "di%d", chno);
ac4c1a9b SH	335	ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
	336	if (IS_ERR(ldb->clk[chno]))
	337	return PTR_ERR(ldb->clk[chno]);
	338
98dd3b2a	339	snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
ac4c1a9b	340	ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
ac4c1a9b	341
1f933fa8	342	return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
ac4c1a9b SH	343	}
ac4c1a9b SH	344
1b3f7675 RK	345	static int imx_ldb_register(struct drm_device *drm,
1b3f7675 RK	346	struct imx_ldb_channel *imx_ldb_ch)
ac4c1a9b	347	{
ac4c1a9b	348	struct imx_ldb *ldb = imx_ldb_ch->ldb;
1b3f7675 RK	349	int ret;
	350
	351	ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
	352	imx_ldb_ch->child);
	353	if (ret)
	354	return ret;
ac4c1a9b SH	355
	356	ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
	357	if (ret)
	358	return ret;
1b3f7675	359
ac4c1a9b	360	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
1b3f7675	361	ret = imx_ldb_get_clk(ldb, 1);
ac4c1a9b SH	362	if (ret)
	363	return ret;
	364	}
	365
ac4c1a9b SH	366	drm_encoder_helper_add(&imx_ldb_ch->encoder,
ac4c1a9b SH	367	&imx_ldb_encoder_helper_funcs);
1b3f7675 RK	368	drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
1b3f7675 RK	369	DRM_MODE_ENCODER_LVDS);
ac4c1a9b SH	370
	371	drm_connector_helper_add(&imx_ldb_ch->connector,
	372	&imx_ldb_connector_helper_funcs);
1b3f7675 RK	373	drm_connector_init(drm, &imx_ldb_ch->connector,
1b3f7675 RK	374	&imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
ac4c1a9b SH	375
	376	drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
	377	&imx_ldb_ch->encoder);
	378
	379	return 0;
	380	}
	381
	382	enum {
	383	LVDS_BIT_MAP_SPWG,
	384	LVDS_BIT_MAP_JEIDA
	385	};
	386
5354cb64	387	static const char * const imx_ldb_bit_mappings[] = {
ac4c1a9b SH	388	[LVDS_BIT_MAP_SPWG] = "spwg",
	389	[LVDS_BIT_MAP_JEIDA] = "jeida",
	390	};
	391
d78b1406	392	static const int of_get_data_mapping(struct device_node *np)
ac4c1a9b SH	393	{
	394	const char *bm;
	395	int ret, i;
	396
	397	ret = of_property_read_string(np, "fsl,data-mapping", &bm);
	398	if (ret < 0)
	399	return ret;
	400
	401	for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
	402	if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
	403	return i;
	404
	405	return -EINVAL;
	406	}
	407
	408	static struct bus_mux imx6q_lvds_mux[2] = {
	409	{
	410	.reg = IOMUXC_GPR3,
	411	.shift = 6,
	412	.mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
	413	}, {
	414	.reg = IOMUXC_GPR3,
	415	.shift = 8,
	416	.mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
	417	}
	418	};
	419
	420	/*
	421	* For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
	422	* of_match_device will walk through this list and take the first entry
	423	* matching any of its compatible values. Therefore, the more generic
	424	* entries (in this case fsl,imx53-ldb) need to be ordered last.
	425	*/
	426	static const struct of_device_id imx_ldb_dt_ids[] = {
	427	{ .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
	428	{ .compatible = "fsl,imx53-ldb", .data = NULL, },
	429	{ }
	430	};
	431	MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
	432
17b5001b	433	static int imx_ldb_bind(struct device dev, struct device master, void *data)
ac4c1a9b	434	{
1b3f7675	435	struct drm_device *drm = data;
17b5001b	436	struct device_node *np = dev->of_node;
ac4c1a9b	437	const struct of_device_id *of_id =
17b5001b	438	of_match_device(imx_ldb_dt_ids, dev);
ac4c1a9b SH	439	struct device_node *child;
	440	const u8 *edidp;
	441	struct imx_ldb *imx_ldb;
	442	int datawidth;
	443	int mapping;
	444	int dual;
	445	int ret;
	446	int i;
	447
17b5001b	448	imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
ac4c1a9b SH	449	if (!imx_ldb)
	450	return -ENOMEM;
	451
	452	imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
	453	if (IS_ERR(imx_ldb->regmap)) {
17b5001b	454	dev_err(dev, "failed to get parent regmap\n");
ac4c1a9b SH	455	return PTR_ERR(imx_ldb->regmap);
	456	}
	457
17b5001b	458	imx_ldb->dev = dev;
ac4c1a9b SH	459
	460	if (of_id)
	461	imx_ldb->lvds_mux = of_id->data;
	462
	463	dual = of_property_read_bool(np, "fsl,dual-channel");
	464	if (dual)
	465	imx_ldb->ldb_ctrl \|= LDB_SPLIT_MODE_EN;
	466
	467	/*
4599934d	468	* There are three different possible clock mux configurations:
ac4c1a9b SH	469	* i.MX53: ipu1_di0_sel, ipu1_di1_sel
	470	* i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
	471	* i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
	472	* Map them all to di0_sel...di3_sel.
	473	*/
	474	for (i = 0; i < 4; i++) {
	475	char clkname[16];
	476
	477	sprintf(clkname, "di%d_sel", i);
	478	imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
	479	if (IS_ERR(imx_ldb->clk_sel[i])) {
	480	ret = PTR_ERR(imx_ldb->clk_sel[i]);
	481	imx_ldb->clk_sel[i] = NULL;
	482	break;
	483	}
	484	}
	485	if (i == 0)
	486	return ret;
	487
	488	for_each_child_of_node(np, child) {
	489	struct imx_ldb_channel *channel;
	490
	491	ret = of_property_read_u32(child, "reg", &i);
	492	if (ret \|\| i < 0 \|\| i > 1)
	493	return -EINVAL;
	494
	495	if (dual && i > 0) {
17b5001b	496	dev_warn(dev, "dual-channel mode, ignoring second output\n");
ac4c1a9b SH	497	continue;
	498	}
	499
	500	if (!of_device_is_available(child))
	501	continue;
	502
	503	channel = &imx_ldb->channel[i];
	504	channel->ldb = imx_ldb;
	505	channel->chno = i;
1b3f7675	506	channel->child = child;
ac4c1a9b SH	507
	508	edidp = of_get_property(child, "edid", &channel->edid_len);
	509	if (edidp) {
	510	channel->edid = kmemdup(edidp, channel->edid_len,
	511	GFP_KERNEL);
	512	} else {
	513	ret = of_get_drm_display_mode(child, &channel->mode, 0);
	514	if (!ret)
	515	channel->mode_valid = 1;
	516	}
	517
	518	ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
	519	if (ret)
	520	datawidth = 0;
	521	else if (datawidth != 18 && datawidth != 24)
	522	return -EINVAL;
	523
	524	mapping = of_get_data_mapping(child);
	525	switch (mapping) {
	526	case LVDS_BIT_MAP_SPWG:
	527	if (datawidth == 24) {
	528	if (i == 0 \|\| dual)
e5e1b166 AO	529	imx_ldb->ldb_ctrl \|=
e5e1b166 AO	530	LDB_DATA_WIDTH_CH0_24;
ac4c1a9b	531	if (i == 1 \|\| dual)
e5e1b166 AO	532	imx_ldb->ldb_ctrl \|=
e5e1b166 AO	533	LDB_DATA_WIDTH_CH1_24;
ac4c1a9b SH	534	}
	535	break;
	536	case LVDS_BIT_MAP_JEIDA:
	537	if (datawidth == 18) {
17b5001b	538	dev_err(dev, "JEIDA standard only supported in 24 bit\n");
ac4c1a9b SH	539	return -EINVAL;
	540	}
	541	if (i == 0 \|\| dual)
e5e1b166 AO	542	imx_ldb->ldb_ctrl \|= LDB_DATA_WIDTH_CH0_24 \|
e5e1b166 AO	543	LDB_BIT_MAP_CH0_JEIDA;
ac4c1a9b	544	if (i == 1 \|\| dual)
e5e1b166 AO	545	imx_ldb->ldb_ctrl \|= LDB_DATA_WIDTH_CH1_24 \|
e5e1b166 AO	546	LDB_BIT_MAP_CH1_JEIDA;
ac4c1a9b SH	547	break;
ac4c1a9b SH	548	default:
17b5001b	549	dev_err(dev, "data mapping not specified or invalid\n");
ac4c1a9b SH	550	return -EINVAL;
	551	}
	552
1b3f7675	553	ret = imx_ldb_register(drm, channel);
ac4c1a9b SH	554	if (ret)
ac4c1a9b SH	555	return ret;
ac4c1a9b SH	556	}
ac4c1a9b SH	557
17b5001b	558	dev_set_drvdata(dev, imx_ldb);
ac4c1a9b SH	559
	560	return 0;
	561	}
	562
17b5001b RK	563	static void imx_ldb_unbind(struct device dev, struct device master,
17b5001b RK	564	void *data)
ac4c1a9b	565	{
17b5001b	566	struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
ac4c1a9b SH	567	int i;
	568
	569	for (i = 0; i < 2; i++) {
	570	struct imx_ldb_channel *channel = &imx_ldb->channel[i];
ac4c1a9b	571
d9fdb9fb RK	572	if (!channel->connector.funcs)
	573	continue;
	574
1b3f7675 RK	575	channel->connector.funcs->destroy(&channel->connector);
1b3f7675 RK	576	channel->encoder.funcs->destroy(&channel->encoder);
f4876ffe PS	577
f4876ffe PS	578	kfree(channel->edid);
ac4c1a9b	579	}
17b5001b	580	}
ac4c1a9b	581
17b5001b RK	582	static const struct component_ops imx_ldb_ops = {
	583	.bind = imx_ldb_bind,
	584	.unbind = imx_ldb_unbind,
	585	};
	586
	587	static int imx_ldb_probe(struct platform_device *pdev)
	588	{
	589	return component_add(&pdev->dev, &imx_ldb_ops);
	590	}
	591
	592	static int imx_ldb_remove(struct platform_device *pdev)
	593	{
	594	component_del(&pdev->dev, &imx_ldb_ops);
ac4c1a9b SH	595	return 0;
	596	}
	597
	598	static struct platform_driver imx_ldb_driver = {
	599	.probe = imx_ldb_probe,
	600	.remove = imx_ldb_remove,
	601	.driver = {
	602	.of_match_table = imx_ldb_dt_ids,
	603	.name = DRIVER_NAME,
ac4c1a9b SH	604	},
	605	};
	606
	607	module_platform_driver(imx_ldb_driver);
	608
	609	MODULE_DESCRIPTION("i.MX LVDS driver");
	610	MODULE_AUTHOR("Sascha Hauer, Pengutronix");
	611	MODULE_LICENSE("GPL");
bc627387	612	MODULE_ALIAS("platform:" DRIVER_NAME);