Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | /* |
2 | * i.MX drm driver - LVDS display bridge | |
3 | * | |
4 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
ac4c1a9b SH |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
17b5001b | 18 | #include <linux/component.h> |
ac4c1a9b | 19 | #include <drm/drmP.h> |
49f98bc4 | 20 | #include <drm/drm_atomic.h> |
255c35f8 | 21 | #include <drm/drm_atomic_helper.h> |
ac4c1a9b SH |
22 | #include <drm/drm_fb_helper.h> |
23 | #include <drm/drm_crtc_helper.h> | |
53141e42 | 24 | #include <drm/drm_of.h> |
751e2676 | 25 | #include <drm/drm_panel.h> |
ac4c1a9b SH |
26 | #include <linux/mfd/syscon.h> |
27 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
ac4c1a9b | 28 | #include <linux/of_device.h> |
751e2676 | 29 | #include <linux/of_graph.h> |
c82b4d73 | 30 | #include <video/of_display_timing.h> |
ac4c1a9b SH |
31 | #include <video/of_videomode.h> |
32 | #include <linux/regmap.h> | |
33 | #include <linux/videodev2.h> | |
34 | ||
35 | #include "imx-drm.h" | |
36 | ||
37 | #define DRIVER_NAME "imx-ldb" | |
38 | ||
39 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
40 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
41 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
42 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
43 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
44 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
45 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
46 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
47 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
48 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
49 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
50 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
51 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
52 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
53 | ||
ac4c1a9b SH |
54 | struct imx_ldb; |
55 | ||
56 | struct imx_ldb_channel { | |
57 | struct imx_ldb *ldb; | |
58 | struct drm_connector connector; | |
49f98bc4 | 59 | struct drm_encoder encoder; |
dc80d703 PST |
60 | |
61 | /* Defines what is connected to the ldb, only one at a time */ | |
751e2676 | 62 | struct drm_panel *panel; |
dc80d703 PST |
63 | struct drm_bridge *bridge; |
64 | ||
1b3f7675 | 65 | struct device_node *child; |
a6d206e2 | 66 | struct i2c_adapter *ddc; |
ac4c1a9b SH |
67 | int chno; |
68 | void *edid; | |
69 | int edid_len; | |
70 | struct drm_display_mode mode; | |
71 | int mode_valid; | |
49f98bc4 | 72 | u32 bus_format; |
fafc79ef | 73 | u32 bus_flags; |
ac4c1a9b SH |
74 | }; |
75 | ||
3df07390 PZ |
76 | static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c) |
77 | { | |
78 | return container_of(c, struct imx_ldb_channel, connector); | |
79 | } | |
80 | ||
49f98bc4 PZ |
81 | static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e) |
82 | { | |
83 | return container_of(e, struct imx_ldb_channel, encoder); | |
84 | } | |
85 | ||
ac4c1a9b SH |
86 | struct bus_mux { |
87 | int reg; | |
88 | int shift; | |
89 | int mask; | |
90 | }; | |
91 | ||
92 | struct imx_ldb { | |
93 | struct regmap *regmap; | |
94 | struct device *dev; | |
95 | struct imx_ldb_channel channel[2]; | |
96 | struct clk *clk[2]; /* our own clock */ | |
97 | struct clk *clk_sel[4]; /* parent of display clock */ | |
3973aff0 | 98 | struct clk *clk_parent[4]; /* original parent of clk_sel */ |
ac4c1a9b SH |
99 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ |
100 | u32 ldb_ctrl; | |
101 | const struct bus_mux *lvds_mux; | |
102 | }; | |
103 | ||
104 | static enum drm_connector_status imx_ldb_connector_detect( | |
105 | struct drm_connector *connector, bool force) | |
106 | { | |
107 | return connector_status_connected; | |
108 | } | |
109 | ||
49f98bc4 PZ |
110 | static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch, |
111 | u32 bus_format) | |
032003c5 LY |
112 | { |
113 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
114 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
115 | ||
116 | switch (bus_format) { | |
117 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
032003c5 LY |
118 | break; |
119 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: | |
032003c5 LY |
120 | if (imx_ldb_ch->chno == 0 || dual) |
121 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; | |
122 | if (imx_ldb_ch->chno == 1 || dual) | |
123 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; | |
124 | break; | |
125 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: | |
032003c5 LY |
126 | if (imx_ldb_ch->chno == 0 || dual) |
127 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | | |
128 | LDB_BIT_MAP_CH0_JEIDA; | |
129 | if (imx_ldb_ch->chno == 1 || dual) | |
130 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | | |
131 | LDB_BIT_MAP_CH1_JEIDA; | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
ac4c1a9b SH |
136 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
137 | { | |
138 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
139 | int num_modes = 0; | |
140 | ||
751e2676 PZ |
141 | if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && |
142 | imx_ldb_ch->panel->funcs->get_modes) { | |
143 | num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); | |
144 | if (num_modes > 0) | |
145 | return num_modes; | |
146 | } | |
147 | ||
a6d206e2 SL |
148 | if (!imx_ldb_ch->edid && imx_ldb_ch->ddc) |
149 | imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc); | |
150 | ||
ac4c1a9b SH |
151 | if (imx_ldb_ch->edid) { |
152 | drm_mode_connector_update_edid_property(connector, | |
153 | imx_ldb_ch->edid); | |
154 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
155 | } | |
156 | ||
157 | if (imx_ldb_ch->mode_valid) { | |
158 | struct drm_display_mode *mode; | |
159 | ||
160 | mode = drm_mode_create(connector->dev); | |
9f9b036f FE |
161 | if (!mode) |
162 | return -EINVAL; | |
ac4c1a9b SH |
163 | drm_mode_copy(mode, &imx_ldb_ch->mode); |
164 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
165 | drm_mode_probed_add(connector, mode); | |
166 | num_modes++; | |
167 | } | |
168 | ||
169 | return num_modes; | |
170 | } | |
171 | ||
ac4c1a9b SH |
172 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
173 | struct drm_connector *connector) | |
174 | { | |
175 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
176 | ||
49f98bc4 | 177 | return &imx_ldb_ch->encoder; |
ac4c1a9b SH |
178 | } |
179 | ||
ac4c1a9b SH |
180 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, |
181 | unsigned long serial_clk, unsigned long di_clk) | |
182 | { | |
183 | int ret; | |
184 | ||
185 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
186 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
187 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
188 | ||
189 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
190 | clk_get_rate(ldb->clk_pll[chno])); | |
191 | ||
192 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
193 | clk_get_rate(ldb->clk[chno]), | |
194 | (long int)di_clk); | |
195 | clk_set_rate(ldb->clk[chno], di_clk); | |
196 | ||
197 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
198 | clk_get_rate(ldb->clk[chno])); | |
199 | ||
200 | /* set display clock mux to LDB input clock */ | |
201 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 202 | if (ret) |
e5e1b166 AO |
203 | dev_err(ldb->dev, |
204 | "unable to set di%d parent clock to ldb_di%d\n", mux, | |
205 | chno); | |
ac4c1a9b SH |
206 | } |
207 | ||
f6e396e5 | 208 | static void imx_ldb_encoder_enable(struct drm_encoder *encoder) |
ac4c1a9b | 209 | { |
49f98bc4 | 210 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
ac4c1a9b SH |
211 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
212 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
53141e42 | 213 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b | 214 | |
751e2676 PZ |
215 | drm_panel_prepare(imx_ldb_ch->panel); |
216 | ||
ac4c1a9b | 217 | if (dual) { |
f6e396e5 LY |
218 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); |
219 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); | |
220 | ||
ac4c1a9b SH |
221 | clk_prepare_enable(ldb->clk[0]); |
222 | clk_prepare_enable(ldb->clk[1]); | |
f6e396e5 LY |
223 | } else { |
224 | clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); | |
ac4c1a9b SH |
225 | } |
226 | ||
227 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
228 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
229 | if (mux == 0 || ldb->lvds_mux) | |
230 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
231 | else if (mux == 1) | |
232 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
233 | } | |
234 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
235 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
236 | if (mux == 1 || ldb->lvds_mux) | |
237 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
238 | else if (mux == 0) | |
239 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
240 | } | |
241 | ||
242 | if (ldb->lvds_mux) { | |
243 | const struct bus_mux *lvds_mux = NULL; | |
244 | ||
245 | if (imx_ldb_ch == &ldb->channel[0]) | |
246 | lvds_mux = &ldb->lvds_mux[0]; | |
247 | else if (imx_ldb_ch == &ldb->channel[1]) | |
248 | lvds_mux = &ldb->lvds_mux[1]; | |
249 | ||
250 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
251 | mux << lvds_mux->shift); | |
252 | } | |
253 | ||
254 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
751e2676 PZ |
255 | |
256 | drm_panel_enable(imx_ldb_ch->panel); | |
ac4c1a9b SH |
257 | } |
258 | ||
3a2ad502 PZ |
259 | static void |
260 | imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder, | |
261 | struct drm_crtc_state *crtc_state, | |
262 | struct drm_connector_state *connector_state) | |
ac4c1a9b | 263 | { |
49f98bc4 | 264 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
3a2ad502 | 265 | struct drm_display_mode *mode = &crtc_state->adjusted_mode; |
ac4c1a9b SH |
266 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
267 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
51dac94e PZ |
268 | unsigned long serial_clk; |
269 | unsigned long di_clk = mode->clock * 1000; | |
53141e42 | 270 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
49f98bc4 | 271 | u32 bus_format = imx_ldb_ch->bus_format; |
ac4c1a9b SH |
272 | |
273 | if (mode->clock > 170000) { | |
274 | dev_warn(ldb->dev, | |
275 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
276 | } | |
277 | if (mode->clock > 85000 && !dual) { | |
278 | dev_warn(ldb->dev, | |
279 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
280 | } | |
281 | ||
51dac94e PZ |
282 | if (dual) { |
283 | serial_clk = 3500UL * mode->clock; | |
284 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
285 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
286 | } else { | |
287 | serial_clk = 7000UL * mode->clock; | |
288 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | |
289 | di_clk); | |
290 | } | |
291 | ||
ac4c1a9b | 292 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
49f98bc4 | 293 | if (imx_ldb_ch == &ldb->channel[0] || dual) { |
ac4c1a9b SH |
294 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
295 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
296 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
297 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
298 | } | |
49f98bc4 | 299 | if (imx_ldb_ch == &ldb->channel[1] || dual) { |
ac4c1a9b SH |
300 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
301 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
302 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
303 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
304 | } | |
49f98bc4 PZ |
305 | |
306 | if (!bus_format) { | |
3a2ad502 PZ |
307 | struct drm_connector *connector = connector_state->connector; |
308 | struct drm_display_info *di = &connector->display_info; | |
49f98bc4 | 309 | |
3a2ad502 PZ |
310 | if (di->num_bus_formats) |
311 | bus_format = di->bus_formats[0]; | |
49f98bc4 PZ |
312 | } |
313 | imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format); | |
ac4c1a9b SH |
314 | } |
315 | ||
316 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
317 | { | |
49f98bc4 | 318 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
ac4c1a9b | 319 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
3973aff0 | 320 | int mux, ret; |
ac4c1a9b SH |
321 | |
322 | /* | |
323 | * imx_ldb_encoder_disable is called by | |
324 | * drm_helper_disable_unused_functions without | |
325 | * the encoder being enabled before. | |
326 | */ | |
327 | if (imx_ldb_ch == &ldb->channel[0] && | |
328 | (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) | |
329 | return; | |
330 | else if (imx_ldb_ch == &ldb->channel[1] && | |
331 | (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) | |
332 | return; | |
333 | ||
751e2676 PZ |
334 | drm_panel_disable(imx_ldb_ch->panel); |
335 | ||
ac4c1a9b SH |
336 | if (imx_ldb_ch == &ldb->channel[0]) |
337 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
338 | else if (imx_ldb_ch == &ldb->channel[1]) | |
339 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
340 | ||
341 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
342 | ||
343 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
344 | clk_disable_unprepare(ldb->clk[0]); | |
345 | clk_disable_unprepare(ldb->clk[1]); | |
346 | } | |
751e2676 | 347 | |
3973aff0 PZ |
348 | if (ldb->lvds_mux) { |
349 | const struct bus_mux *lvds_mux = NULL; | |
350 | ||
351 | if (imx_ldb_ch == &ldb->channel[0]) | |
352 | lvds_mux = &ldb->lvds_mux[0]; | |
353 | else if (imx_ldb_ch == &ldb->channel[1]) | |
354 | lvds_mux = &ldb->lvds_mux[1]; | |
355 | ||
356 | regmap_read(ldb->regmap, lvds_mux->reg, &mux); | |
357 | mux &= lvds_mux->mask; | |
358 | mux >>= lvds_mux->shift; | |
359 | } else { | |
360 | mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; | |
361 | } | |
362 | ||
363 | /* set display clock mux back to original input clock */ | |
364 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); | |
365 | if (ret) | |
366 | dev_err(ldb->dev, | |
367 | "unable to set di%d parent clock to original parent\n", | |
368 | mux); | |
369 | ||
751e2676 | 370 | drm_panel_unprepare(imx_ldb_ch->panel); |
ac4c1a9b SH |
371 | } |
372 | ||
49f98bc4 PZ |
373 | static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder, |
374 | struct drm_crtc_state *crtc_state, | |
375 | struct drm_connector_state *conn_state) | |
376 | { | |
377 | struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); | |
378 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
379 | struct drm_display_info *di = &conn_state->connector->display_info; | |
380 | u32 bus_format = imx_ldb_ch->bus_format; | |
381 | ||
382 | /* Bus format description in DT overrides connector display info. */ | |
fafc79ef | 383 | if (!bus_format && di->num_bus_formats) { |
49f98bc4 | 384 | bus_format = di->bus_formats[0]; |
fafc79ef LW |
385 | imx_crtc_state->bus_flags = di->bus_flags; |
386 | } else { | |
387 | bus_format = imx_ldb_ch->bus_format; | |
388 | imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags; | |
389 | } | |
49f98bc4 PZ |
390 | switch (bus_format) { |
391 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
392 | imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18; | |
393 | break; | |
394 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: | |
395 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: | |
396 | imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
397 | break; | |
398 | default: | |
399 | return -EINVAL; | |
400 | } | |
401 | ||
402 | imx_crtc_state->di_hsync_pin = 2; | |
403 | imx_crtc_state->di_vsync_pin = 3; | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | ||
7ae847dd | 409 | static const struct drm_connector_funcs imx_ldb_connector_funcs = { |
f6e396e5 | 410 | .dpms = drm_atomic_helper_connector_dpms, |
ac4c1a9b SH |
411 | .fill_modes = drm_helper_probe_single_connector_modes, |
412 | .detect = imx_ldb_connector_detect, | |
1b3f7675 | 413 | .destroy = imx_drm_connector_destroy, |
255c35f8 LY |
414 | .reset = drm_atomic_helper_connector_reset, |
415 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
416 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
ac4c1a9b SH |
417 | }; |
418 | ||
7ae847dd | 419 | static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { |
ac4c1a9b SH |
420 | .get_modes = imx_ldb_connector_get_modes, |
421 | .best_encoder = imx_ldb_connector_best_encoder, | |
ac4c1a9b SH |
422 | }; |
423 | ||
7ae847dd | 424 | static const struct drm_encoder_funcs imx_ldb_encoder_funcs = { |
1b3f7675 | 425 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
426 | }; |
427 | ||
7ae847dd | 428 | static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { |
3a2ad502 | 429 | .atomic_mode_set = imx_ldb_encoder_atomic_mode_set, |
f6e396e5 | 430 | .enable = imx_ldb_encoder_enable, |
ac4c1a9b | 431 | .disable = imx_ldb_encoder_disable, |
49f98bc4 | 432 | .atomic_check = imx_ldb_encoder_atomic_check, |
ac4c1a9b SH |
433 | }; |
434 | ||
435 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
436 | { | |
437 | char clkname[16]; | |
438 | ||
98dd3b2a | 439 | snprintf(clkname, sizeof(clkname), "di%d", chno); |
ac4c1a9b SH |
440 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); |
441 | if (IS_ERR(ldb->clk[chno])) | |
442 | return PTR_ERR(ldb->clk[chno]); | |
443 | ||
98dd3b2a | 444 | snprintf(clkname, sizeof(clkname), "di%d_pll", chno); |
ac4c1a9b | 445 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); |
ac4c1a9b | 446 | |
1f933fa8 | 447 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
448 | } |
449 | ||
1b3f7675 RK |
450 | static int imx_ldb_register(struct drm_device *drm, |
451 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 452 | { |
ac4c1a9b | 453 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
49f98bc4 | 454 | struct drm_encoder *encoder = &imx_ldb_ch->encoder; |
1b3f7675 RK |
455 | int ret; |
456 | ||
49f98bc4 | 457 | ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child); |
1b3f7675 RK |
458 | if (ret) |
459 | return ret; | |
ac4c1a9b SH |
460 | |
461 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
462 | if (ret) | |
463 | return ret; | |
1b3f7675 | 464 | |
ac4c1a9b | 465 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 466 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
467 | if (ret) |
468 | return ret; | |
469 | } | |
470 | ||
49f98bc4 PZ |
471 | drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs); |
472 | drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs, | |
473 | DRM_MODE_ENCODER_LVDS, NULL); | |
ac4c1a9b | 474 | |
dc80d703 PST |
475 | if (imx_ldb_ch->bridge) { |
476 | imx_ldb_ch->bridge->encoder = encoder; | |
477 | ||
478 | imx_ldb_ch->encoder.bridge = imx_ldb_ch->bridge; | |
479 | ret = drm_bridge_attach(drm, imx_ldb_ch->bridge); | |
480 | if (ret) { | |
481 | DRM_ERROR("Failed to initialize bridge with drm\n"); | |
482 | return ret; | |
483 | } | |
484 | } else { | |
485 | /* | |
486 | * We want to add the connector whenever there is no bridge | |
487 | * that brings its own, not only when there is a panel. For | |
488 | * historical reasons, the ldb driver can also work without | |
489 | * a panel. | |
490 | */ | |
491 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
492 | &imx_ldb_connector_helper_funcs); | |
493 | drm_connector_init(drm, &imx_ldb_ch->connector, | |
494 | &imx_ldb_connector_funcs, | |
495 | DRM_MODE_CONNECTOR_LVDS); | |
496 | drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, | |
497 | encoder); | |
498 | } | |
ac4c1a9b | 499 | |
7075ba79 LS |
500 | if (imx_ldb_ch->panel) { |
501 | ret = drm_panel_attach(imx_ldb_ch->panel, | |
502 | &imx_ldb_ch->connector); | |
503 | if (ret) | |
504 | return ret; | |
505 | } | |
751e2676 | 506 | |
ac4c1a9b SH |
507 | return 0; |
508 | } | |
509 | ||
510 | enum { | |
511 | LVDS_BIT_MAP_SPWG, | |
512 | LVDS_BIT_MAP_JEIDA | |
513 | }; | |
514 | ||
5e501ed7 PZ |
515 | struct imx_ldb_bit_mapping { |
516 | u32 bus_format; | |
517 | u32 datawidth; | |
518 | const char * const mapping; | |
ac4c1a9b SH |
519 | }; |
520 | ||
5e501ed7 PZ |
521 | static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { |
522 | { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, | |
523 | { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, | |
524 | { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, | |
525 | }; | |
526 | ||
527 | static u32 of_get_bus_format(struct device *dev, struct device_node *np) | |
ac4c1a9b SH |
528 | { |
529 | const char *bm; | |
5e501ed7 | 530 | u32 datawidth = 0; |
ac4c1a9b SH |
531 | int ret, i; |
532 | ||
533 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
534 | if (ret < 0) | |
535 | return ret; | |
536 | ||
5e501ed7 PZ |
537 | of_property_read_u32(np, "fsl,data-width", &datawidth); |
538 | ||
539 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { | |
540 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && | |
541 | datawidth == imx_ldb_bit_mappings[i].datawidth) | |
542 | return imx_ldb_bit_mappings[i].bus_format; | |
543 | } | |
544 | ||
545 | dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); | |
ac4c1a9b | 546 | |
5e501ed7 | 547 | return -ENOENT; |
ac4c1a9b SH |
548 | } |
549 | ||
550 | static struct bus_mux imx6q_lvds_mux[2] = { | |
551 | { | |
552 | .reg = IOMUXC_GPR3, | |
553 | .shift = 6, | |
554 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
555 | }, { | |
556 | .reg = IOMUXC_GPR3, | |
557 | .shift = 8, | |
558 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
559 | } | |
560 | }; | |
561 | ||
562 | /* | |
563 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
564 | * of_match_device will walk through this list and take the first entry | |
565 | * matching any of its compatible values. Therefore, the more generic | |
566 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
567 | */ | |
568 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
569 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
570 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
571 | { } | |
572 | }; | |
573 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
574 | ||
dc80d703 PST |
575 | static int imx_ldb_panel_ddc(struct device *dev, |
576 | struct imx_ldb_channel *channel, struct device_node *child) | |
577 | { | |
578 | struct device_node *ddc_node; | |
579 | const u8 *edidp; | |
580 | int ret; | |
581 | ||
582 | ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0); | |
583 | if (ddc_node) { | |
584 | channel->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
585 | of_node_put(ddc_node); | |
586 | if (!channel->ddc) { | |
587 | dev_warn(dev, "failed to get ddc i2c adapter\n"); | |
588 | return -EPROBE_DEFER; | |
589 | } | |
590 | } | |
591 | ||
592 | if (!channel->ddc) { | |
593 | /* if no DDC available, fallback to hardcoded EDID */ | |
594 | dev_dbg(dev, "no ddc available\n"); | |
595 | ||
596 | edidp = of_get_property(child, "edid", | |
597 | &channel->edid_len); | |
598 | if (edidp) { | |
599 | channel->edid = kmemdup(edidp, | |
600 | channel->edid_len, | |
601 | GFP_KERNEL); | |
602 | } else if (!channel->panel) { | |
603 | /* fallback to display-timings node */ | |
604 | ret = of_get_drm_display_mode(child, | |
605 | &channel->mode, | |
606 | &channel->bus_flags, | |
607 | OF_USE_NATIVE_MODE); | |
608 | if (!ret) | |
609 | channel->mode_valid = 1; | |
610 | } | |
611 | } | |
612 | return 0; | |
613 | } | |
614 | ||
17b5001b | 615 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 616 | { |
1b3f7675 | 617 | struct drm_device *drm = data; |
17b5001b | 618 | struct device_node *np = dev->of_node; |
ac4c1a9b | 619 | const struct of_device_id *of_id = |
17b5001b | 620 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b | 621 | struct device_node *child; |
ac4c1a9b | 622 | struct imx_ldb *imx_ldb; |
ac4c1a9b SH |
623 | int dual; |
624 | int ret; | |
625 | int i; | |
626 | ||
17b5001b | 627 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
628 | if (!imx_ldb) |
629 | return -ENOMEM; | |
630 | ||
631 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
632 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 633 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
634 | return PTR_ERR(imx_ldb->regmap); |
635 | } | |
636 | ||
17b5001b | 637 | imx_ldb->dev = dev; |
ac4c1a9b SH |
638 | |
639 | if (of_id) | |
640 | imx_ldb->lvds_mux = of_id->data; | |
641 | ||
642 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
643 | if (dual) | |
644 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
645 | ||
646 | /* | |
4599934d | 647 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
648 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
649 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
650 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
651 | * Map them all to di0_sel...di3_sel. | |
652 | */ | |
653 | for (i = 0; i < 4; i++) { | |
654 | char clkname[16]; | |
655 | ||
656 | sprintf(clkname, "di%d_sel", i); | |
657 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
658 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
659 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
660 | imx_ldb->clk_sel[i] = NULL; | |
661 | break; | |
662 | } | |
3973aff0 PZ |
663 | |
664 | imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); | |
ac4c1a9b SH |
665 | } |
666 | if (i == 0) | |
667 | return ret; | |
668 | ||
669 | for_each_child_of_node(np, child) { | |
670 | struct imx_ldb_channel *channel; | |
620011e0 | 671 | struct device_node *ep; |
032003c5 | 672 | int bus_format; |
ac4c1a9b SH |
673 | |
674 | ret = of_property_read_u32(child, "reg", &i); | |
675 | if (ret || i < 0 || i > 1) | |
676 | return -EINVAL; | |
677 | ||
678 | if (dual && i > 0) { | |
17b5001b | 679 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
680 | continue; |
681 | } | |
682 | ||
683 | if (!of_device_is_available(child)) | |
684 | continue; | |
685 | ||
686 | channel = &imx_ldb->channel[i]; | |
687 | channel->ldb = imx_ldb; | |
688 | channel->chno = i; | |
1b3f7675 | 689 | channel->child = child; |
ac4c1a9b | 690 | |
751e2676 PZ |
691 | /* |
692 | * The output port is port@4 with an external 4-port mux or | |
693 | * port@2 with the internal 2-port mux. | |
694 | */ | |
620011e0 PZ |
695 | ep = of_graph_get_endpoint_by_regs(child, |
696 | imx_ldb->lvds_mux ? 4 : 2, | |
697 | -1); | |
698 | if (ep) { | |
699 | struct device_node *remote; | |
700 | ||
701 | remote = of_graph_get_remote_port_parent(ep); | |
702 | of_node_put(ep); | |
dc80d703 | 703 | if (remote) { |
620011e0 | 704 | channel->panel = of_drm_find_panel(remote); |
dc80d703 PST |
705 | channel->bridge = of_drm_find_bridge(remote); |
706 | } else | |
620011e0 PZ |
707 | return -EPROBE_DEFER; |
708 | of_node_put(remote); | |
751e2676 | 709 | |
dc80d703 PST |
710 | if (!channel->panel && !channel->bridge) { |
711 | dev_err(dev, "panel/bridge not found: %s\n", | |
712 | remote->full_name); | |
a6d206e2 SL |
713 | return -EPROBE_DEFER; |
714 | } | |
715 | } | |
716 | ||
dc80d703 PST |
717 | /* panel ddc only if there is no bridge */ |
718 | if (!channel->bridge) { | |
719 | ret = imx_ldb_panel_ddc(dev, channel, child); | |
720 | if (ret) | |
721 | return ret; | |
ac4c1a9b SH |
722 | } |
723 | ||
032003c5 LY |
724 | bus_format = of_get_bus_format(dev, child); |
725 | if (bus_format == -EINVAL) { | |
5e501ed7 PZ |
726 | /* |
727 | * If no bus format was specified in the device tree, | |
728 | * we can still get it from the connected panel later. | |
729 | */ | |
730 | if (channel->panel && channel->panel->funcs && | |
731 | channel->panel->funcs->get_modes) | |
032003c5 | 732 | bus_format = 0; |
5e501ed7 | 733 | } |
032003c5 | 734 | if (bus_format < 0) { |
5e501ed7 | 735 | dev_err(dev, "could not determine data mapping: %d\n", |
032003c5 LY |
736 | bus_format); |
737 | return bus_format; | |
ac4c1a9b | 738 | } |
49f98bc4 | 739 | channel->bus_format = bus_format; |
ac4c1a9b | 740 | |
1b3f7675 | 741 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
742 | if (ret) |
743 | return ret; | |
ac4c1a9b SH |
744 | } |
745 | ||
17b5001b | 746 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
17b5001b RK |
751 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
752 | void *data) | |
ac4c1a9b | 753 | { |
17b5001b | 754 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
755 | int i; |
756 | ||
757 | for (i = 0; i < 2; i++) { | |
758 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 759 | |
d9fdb9fb RK |
760 | if (!channel->connector.funcs) |
761 | continue; | |
762 | ||
1b3f7675 | 763 | channel->connector.funcs->destroy(&channel->connector); |
49f98bc4 | 764 | channel->encoder.funcs->destroy(&channel->encoder); |
f4876ffe PS |
765 | |
766 | kfree(channel->edid); | |
a6d206e2 | 767 | i2c_put_adapter(channel->ddc); |
ac4c1a9b | 768 | } |
17b5001b | 769 | } |
ac4c1a9b | 770 | |
17b5001b RK |
771 | static const struct component_ops imx_ldb_ops = { |
772 | .bind = imx_ldb_bind, | |
773 | .unbind = imx_ldb_unbind, | |
774 | }; | |
775 | ||
776 | static int imx_ldb_probe(struct platform_device *pdev) | |
777 | { | |
778 | return component_add(&pdev->dev, &imx_ldb_ops); | |
779 | } | |
780 | ||
781 | static int imx_ldb_remove(struct platform_device *pdev) | |
782 | { | |
783 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
784 | return 0; |
785 | } | |
786 | ||
787 | static struct platform_driver imx_ldb_driver = { | |
788 | .probe = imx_ldb_probe, | |
789 | .remove = imx_ldb_remove, | |
790 | .driver = { | |
791 | .of_match_table = imx_ldb_dt_ids, | |
792 | .name = DRIVER_NAME, | |
ac4c1a9b SH |
793 | }, |
794 | }; | |
795 | ||
796 | module_platform_driver(imx_ldb_driver); | |
797 | ||
798 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
799 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
800 | MODULE_LICENSE("GPL"); | |
bc627387 | 801 | MODULE_ALIAS("platform:" DRIVER_NAME); |