Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | /* |
2 | * i.MX drm driver - LVDS display bridge | |
3 | * | |
4 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
ac4c1a9b SH |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
17b5001b | 18 | #include <linux/component.h> |
ac4c1a9b | 19 | #include <drm/drmP.h> |
255c35f8 | 20 | #include <drm/drm_atomic_helper.h> |
ac4c1a9b SH |
21 | #include <drm/drm_fb_helper.h> |
22 | #include <drm/drm_crtc_helper.h> | |
53141e42 | 23 | #include <drm/drm_of.h> |
751e2676 | 24 | #include <drm/drm_panel.h> |
ac4c1a9b SH |
25 | #include <linux/mfd/syscon.h> |
26 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
ac4c1a9b | 27 | #include <linux/of_device.h> |
751e2676 | 28 | #include <linux/of_graph.h> |
c82b4d73 | 29 | #include <video/of_display_timing.h> |
ac4c1a9b SH |
30 | #include <video/of_videomode.h> |
31 | #include <linux/regmap.h> | |
32 | #include <linux/videodev2.h> | |
33 | ||
34 | #include "imx-drm.h" | |
35 | ||
36 | #define DRIVER_NAME "imx-ldb" | |
37 | ||
38 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
39 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
40 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
41 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
42 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
43 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
44 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
45 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
46 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
47 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
48 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
49 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
50 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
51 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
52 | ||
53 | #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector) | |
54 | #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder) | |
55 | ||
56 | struct imx_ldb; | |
57 | ||
58 | struct imx_ldb_channel { | |
59 | struct imx_ldb *ldb; | |
60 | struct drm_connector connector; | |
ac4c1a9b | 61 | struct drm_encoder encoder; |
751e2676 | 62 | struct drm_panel *panel; |
1b3f7675 | 63 | struct device_node *child; |
a6d206e2 | 64 | struct i2c_adapter *ddc; |
ac4c1a9b SH |
65 | int chno; |
66 | void *edid; | |
67 | int edid_len; | |
68 | struct drm_display_mode mode; | |
69 | int mode_valid; | |
5e501ed7 | 70 | int bus_format; |
ac4c1a9b SH |
71 | }; |
72 | ||
73 | struct bus_mux { | |
74 | int reg; | |
75 | int shift; | |
76 | int mask; | |
77 | }; | |
78 | ||
79 | struct imx_ldb { | |
80 | struct regmap *regmap; | |
81 | struct device *dev; | |
82 | struct imx_ldb_channel channel[2]; | |
83 | struct clk *clk[2]; /* our own clock */ | |
84 | struct clk *clk_sel[4]; /* parent of display clock */ | |
3973aff0 | 85 | struct clk *clk_parent[4]; /* original parent of clk_sel */ |
ac4c1a9b SH |
86 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ |
87 | u32 ldb_ctrl; | |
88 | const struct bus_mux *lvds_mux; | |
89 | }; | |
90 | ||
91 | static enum drm_connector_status imx_ldb_connector_detect( | |
92 | struct drm_connector *connector, bool force) | |
93 | { | |
94 | return connector_status_connected; | |
95 | } | |
96 | ||
ac4c1a9b SH |
97 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
98 | { | |
99 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
100 | int num_modes = 0; | |
101 | ||
751e2676 PZ |
102 | if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && |
103 | imx_ldb_ch->panel->funcs->get_modes) { | |
5e501ed7 PZ |
104 | struct drm_display_info *di = &connector->display_info; |
105 | ||
751e2676 | 106 | num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); |
5e501ed7 PZ |
107 | if (!imx_ldb_ch->bus_format && di->num_bus_formats) |
108 | imx_ldb_ch->bus_format = di->bus_formats[0]; | |
751e2676 PZ |
109 | if (num_modes > 0) |
110 | return num_modes; | |
111 | } | |
112 | ||
a6d206e2 SL |
113 | if (!imx_ldb_ch->edid && imx_ldb_ch->ddc) |
114 | imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc); | |
115 | ||
ac4c1a9b SH |
116 | if (imx_ldb_ch->edid) { |
117 | drm_mode_connector_update_edid_property(connector, | |
118 | imx_ldb_ch->edid); | |
119 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
120 | } | |
121 | ||
122 | if (imx_ldb_ch->mode_valid) { | |
123 | struct drm_display_mode *mode; | |
124 | ||
125 | mode = drm_mode_create(connector->dev); | |
9f9b036f FE |
126 | if (!mode) |
127 | return -EINVAL; | |
ac4c1a9b SH |
128 | drm_mode_copy(mode, &imx_ldb_ch->mode); |
129 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
130 | drm_mode_probed_add(connector, mode); | |
131 | num_modes++; | |
132 | } | |
133 | ||
134 | return num_modes; | |
135 | } | |
136 | ||
ac4c1a9b SH |
137 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
138 | struct drm_connector *connector) | |
139 | { | |
140 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
141 | ||
142 | return &imx_ldb_ch->encoder; | |
143 | } | |
144 | ||
145 | static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode) | |
146 | { | |
147 | } | |
148 | ||
ac4c1a9b SH |
149 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, |
150 | unsigned long serial_clk, unsigned long di_clk) | |
151 | { | |
152 | int ret; | |
153 | ||
154 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
155 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
156 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
157 | ||
158 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
159 | clk_get_rate(ldb->clk_pll[chno])); | |
160 | ||
161 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
162 | clk_get_rate(ldb->clk[chno]), | |
163 | (long int)di_clk); | |
164 | clk_set_rate(ldb->clk[chno], di_clk); | |
165 | ||
166 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
167 | clk_get_rate(ldb->clk[chno])); | |
168 | ||
169 | /* set display clock mux to LDB input clock */ | |
170 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 171 | if (ret) |
e5e1b166 AO |
172 | dev_err(ldb->dev, |
173 | "unable to set di%d parent clock to ldb_di%d\n", mux, | |
174 | chno); | |
ac4c1a9b SH |
175 | } |
176 | ||
177 | static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) | |
178 | { | |
179 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
180 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
5e501ed7 | 181 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; |
2872c807 | 182 | u32 bus_format; |
ac4c1a9b | 183 | |
5e501ed7 PZ |
184 | switch (imx_ldb_ch->bus_format) { |
185 | default: | |
186 | dev_warn(ldb->dev, | |
187 | "could not determine data mapping, default to 18-bit \"spwg\"\n"); | |
188 | /* fallthrough */ | |
189 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
190 | bus_format = MEDIA_BUS_FMT_RGB666_1X18; | |
000d73fc | 191 | break; |
5e501ed7 PZ |
192 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: |
193 | bus_format = MEDIA_BUS_FMT_RGB888_1X24; | |
194 | if (imx_ldb_ch->chno == 0 || dual) | |
195 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; | |
196 | if (imx_ldb_ch->chno == 1 || dual) | |
197 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; | |
000d73fc | 198 | break; |
5e501ed7 | 199 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: |
2872c807 | 200 | bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
5e501ed7 PZ |
201 | if (imx_ldb_ch->chno == 0 || dual) |
202 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | | |
203 | LDB_BIT_MAP_CH0_JEIDA; | |
204 | if (imx_ldb_ch->chno == 1 || dual) | |
205 | ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | | |
206 | LDB_BIT_MAP_CH1_JEIDA; | |
207 | break; | |
000d73fc MN |
208 | } |
209 | ||
2872c807 | 210 | imx_drm_set_bus_format(encoder, bus_format); |
ac4c1a9b SH |
211 | } |
212 | ||
213 | static void imx_ldb_encoder_commit(struct drm_encoder *encoder) | |
214 | { | |
215 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
216 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
217 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
53141e42 | 218 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b | 219 | |
751e2676 PZ |
220 | drm_panel_prepare(imx_ldb_ch->panel); |
221 | ||
ac4c1a9b SH |
222 | if (dual) { |
223 | clk_prepare_enable(ldb->clk[0]); | |
224 | clk_prepare_enable(ldb->clk[1]); | |
225 | } | |
226 | ||
227 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
228 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
229 | if (mux == 0 || ldb->lvds_mux) | |
230 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
231 | else if (mux == 1) | |
232 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
233 | } | |
234 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
235 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
236 | if (mux == 1 || ldb->lvds_mux) | |
237 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
238 | else if (mux == 0) | |
239 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
240 | } | |
241 | ||
242 | if (ldb->lvds_mux) { | |
243 | const struct bus_mux *lvds_mux = NULL; | |
244 | ||
245 | if (imx_ldb_ch == &ldb->channel[0]) | |
246 | lvds_mux = &ldb->lvds_mux[0]; | |
247 | else if (imx_ldb_ch == &ldb->channel[1]) | |
248 | lvds_mux = &ldb->lvds_mux[1]; | |
249 | ||
250 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
251 | mux << lvds_mux->shift); | |
252 | } | |
253 | ||
254 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
751e2676 PZ |
255 | |
256 | drm_panel_enable(imx_ldb_ch->panel); | |
ac4c1a9b SH |
257 | } |
258 | ||
259 | static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |
eb10d635 SL |
260 | struct drm_display_mode *orig_mode, |
261 | struct drm_display_mode *mode) | |
ac4c1a9b SH |
262 | { |
263 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
264 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
265 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
51dac94e PZ |
266 | unsigned long serial_clk; |
267 | unsigned long di_clk = mode->clock * 1000; | |
53141e42 | 268 | int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); |
ac4c1a9b SH |
269 | |
270 | if (mode->clock > 170000) { | |
271 | dev_warn(ldb->dev, | |
272 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
273 | } | |
274 | if (mode->clock > 85000 && !dual) { | |
275 | dev_warn(ldb->dev, | |
276 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
277 | } | |
278 | ||
51dac94e PZ |
279 | if (dual) { |
280 | serial_clk = 3500UL * mode->clock; | |
281 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
282 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
283 | } else { | |
284 | serial_clk = 7000UL * mode->clock; | |
285 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | |
286 | di_clk); | |
287 | } | |
288 | ||
ac4c1a9b SH |
289 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
290 | if (imx_ldb_ch == &ldb->channel[0]) { | |
291 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
292 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
293 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
294 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
295 | } | |
296 | if (imx_ldb_ch == &ldb->channel[1]) { | |
297 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
298 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
299 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
300 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
301 | } | |
302 | } | |
303 | ||
304 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
305 | { | |
306 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
307 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
3973aff0 | 308 | int mux, ret; |
ac4c1a9b SH |
309 | |
310 | /* | |
311 | * imx_ldb_encoder_disable is called by | |
312 | * drm_helper_disable_unused_functions without | |
313 | * the encoder being enabled before. | |
314 | */ | |
315 | if (imx_ldb_ch == &ldb->channel[0] && | |
316 | (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) | |
317 | return; | |
318 | else if (imx_ldb_ch == &ldb->channel[1] && | |
319 | (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) | |
320 | return; | |
321 | ||
751e2676 PZ |
322 | drm_panel_disable(imx_ldb_ch->panel); |
323 | ||
ac4c1a9b SH |
324 | if (imx_ldb_ch == &ldb->channel[0]) |
325 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
326 | else if (imx_ldb_ch == &ldb->channel[1]) | |
327 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
328 | ||
329 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
330 | ||
331 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
332 | clk_disable_unprepare(ldb->clk[0]); | |
333 | clk_disable_unprepare(ldb->clk[1]); | |
334 | } | |
751e2676 | 335 | |
3973aff0 PZ |
336 | if (ldb->lvds_mux) { |
337 | const struct bus_mux *lvds_mux = NULL; | |
338 | ||
339 | if (imx_ldb_ch == &ldb->channel[0]) | |
340 | lvds_mux = &ldb->lvds_mux[0]; | |
341 | else if (imx_ldb_ch == &ldb->channel[1]) | |
342 | lvds_mux = &ldb->lvds_mux[1]; | |
343 | ||
344 | regmap_read(ldb->regmap, lvds_mux->reg, &mux); | |
345 | mux &= lvds_mux->mask; | |
346 | mux >>= lvds_mux->shift; | |
347 | } else { | |
348 | mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; | |
349 | } | |
350 | ||
351 | /* set display clock mux back to original input clock */ | |
352 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); | |
353 | if (ret) | |
354 | dev_err(ldb->dev, | |
355 | "unable to set di%d parent clock to original parent\n", | |
356 | mux); | |
357 | ||
751e2676 | 358 | drm_panel_unprepare(imx_ldb_ch->panel); |
ac4c1a9b SH |
359 | } |
360 | ||
7ae847dd | 361 | static const struct drm_connector_funcs imx_ldb_connector_funcs = { |
ac4c1a9b SH |
362 | .dpms = drm_helper_connector_dpms, |
363 | .fill_modes = drm_helper_probe_single_connector_modes, | |
364 | .detect = imx_ldb_connector_detect, | |
1b3f7675 | 365 | .destroy = imx_drm_connector_destroy, |
255c35f8 LY |
366 | .reset = drm_atomic_helper_connector_reset, |
367 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
368 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
ac4c1a9b SH |
369 | }; |
370 | ||
7ae847dd | 371 | static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { |
ac4c1a9b SH |
372 | .get_modes = imx_ldb_connector_get_modes, |
373 | .best_encoder = imx_ldb_connector_best_encoder, | |
ac4c1a9b SH |
374 | }; |
375 | ||
7ae847dd | 376 | static const struct drm_encoder_funcs imx_ldb_encoder_funcs = { |
1b3f7675 | 377 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
378 | }; |
379 | ||
7ae847dd | 380 | static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { |
ac4c1a9b | 381 | .dpms = imx_ldb_encoder_dpms, |
ac4c1a9b SH |
382 | .prepare = imx_ldb_encoder_prepare, |
383 | .commit = imx_ldb_encoder_commit, | |
384 | .mode_set = imx_ldb_encoder_mode_set, | |
385 | .disable = imx_ldb_encoder_disable, | |
386 | }; | |
387 | ||
388 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
389 | { | |
390 | char clkname[16]; | |
391 | ||
98dd3b2a | 392 | snprintf(clkname, sizeof(clkname), "di%d", chno); |
ac4c1a9b SH |
393 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); |
394 | if (IS_ERR(ldb->clk[chno])) | |
395 | return PTR_ERR(ldb->clk[chno]); | |
396 | ||
98dd3b2a | 397 | snprintf(clkname, sizeof(clkname), "di%d_pll", chno); |
ac4c1a9b | 398 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); |
ac4c1a9b | 399 | |
1f933fa8 | 400 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
401 | } |
402 | ||
1b3f7675 RK |
403 | static int imx_ldb_register(struct drm_device *drm, |
404 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 405 | { |
ac4c1a9b | 406 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
1b3f7675 RK |
407 | int ret; |
408 | ||
409 | ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder, | |
410 | imx_ldb_ch->child); | |
411 | if (ret) | |
412 | return ret; | |
ac4c1a9b SH |
413 | |
414 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
415 | if (ret) | |
416 | return ret; | |
1b3f7675 | 417 | |
ac4c1a9b | 418 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 419 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
420 | if (ret) |
421 | return ret; | |
422 | } | |
423 | ||
ac4c1a9b SH |
424 | drm_encoder_helper_add(&imx_ldb_ch->encoder, |
425 | &imx_ldb_encoder_helper_funcs); | |
1b3f7675 | 426 | drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs, |
13a3d91f | 427 | DRM_MODE_ENCODER_LVDS, NULL); |
ac4c1a9b SH |
428 | |
429 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
430 | &imx_ldb_connector_helper_funcs); | |
1b3f7675 RK |
431 | drm_connector_init(drm, &imx_ldb_ch->connector, |
432 | &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); | |
ac4c1a9b | 433 | |
751e2676 PZ |
434 | if (imx_ldb_ch->panel) |
435 | drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector); | |
436 | ||
ac4c1a9b SH |
437 | drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, |
438 | &imx_ldb_ch->encoder); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | enum { | |
444 | LVDS_BIT_MAP_SPWG, | |
445 | LVDS_BIT_MAP_JEIDA | |
446 | }; | |
447 | ||
5e501ed7 PZ |
448 | struct imx_ldb_bit_mapping { |
449 | u32 bus_format; | |
450 | u32 datawidth; | |
451 | const char * const mapping; | |
ac4c1a9b SH |
452 | }; |
453 | ||
5e501ed7 PZ |
454 | static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { |
455 | { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, | |
456 | { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, | |
457 | { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, | |
458 | }; | |
459 | ||
460 | static u32 of_get_bus_format(struct device *dev, struct device_node *np) | |
ac4c1a9b SH |
461 | { |
462 | const char *bm; | |
5e501ed7 | 463 | u32 datawidth = 0; |
ac4c1a9b SH |
464 | int ret, i; |
465 | ||
466 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
467 | if (ret < 0) | |
468 | return ret; | |
469 | ||
5e501ed7 PZ |
470 | of_property_read_u32(np, "fsl,data-width", &datawidth); |
471 | ||
472 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { | |
473 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && | |
474 | datawidth == imx_ldb_bit_mappings[i].datawidth) | |
475 | return imx_ldb_bit_mappings[i].bus_format; | |
476 | } | |
477 | ||
478 | dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); | |
ac4c1a9b | 479 | |
5e501ed7 | 480 | return -ENOENT; |
ac4c1a9b SH |
481 | } |
482 | ||
483 | static struct bus_mux imx6q_lvds_mux[2] = { | |
484 | { | |
485 | .reg = IOMUXC_GPR3, | |
486 | .shift = 6, | |
487 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
488 | }, { | |
489 | .reg = IOMUXC_GPR3, | |
490 | .shift = 8, | |
491 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
492 | } | |
493 | }; | |
494 | ||
495 | /* | |
496 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
497 | * of_match_device will walk through this list and take the first entry | |
498 | * matching any of its compatible values. Therefore, the more generic | |
499 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
500 | */ | |
501 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
502 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
503 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
504 | { } | |
505 | }; | |
506 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
507 | ||
17b5001b | 508 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 509 | { |
1b3f7675 | 510 | struct drm_device *drm = data; |
17b5001b | 511 | struct device_node *np = dev->of_node; |
ac4c1a9b | 512 | const struct of_device_id *of_id = |
17b5001b | 513 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b SH |
514 | struct device_node *child; |
515 | const u8 *edidp; | |
516 | struct imx_ldb *imx_ldb; | |
ac4c1a9b SH |
517 | int dual; |
518 | int ret; | |
519 | int i; | |
520 | ||
17b5001b | 521 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
522 | if (!imx_ldb) |
523 | return -ENOMEM; | |
524 | ||
525 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
526 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 527 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
528 | return PTR_ERR(imx_ldb->regmap); |
529 | } | |
530 | ||
17b5001b | 531 | imx_ldb->dev = dev; |
ac4c1a9b SH |
532 | |
533 | if (of_id) | |
534 | imx_ldb->lvds_mux = of_id->data; | |
535 | ||
536 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
537 | if (dual) | |
538 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
539 | ||
540 | /* | |
4599934d | 541 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
542 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
543 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
544 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
545 | * Map them all to di0_sel...di3_sel. | |
546 | */ | |
547 | for (i = 0; i < 4; i++) { | |
548 | char clkname[16]; | |
549 | ||
550 | sprintf(clkname, "di%d_sel", i); | |
551 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
552 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
553 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
554 | imx_ldb->clk_sel[i] = NULL; | |
555 | break; | |
556 | } | |
3973aff0 PZ |
557 | |
558 | imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); | |
ac4c1a9b SH |
559 | } |
560 | if (i == 0) | |
561 | return ret; | |
562 | ||
563 | for_each_child_of_node(np, child) { | |
564 | struct imx_ldb_channel *channel; | |
a6d206e2 | 565 | struct device_node *ddc_node; |
620011e0 | 566 | struct device_node *ep; |
ac4c1a9b SH |
567 | |
568 | ret = of_property_read_u32(child, "reg", &i); | |
569 | if (ret || i < 0 || i > 1) | |
570 | return -EINVAL; | |
571 | ||
572 | if (dual && i > 0) { | |
17b5001b | 573 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
574 | continue; |
575 | } | |
576 | ||
577 | if (!of_device_is_available(child)) | |
578 | continue; | |
579 | ||
580 | channel = &imx_ldb->channel[i]; | |
581 | channel->ldb = imx_ldb; | |
582 | channel->chno = i; | |
1b3f7675 | 583 | channel->child = child; |
ac4c1a9b | 584 | |
751e2676 PZ |
585 | /* |
586 | * The output port is port@4 with an external 4-port mux or | |
587 | * port@2 with the internal 2-port mux. | |
588 | */ | |
620011e0 PZ |
589 | ep = of_graph_get_endpoint_by_regs(child, |
590 | imx_ldb->lvds_mux ? 4 : 2, | |
591 | -1); | |
592 | if (ep) { | |
593 | struct device_node *remote; | |
594 | ||
595 | remote = of_graph_get_remote_port_parent(ep); | |
596 | of_node_put(ep); | |
597 | if (remote) | |
598 | channel->panel = of_drm_find_panel(remote); | |
599 | else | |
600 | return -EPROBE_DEFER; | |
601 | of_node_put(remote); | |
602 | if (!channel->panel) { | |
603 | dev_err(dev, "panel not found: %s\n", | |
604 | remote->full_name); | |
605 | return -EPROBE_DEFER; | |
751e2676 PZ |
606 | } |
607 | } | |
608 | ||
a6d206e2 SL |
609 | ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0); |
610 | if (ddc_node) { | |
611 | channel->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
612 | of_node_put(ddc_node); | |
613 | if (!channel->ddc) { | |
614 | dev_warn(dev, "failed to get ddc i2c adapter\n"); | |
615 | return -EPROBE_DEFER; | |
616 | } | |
617 | } | |
618 | ||
619 | if (!channel->ddc) { | |
620 | /* if no DDC available, fallback to hardcoded EDID */ | |
621 | dev_dbg(dev, "no ddc available\n"); | |
622 | ||
623 | edidp = of_get_property(child, "edid", | |
624 | &channel->edid_len); | |
625 | if (edidp) { | |
626 | channel->edid = kmemdup(edidp, | |
627 | channel->edid_len, | |
628 | GFP_KERNEL); | |
629 | } else if (!channel->panel) { | |
630 | /* fallback to display-timings node */ | |
631 | ret = of_get_drm_display_mode(child, | |
632 | &channel->mode, | |
c82b4d73 | 633 | OF_USE_NATIVE_MODE); |
a6d206e2 SL |
634 | if (!ret) |
635 | channel->mode_valid = 1; | |
636 | } | |
ac4c1a9b SH |
637 | } |
638 | ||
5e501ed7 PZ |
639 | channel->bus_format = of_get_bus_format(dev, child); |
640 | if (channel->bus_format == -EINVAL) { | |
641 | /* | |
642 | * If no bus format was specified in the device tree, | |
643 | * we can still get it from the connected panel later. | |
644 | */ | |
645 | if (channel->panel && channel->panel->funcs && | |
646 | channel->panel->funcs->get_modes) | |
647 | channel->bus_format = 0; | |
648 | } | |
649 | if (channel->bus_format < 0) { | |
650 | dev_err(dev, "could not determine data mapping: %d\n", | |
651 | channel->bus_format); | |
652 | return channel->bus_format; | |
ac4c1a9b SH |
653 | } |
654 | ||
1b3f7675 | 655 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
656 | if (ret) |
657 | return ret; | |
ac4c1a9b SH |
658 | } |
659 | ||
17b5001b | 660 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
661 | |
662 | return 0; | |
663 | } | |
664 | ||
17b5001b RK |
665 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
666 | void *data) | |
ac4c1a9b | 667 | { |
17b5001b | 668 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
669 | int i; |
670 | ||
671 | for (i = 0; i < 2; i++) { | |
672 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 673 | |
d9fdb9fb RK |
674 | if (!channel->connector.funcs) |
675 | continue; | |
676 | ||
1b3f7675 RK |
677 | channel->connector.funcs->destroy(&channel->connector); |
678 | channel->encoder.funcs->destroy(&channel->encoder); | |
f4876ffe PS |
679 | |
680 | kfree(channel->edid); | |
a6d206e2 | 681 | i2c_put_adapter(channel->ddc); |
ac4c1a9b | 682 | } |
17b5001b | 683 | } |
ac4c1a9b | 684 | |
17b5001b RK |
685 | static const struct component_ops imx_ldb_ops = { |
686 | .bind = imx_ldb_bind, | |
687 | .unbind = imx_ldb_unbind, | |
688 | }; | |
689 | ||
690 | static int imx_ldb_probe(struct platform_device *pdev) | |
691 | { | |
692 | return component_add(&pdev->dev, &imx_ldb_ops); | |
693 | } | |
694 | ||
695 | static int imx_ldb_remove(struct platform_device *pdev) | |
696 | { | |
697 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
698 | return 0; |
699 | } | |
700 | ||
701 | static struct platform_driver imx_ldb_driver = { | |
702 | .probe = imx_ldb_probe, | |
703 | .remove = imx_ldb_remove, | |
704 | .driver = { | |
705 | .of_match_table = imx_ldb_dt_ids, | |
706 | .name = DRIVER_NAME, | |
ac4c1a9b SH |
707 | }, |
708 | }; | |
709 | ||
710 | module_platform_driver(imx_ldb_driver); | |
711 | ||
712 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
713 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
714 | MODULE_LICENSE("GPL"); | |
bc627387 | 715 | MODULE_ALIAS("platform:" DRIVER_NAME); |