Merge tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux into...
[deliverable/linux.git] / drivers / gpu / drm / imx / imx-ldb.c
CommitLineData
ac4c1a9b
SH
1/*
2 * i.MX drm driver - LVDS display bridge
3 *
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
ac4c1a9b
SH
14 */
15
16#include <linux/module.h>
17#include <linux/clk.h>
17b5001b 18#include <linux/component.h>
ac4c1a9b 19#include <drm/drmP.h>
49f98bc4 20#include <drm/drm_atomic.h>
255c35f8 21#include <drm/drm_atomic_helper.h>
ac4c1a9b
SH
22#include <drm/drm_fb_helper.h>
23#include <drm/drm_crtc_helper.h>
53141e42 24#include <drm/drm_of.h>
751e2676 25#include <drm/drm_panel.h>
ac4c1a9b
SH
26#include <linux/mfd/syscon.h>
27#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
ac4c1a9b 28#include <linux/of_device.h>
751e2676 29#include <linux/of_graph.h>
c82b4d73 30#include <video/of_display_timing.h>
ac4c1a9b
SH
31#include <video/of_videomode.h>
32#include <linux/regmap.h>
33#include <linux/videodev2.h>
34
35#include "imx-drm.h"
36
37#define DRIVER_NAME "imx-ldb"
38
39#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
40#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
41#define LDB_CH0_MODE_EN_MASK (3 << 0)
42#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
43#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
44#define LDB_CH1_MODE_EN_MASK (3 << 2)
45#define LDB_SPLIT_MODE_EN (1 << 4)
46#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
47#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
48#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
49#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
50#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
51#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
52#define LDB_BGREF_RMODE_INT (1 << 15)
53
ac4c1a9b
SH
54struct imx_ldb;
55
56struct imx_ldb_channel {
57 struct imx_ldb *ldb;
58 struct drm_connector connector;
49f98bc4 59 struct drm_encoder encoder;
751e2676 60 struct drm_panel *panel;
1b3f7675 61 struct device_node *child;
a6d206e2 62 struct i2c_adapter *ddc;
ac4c1a9b
SH
63 int chno;
64 void *edid;
65 int edid_len;
66 struct drm_display_mode mode;
67 int mode_valid;
49f98bc4 68 u32 bus_format;
ac4c1a9b
SH
69};
70
3df07390
PZ
71static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
72{
73 return container_of(c, struct imx_ldb_channel, connector);
74}
75
49f98bc4
PZ
76static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
77{
78 return container_of(e, struct imx_ldb_channel, encoder);
79}
80
ac4c1a9b
SH
81struct bus_mux {
82 int reg;
83 int shift;
84 int mask;
85};
86
87struct imx_ldb {
88 struct regmap *regmap;
89 struct device *dev;
90 struct imx_ldb_channel channel[2];
91 struct clk *clk[2]; /* our own clock */
92 struct clk *clk_sel[4]; /* parent of display clock */
3973aff0 93 struct clk *clk_parent[4]; /* original parent of clk_sel */
ac4c1a9b
SH
94 struct clk *clk_pll[2]; /* upstream clock we can adjust */
95 u32 ldb_ctrl;
96 const struct bus_mux *lvds_mux;
97};
98
99static enum drm_connector_status imx_ldb_connector_detect(
100 struct drm_connector *connector, bool force)
101{
102 return connector_status_connected;
103}
104
49f98bc4
PZ
105static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
106 u32 bus_format)
032003c5
LY
107{
108 struct imx_ldb *ldb = imx_ldb_ch->ldb;
109 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
110
111 switch (bus_format) {
112 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
032003c5
LY
113 break;
114 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
032003c5
LY
115 if (imx_ldb_ch->chno == 0 || dual)
116 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
117 if (imx_ldb_ch->chno == 1 || dual)
118 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
119 break;
120 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
032003c5
LY
121 if (imx_ldb_ch->chno == 0 || dual)
122 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
123 LDB_BIT_MAP_CH0_JEIDA;
124 if (imx_ldb_ch->chno == 1 || dual)
125 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
126 LDB_BIT_MAP_CH1_JEIDA;
127 break;
128 }
129}
130
ac4c1a9b
SH
131static int imx_ldb_connector_get_modes(struct drm_connector *connector)
132{
133 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
134 int num_modes = 0;
135
751e2676
PZ
136 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
137 imx_ldb_ch->panel->funcs->get_modes) {
138 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
139 if (num_modes > 0)
140 return num_modes;
141 }
142
a6d206e2
SL
143 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
144 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
145
ac4c1a9b
SH
146 if (imx_ldb_ch->edid) {
147 drm_mode_connector_update_edid_property(connector,
148 imx_ldb_ch->edid);
149 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
150 }
151
152 if (imx_ldb_ch->mode_valid) {
153 struct drm_display_mode *mode;
154
155 mode = drm_mode_create(connector->dev);
9f9b036f
FE
156 if (!mode)
157 return -EINVAL;
ac4c1a9b
SH
158 drm_mode_copy(mode, &imx_ldb_ch->mode);
159 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
160 drm_mode_probed_add(connector, mode);
161 num_modes++;
162 }
163
164 return num_modes;
165}
166
ac4c1a9b
SH
167static struct drm_encoder *imx_ldb_connector_best_encoder(
168 struct drm_connector *connector)
169{
170 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
171
49f98bc4 172 return &imx_ldb_ch->encoder;
ac4c1a9b
SH
173}
174
ac4c1a9b
SH
175static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
176 unsigned long serial_clk, unsigned long di_clk)
177{
178 int ret;
179
180 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
181 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
182 clk_set_rate(ldb->clk_pll[chno], serial_clk);
183
184 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
185 clk_get_rate(ldb->clk_pll[chno]));
186
187 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
188 clk_get_rate(ldb->clk[chno]),
189 (long int)di_clk);
190 clk_set_rate(ldb->clk[chno], di_clk);
191
192 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
193 clk_get_rate(ldb->clk[chno]));
194
195 /* set display clock mux to LDB input clock */
196 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
49f4a9c8 197 if (ret)
e5e1b166
AO
198 dev_err(ldb->dev,
199 "unable to set di%d parent clock to ldb_di%d\n", mux,
200 chno);
ac4c1a9b
SH
201}
202
f6e396e5 203static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
ac4c1a9b 204{
49f98bc4 205 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
ac4c1a9b
SH
206 struct imx_ldb *ldb = imx_ldb_ch->ldb;
207 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
53141e42 208 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
ac4c1a9b 209
751e2676
PZ
210 drm_panel_prepare(imx_ldb_ch->panel);
211
ac4c1a9b 212 if (dual) {
f6e396e5
LY
213 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
214 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
215
ac4c1a9b
SH
216 clk_prepare_enable(ldb->clk[0]);
217 clk_prepare_enable(ldb->clk[1]);
f6e396e5
LY
218 } else {
219 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
ac4c1a9b
SH
220 }
221
222 if (imx_ldb_ch == &ldb->channel[0] || dual) {
223 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
224 if (mux == 0 || ldb->lvds_mux)
225 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
226 else if (mux == 1)
227 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
228 }
229 if (imx_ldb_ch == &ldb->channel[1] || dual) {
230 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
231 if (mux == 1 || ldb->lvds_mux)
232 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
233 else if (mux == 0)
234 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
235 }
236
237 if (ldb->lvds_mux) {
238 const struct bus_mux *lvds_mux = NULL;
239
240 if (imx_ldb_ch == &ldb->channel[0])
241 lvds_mux = &ldb->lvds_mux[0];
242 else if (imx_ldb_ch == &ldb->channel[1])
243 lvds_mux = &ldb->lvds_mux[1];
244
245 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
246 mux << lvds_mux->shift);
247 }
248
249 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
751e2676
PZ
250
251 drm_panel_enable(imx_ldb_ch->panel);
ac4c1a9b
SH
252}
253
254static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
eb10d635
SL
255 struct drm_display_mode *orig_mode,
256 struct drm_display_mode *mode)
ac4c1a9b 257{
49f98bc4 258 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
ac4c1a9b
SH
259 struct imx_ldb *ldb = imx_ldb_ch->ldb;
260 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
51dac94e
PZ
261 unsigned long serial_clk;
262 unsigned long di_clk = mode->clock * 1000;
53141e42 263 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
49f98bc4 264 u32 bus_format = imx_ldb_ch->bus_format;
ac4c1a9b
SH
265
266 if (mode->clock > 170000) {
267 dev_warn(ldb->dev,
268 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
269 }
270 if (mode->clock > 85000 && !dual) {
271 dev_warn(ldb->dev,
272 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
273 }
274
51dac94e
PZ
275 if (dual) {
276 serial_clk = 3500UL * mode->clock;
277 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
278 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
279 } else {
280 serial_clk = 7000UL * mode->clock;
281 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
282 di_clk);
283 }
284
ac4c1a9b 285 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
49f98bc4 286 if (imx_ldb_ch == &ldb->channel[0] || dual) {
ac4c1a9b
SH
287 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
288 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
289 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
290 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
291 }
49f98bc4 292 if (imx_ldb_ch == &ldb->channel[1] || dual) {
ac4c1a9b
SH
293 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
294 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
295 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
296 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
297 }
49f98bc4
PZ
298
299 if (!bus_format) {
300 struct drm_connector_state *conn_state;
301 struct drm_connector *connector;
302 int i;
303
304 for_each_connector_in_state(encoder->crtc->state->state,
305 connector, conn_state, i) {
306 struct drm_display_info *di = &connector->display_info;
307
308 if (conn_state->crtc == encoder->crtc &&
309 di->num_bus_formats) {
310 bus_format = di->bus_formats[0];
311 break;
312 }
313 }
314 }
315 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
ac4c1a9b
SH
316}
317
318static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
319{
49f98bc4 320 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
ac4c1a9b 321 struct imx_ldb *ldb = imx_ldb_ch->ldb;
3973aff0 322 int mux, ret;
ac4c1a9b
SH
323
324 /*
325 * imx_ldb_encoder_disable is called by
326 * drm_helper_disable_unused_functions without
327 * the encoder being enabled before.
328 */
329 if (imx_ldb_ch == &ldb->channel[0] &&
330 (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
331 return;
332 else if (imx_ldb_ch == &ldb->channel[1] &&
333 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
334 return;
335
751e2676
PZ
336 drm_panel_disable(imx_ldb_ch->panel);
337
ac4c1a9b
SH
338 if (imx_ldb_ch == &ldb->channel[0])
339 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
340 else if (imx_ldb_ch == &ldb->channel[1])
341 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
342
343 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
344
345 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
346 clk_disable_unprepare(ldb->clk[0]);
347 clk_disable_unprepare(ldb->clk[1]);
348 }
751e2676 349
3973aff0
PZ
350 if (ldb->lvds_mux) {
351 const struct bus_mux *lvds_mux = NULL;
352
353 if (imx_ldb_ch == &ldb->channel[0])
354 lvds_mux = &ldb->lvds_mux[0];
355 else if (imx_ldb_ch == &ldb->channel[1])
356 lvds_mux = &ldb->lvds_mux[1];
357
358 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
359 mux &= lvds_mux->mask;
360 mux >>= lvds_mux->shift;
361 } else {
362 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
363 }
364
365 /* set display clock mux back to original input clock */
366 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
367 if (ret)
368 dev_err(ldb->dev,
369 "unable to set di%d parent clock to original parent\n",
370 mux);
371
751e2676 372 drm_panel_unprepare(imx_ldb_ch->panel);
ac4c1a9b
SH
373}
374
49f98bc4
PZ
375static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
376 struct drm_crtc_state *crtc_state,
377 struct drm_connector_state *conn_state)
378{
379 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
380 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
381 struct drm_display_info *di = &conn_state->connector->display_info;
382 u32 bus_format = imx_ldb_ch->bus_format;
383
384 /* Bus format description in DT overrides connector display info. */
385 if (!bus_format && di->num_bus_formats)
386 bus_format = di->bus_formats[0];
387 switch (bus_format) {
388 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
389 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
390 break;
391 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
392 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
393 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
394 break;
395 default:
396 return -EINVAL;
397 }
398
399 imx_crtc_state->di_hsync_pin = 2;
400 imx_crtc_state->di_vsync_pin = 3;
401
402 return 0;
403}
404
405
7ae847dd 406static const struct drm_connector_funcs imx_ldb_connector_funcs = {
f6e396e5 407 .dpms = drm_atomic_helper_connector_dpms,
ac4c1a9b
SH
408 .fill_modes = drm_helper_probe_single_connector_modes,
409 .detect = imx_ldb_connector_detect,
1b3f7675 410 .destroy = imx_drm_connector_destroy,
255c35f8
LY
411 .reset = drm_atomic_helper_connector_reset,
412 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
413 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
ac4c1a9b
SH
414};
415
7ae847dd 416static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
ac4c1a9b
SH
417 .get_modes = imx_ldb_connector_get_modes,
418 .best_encoder = imx_ldb_connector_best_encoder,
ac4c1a9b
SH
419};
420
7ae847dd 421static const struct drm_encoder_funcs imx_ldb_encoder_funcs = {
1b3f7675 422 .destroy = imx_drm_encoder_destroy,
ac4c1a9b
SH
423};
424
7ae847dd 425static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
ac4c1a9b 426 .mode_set = imx_ldb_encoder_mode_set,
f6e396e5 427 .enable = imx_ldb_encoder_enable,
ac4c1a9b 428 .disable = imx_ldb_encoder_disable,
49f98bc4 429 .atomic_check = imx_ldb_encoder_atomic_check,
ac4c1a9b
SH
430};
431
432static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
433{
434 char clkname[16];
435
98dd3b2a 436 snprintf(clkname, sizeof(clkname), "di%d", chno);
ac4c1a9b
SH
437 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
438 if (IS_ERR(ldb->clk[chno]))
439 return PTR_ERR(ldb->clk[chno]);
440
98dd3b2a 441 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
ac4c1a9b 442 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
ac4c1a9b 443
1f933fa8 444 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
ac4c1a9b
SH
445}
446
1b3f7675
RK
447static int imx_ldb_register(struct drm_device *drm,
448 struct imx_ldb_channel *imx_ldb_ch)
ac4c1a9b 449{
ac4c1a9b 450 struct imx_ldb *ldb = imx_ldb_ch->ldb;
49f98bc4 451 struct drm_encoder *encoder = &imx_ldb_ch->encoder;
1b3f7675
RK
452 int ret;
453
49f98bc4 454 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
1b3f7675
RK
455 if (ret)
456 return ret;
ac4c1a9b
SH
457
458 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
459 if (ret)
460 return ret;
1b3f7675 461
ac4c1a9b 462 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
1b3f7675 463 ret = imx_ldb_get_clk(ldb, 1);
ac4c1a9b
SH
464 if (ret)
465 return ret;
466 }
467
49f98bc4
PZ
468 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
469 drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs,
470 DRM_MODE_ENCODER_LVDS, NULL);
ac4c1a9b
SH
471
472 drm_connector_helper_add(&imx_ldb_ch->connector,
473 &imx_ldb_connector_helper_funcs);
1b3f7675
RK
474 drm_connector_init(drm, &imx_ldb_ch->connector,
475 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
ac4c1a9b 476
7075ba79
LS
477 if (imx_ldb_ch->panel) {
478 ret = drm_panel_attach(imx_ldb_ch->panel,
479 &imx_ldb_ch->connector);
480 if (ret)
481 return ret;
482 }
751e2676 483
49f98bc4 484 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
ac4c1a9b
SH
485
486 return 0;
487}
488
489enum {
490 LVDS_BIT_MAP_SPWG,
491 LVDS_BIT_MAP_JEIDA
492};
493
5e501ed7
PZ
494struct imx_ldb_bit_mapping {
495 u32 bus_format;
496 u32 datawidth;
497 const char * const mapping;
ac4c1a9b
SH
498};
499
5e501ed7
PZ
500static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
501 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
502 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
503 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
504};
505
506static u32 of_get_bus_format(struct device *dev, struct device_node *np)
ac4c1a9b
SH
507{
508 const char *bm;
5e501ed7 509 u32 datawidth = 0;
ac4c1a9b
SH
510 int ret, i;
511
512 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
513 if (ret < 0)
514 return ret;
515
5e501ed7
PZ
516 of_property_read_u32(np, "fsl,data-width", &datawidth);
517
518 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
519 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
520 datawidth == imx_ldb_bit_mappings[i].datawidth)
521 return imx_ldb_bit_mappings[i].bus_format;
522 }
523
524 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
ac4c1a9b 525
5e501ed7 526 return -ENOENT;
ac4c1a9b
SH
527}
528
529static struct bus_mux imx6q_lvds_mux[2] = {
530 {
531 .reg = IOMUXC_GPR3,
532 .shift = 6,
533 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
534 }, {
535 .reg = IOMUXC_GPR3,
536 .shift = 8,
537 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
538 }
539};
540
541/*
542 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
543 * of_match_device will walk through this list and take the first entry
544 * matching any of its compatible values. Therefore, the more generic
545 * entries (in this case fsl,imx53-ldb) need to be ordered last.
546 */
547static const struct of_device_id imx_ldb_dt_ids[] = {
548 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
549 { .compatible = "fsl,imx53-ldb", .data = NULL, },
550 { }
551};
552MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
553
17b5001b 554static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
ac4c1a9b 555{
1b3f7675 556 struct drm_device *drm = data;
17b5001b 557 struct device_node *np = dev->of_node;
ac4c1a9b 558 const struct of_device_id *of_id =
17b5001b 559 of_match_device(imx_ldb_dt_ids, dev);
ac4c1a9b
SH
560 struct device_node *child;
561 const u8 *edidp;
562 struct imx_ldb *imx_ldb;
ac4c1a9b
SH
563 int dual;
564 int ret;
565 int i;
566
17b5001b 567 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
ac4c1a9b
SH
568 if (!imx_ldb)
569 return -ENOMEM;
570
571 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
572 if (IS_ERR(imx_ldb->regmap)) {
17b5001b 573 dev_err(dev, "failed to get parent regmap\n");
ac4c1a9b
SH
574 return PTR_ERR(imx_ldb->regmap);
575 }
576
17b5001b 577 imx_ldb->dev = dev;
ac4c1a9b
SH
578
579 if (of_id)
580 imx_ldb->lvds_mux = of_id->data;
581
582 dual = of_property_read_bool(np, "fsl,dual-channel");
583 if (dual)
584 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
585
586 /*
4599934d 587 * There are three different possible clock mux configurations:
ac4c1a9b
SH
588 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
589 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
590 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
591 * Map them all to di0_sel...di3_sel.
592 */
593 for (i = 0; i < 4; i++) {
594 char clkname[16];
595
596 sprintf(clkname, "di%d_sel", i);
597 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
598 if (IS_ERR(imx_ldb->clk_sel[i])) {
599 ret = PTR_ERR(imx_ldb->clk_sel[i]);
600 imx_ldb->clk_sel[i] = NULL;
601 break;
602 }
3973aff0
PZ
603
604 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
ac4c1a9b
SH
605 }
606 if (i == 0)
607 return ret;
608
609 for_each_child_of_node(np, child) {
610 struct imx_ldb_channel *channel;
a6d206e2 611 struct device_node *ddc_node;
620011e0 612 struct device_node *ep;
032003c5 613 int bus_format;
ac4c1a9b
SH
614
615 ret = of_property_read_u32(child, "reg", &i);
616 if (ret || i < 0 || i > 1)
617 return -EINVAL;
618
619 if (dual && i > 0) {
17b5001b 620 dev_warn(dev, "dual-channel mode, ignoring second output\n");
ac4c1a9b
SH
621 continue;
622 }
623
624 if (!of_device_is_available(child))
625 continue;
626
627 channel = &imx_ldb->channel[i];
628 channel->ldb = imx_ldb;
629 channel->chno = i;
1b3f7675 630 channel->child = child;
ac4c1a9b 631
751e2676
PZ
632 /*
633 * The output port is port@4 with an external 4-port mux or
634 * port@2 with the internal 2-port mux.
635 */
620011e0
PZ
636 ep = of_graph_get_endpoint_by_regs(child,
637 imx_ldb->lvds_mux ? 4 : 2,
638 -1);
639 if (ep) {
640 struct device_node *remote;
641
642 remote = of_graph_get_remote_port_parent(ep);
643 of_node_put(ep);
644 if (remote)
645 channel->panel = of_drm_find_panel(remote);
646 else
647 return -EPROBE_DEFER;
648 of_node_put(remote);
649 if (!channel->panel) {
650 dev_err(dev, "panel not found: %s\n",
651 remote->full_name);
652 return -EPROBE_DEFER;
751e2676
PZ
653 }
654 }
655
a6d206e2
SL
656 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
657 if (ddc_node) {
658 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
659 of_node_put(ddc_node);
660 if (!channel->ddc) {
661 dev_warn(dev, "failed to get ddc i2c adapter\n");
662 return -EPROBE_DEFER;
663 }
664 }
665
666 if (!channel->ddc) {
667 /* if no DDC available, fallback to hardcoded EDID */
668 dev_dbg(dev, "no ddc available\n");
669
670 edidp = of_get_property(child, "edid",
671 &channel->edid_len);
672 if (edidp) {
673 channel->edid = kmemdup(edidp,
674 channel->edid_len,
675 GFP_KERNEL);
676 } else if (!channel->panel) {
677 /* fallback to display-timings node */
678 ret = of_get_drm_display_mode(child,
679 &channel->mode,
c82b4d73 680 OF_USE_NATIVE_MODE);
a6d206e2
SL
681 if (!ret)
682 channel->mode_valid = 1;
683 }
ac4c1a9b
SH
684 }
685
032003c5
LY
686 bus_format = of_get_bus_format(dev, child);
687 if (bus_format == -EINVAL) {
5e501ed7
PZ
688 /*
689 * If no bus format was specified in the device tree,
690 * we can still get it from the connected panel later.
691 */
692 if (channel->panel && channel->panel->funcs &&
693 channel->panel->funcs->get_modes)
032003c5 694 bus_format = 0;
5e501ed7 695 }
032003c5 696 if (bus_format < 0) {
5e501ed7 697 dev_err(dev, "could not determine data mapping: %d\n",
032003c5
LY
698 bus_format);
699 return bus_format;
ac4c1a9b 700 }
49f98bc4 701 channel->bus_format = bus_format;
ac4c1a9b 702
1b3f7675 703 ret = imx_ldb_register(drm, channel);
ac4c1a9b
SH
704 if (ret)
705 return ret;
ac4c1a9b
SH
706 }
707
17b5001b 708 dev_set_drvdata(dev, imx_ldb);
ac4c1a9b
SH
709
710 return 0;
711}
712
17b5001b
RK
713static void imx_ldb_unbind(struct device *dev, struct device *master,
714 void *data)
ac4c1a9b 715{
17b5001b 716 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
ac4c1a9b
SH
717 int i;
718
719 for (i = 0; i < 2; i++) {
720 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
ac4c1a9b 721
d9fdb9fb
RK
722 if (!channel->connector.funcs)
723 continue;
724
1b3f7675 725 channel->connector.funcs->destroy(&channel->connector);
49f98bc4 726 channel->encoder.funcs->destroy(&channel->encoder);
f4876ffe
PS
727
728 kfree(channel->edid);
a6d206e2 729 i2c_put_adapter(channel->ddc);
ac4c1a9b 730 }
17b5001b 731}
ac4c1a9b 732
17b5001b
RK
733static const struct component_ops imx_ldb_ops = {
734 .bind = imx_ldb_bind,
735 .unbind = imx_ldb_unbind,
736};
737
738static int imx_ldb_probe(struct platform_device *pdev)
739{
740 return component_add(&pdev->dev, &imx_ldb_ops);
741}
742
743static int imx_ldb_remove(struct platform_device *pdev)
744{
745 component_del(&pdev->dev, &imx_ldb_ops);
ac4c1a9b
SH
746 return 0;
747}
748
749static struct platform_driver imx_ldb_driver = {
750 .probe = imx_ldb_probe,
751 .remove = imx_ldb_remove,
752 .driver = {
753 .of_match_table = imx_ldb_dt_ids,
754 .name = DRIVER_NAME,
ac4c1a9b
SH
755 },
756};
757
758module_platform_driver(imx_ldb_driver);
759
760MODULE_DESCRIPTION("i.MX LVDS driver");
761MODULE_AUTHOR("Sascha Hauer, Pengutronix");
762MODULE_LICENSE("GPL");
bc627387 763MODULE_ALIAS("platform:" DRIVER_NAME);
This page took 0.277306 seconds and 5 git commands to generate.