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fcbc51e5 PZ |
1 | /* |
2 | * i.MX drm driver - Television Encoder (TVEv2) | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
fcbc51e5 PZ |
14 | */ |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/clk-provider.h> | |
17b5001b | 18 | #include <linux/component.h> |
fcbc51e5 | 19 | #include <linux/module.h> |
687b81d0 | 20 | #include <linux/i2c.h> |
fcbc51e5 PZ |
21 | #include <linux/regmap.h> |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/videodev2.h> | |
25 | #include <drm/drmP.h> | |
26 | #include <drm/drm_fb_helper.h> | |
27 | #include <drm/drm_crtc_helper.h> | |
39b9004d | 28 | #include <video/imx-ipu-v3.h> |
fcbc51e5 PZ |
29 | |
30 | #include "imx-drm.h" | |
31 | ||
32 | #define TVE_COM_CONF_REG 0x00 | |
33 | #define TVE_TVDAC0_CONT_REG 0x28 | |
34 | #define TVE_TVDAC1_CONT_REG 0x2c | |
35 | #define TVE_TVDAC2_CONT_REG 0x30 | |
36 | #define TVE_CD_CONT_REG 0x34 | |
37 | #define TVE_INT_CONT_REG 0x64 | |
38 | #define TVE_STAT_REG 0x68 | |
39 | #define TVE_TST_MODE_REG 0x6c | |
40 | #define TVE_MV_CONT_REG 0xdc | |
41 | ||
42 | /* TVE_COM_CONF_REG */ | |
43 | #define TVE_SYNC_CH_2_EN BIT(22) | |
44 | #define TVE_SYNC_CH_1_EN BIT(21) | |
45 | #define TVE_SYNC_CH_0_EN BIT(20) | |
46 | #define TVE_TV_OUT_MODE_MASK (0x7 << 12) | |
47 | #define TVE_TV_OUT_DISABLE (0x0 << 12) | |
48 | #define TVE_TV_OUT_CVBS_0 (0x1 << 12) | |
49 | #define TVE_TV_OUT_CVBS_2 (0x2 << 12) | |
50 | #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) | |
51 | #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) | |
52 | #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) | |
53 | #define TVE_TV_OUT_YPBPR (0x6 << 12) | |
54 | #define TVE_TV_OUT_RGB (0x7 << 12) | |
55 | #define TVE_TV_STAND_MASK (0xf << 8) | |
56 | #define TVE_TV_STAND_HD_1080P30 (0xc << 8) | |
57 | #define TVE_P2I_CONV_EN BIT(7) | |
58 | #define TVE_INP_VIDEO_FORM BIT(6) | |
59 | #define TVE_INP_YCBCR_422 (0x0 << 6) | |
60 | #define TVE_INP_YCBCR_444 (0x1 << 6) | |
61 | #define TVE_DATA_SOURCE_MASK (0x3 << 4) | |
62 | #define TVE_DATA_SOURCE_BUS1 (0x0 << 4) | |
63 | #define TVE_DATA_SOURCE_BUS2 (0x1 << 4) | |
64 | #define TVE_DATA_SOURCE_EXT (0x2 << 4) | |
65 | #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) | |
66 | #define TVE_IPU_CLK_EN_OFS 3 | |
67 | #define TVE_IPU_CLK_EN BIT(3) | |
68 | #define TVE_DAC_SAMP_RATE_OFS 1 | |
69 | #define TVE_DAC_SAMP_RATE_WIDTH 2 | |
70 | #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) | |
71 | #define TVE_DAC_FULL_RATE (0x0 << 1) | |
72 | #define TVE_DAC_DIV2_RATE (0x1 << 1) | |
73 | #define TVE_DAC_DIV4_RATE (0x2 << 1) | |
74 | #define TVE_EN BIT(0) | |
75 | ||
76 | /* TVE_TVDACx_CONT_REG */ | |
77 | #define TVE_TVDAC_GAIN_MASK (0x3f << 0) | |
78 | ||
79 | /* TVE_CD_CONT_REG */ | |
80 | #define TVE_CD_CH_2_SM_EN BIT(22) | |
81 | #define TVE_CD_CH_1_SM_EN BIT(21) | |
82 | #define TVE_CD_CH_0_SM_EN BIT(20) | |
83 | #define TVE_CD_CH_2_LM_EN BIT(18) | |
84 | #define TVE_CD_CH_1_LM_EN BIT(17) | |
85 | #define TVE_CD_CH_0_LM_EN BIT(16) | |
86 | #define TVE_CD_CH_2_REF_LVL BIT(10) | |
87 | #define TVE_CD_CH_1_REF_LVL BIT(9) | |
88 | #define TVE_CD_CH_0_REF_LVL BIT(8) | |
89 | #define TVE_CD_EN BIT(0) | |
90 | ||
91 | /* TVE_INT_CONT_REG */ | |
92 | #define TVE_FRAME_END_IEN BIT(13) | |
93 | #define TVE_CD_MON_END_IEN BIT(2) | |
94 | #define TVE_CD_SM_IEN BIT(1) | |
95 | #define TVE_CD_LM_IEN BIT(0) | |
96 | ||
97 | /* TVE_TST_MODE_REG */ | |
98 | #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) | |
99 | ||
100 | #define con_to_tve(x) container_of(x, struct imx_tve, connector) | |
101 | #define enc_to_tve(x) container_of(x, struct imx_tve, encoder) | |
102 | ||
103 | enum { | |
104 | TVE_MODE_TVOUT, | |
105 | TVE_MODE_VGA, | |
106 | }; | |
107 | ||
108 | struct imx_tve { | |
109 | struct drm_connector connector; | |
fcbc51e5 | 110 | struct drm_encoder encoder; |
fcbc51e5 | 111 | struct device *dev; |
fcbc51e5 PZ |
112 | spinlock_t lock; /* register lock */ |
113 | bool enabled; | |
114 | int mode; | |
115 | ||
116 | struct regmap *regmap; | |
117 | struct regulator *dac_reg; | |
118 | struct i2c_adapter *ddc; | |
119 | struct clk *clk; | |
120 | struct clk *di_sel_clk; | |
121 | struct clk_hw clk_hw_di; | |
122 | struct clk *di_clk; | |
123 | int vsync_pin; | |
124 | int hsync_pin; | |
125 | }; | |
126 | ||
127 | static void tve_lock(void *__tve) | |
5d78bf80 | 128 | __acquires(&tve->lock) |
fcbc51e5 PZ |
129 | { |
130 | struct imx_tve *tve = __tve; | |
63bc5164 | 131 | |
fcbc51e5 PZ |
132 | spin_lock(&tve->lock); |
133 | } | |
134 | ||
135 | static void tve_unlock(void *__tve) | |
5d78bf80 | 136 | __releases(&tve->lock) |
fcbc51e5 PZ |
137 | { |
138 | struct imx_tve *tve = __tve; | |
63bc5164 | 139 | |
fcbc51e5 PZ |
140 | spin_unlock(&tve->lock); |
141 | } | |
142 | ||
143 | static void tve_enable(struct imx_tve *tve) | |
144 | { | |
fcbc51e5 PZ |
145 | int ret; |
146 | ||
fcbc51e5 | 147 | if (!tve->enabled) { |
89bc5be7 | 148 | tve->enabled = true; |
fcbc51e5 PZ |
149 | clk_prepare_enable(tve->clk); |
150 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
151 | TVE_IPU_CLK_EN | TVE_EN, | |
152 | TVE_IPU_CLK_EN | TVE_EN); | |
153 | } | |
154 | ||
155 | /* clear interrupt status register */ | |
156 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
157 | ||
158 | /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ | |
159 | if (tve->mode == TVE_MODE_VGA) | |
160 | regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); | |
161 | else | |
162 | regmap_write(tve->regmap, TVE_INT_CONT_REG, | |
89911e58 AW |
163 | TVE_CD_SM_IEN | |
164 | TVE_CD_LM_IEN | | |
165 | TVE_CD_MON_END_IEN); | |
fcbc51e5 PZ |
166 | } |
167 | ||
168 | static void tve_disable(struct imx_tve *tve) | |
169 | { | |
fcbc51e5 PZ |
170 | int ret; |
171 | ||
fcbc51e5 | 172 | if (tve->enabled) { |
89bc5be7 | 173 | tve->enabled = false; |
fcbc51e5 PZ |
174 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
175 | TVE_IPU_CLK_EN | TVE_EN, 0); | |
176 | clk_disable_unprepare(tve->clk); | |
177 | } | |
fcbc51e5 PZ |
178 | } |
179 | ||
180 | static int tve_setup_tvout(struct imx_tve *tve) | |
181 | { | |
182 | return -ENOTSUPP; | |
183 | } | |
184 | ||
185 | static int tve_setup_vga(struct imx_tve *tve) | |
186 | { | |
187 | unsigned int mask; | |
188 | unsigned int val; | |
189 | int ret; | |
190 | ||
191 | /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ | |
192 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, | |
193 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
194 | if (ret) |
195 | return ret; | |
196 | ||
fcbc51e5 PZ |
197 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, |
198 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
199 | if (ret) |
200 | return ret; | |
201 | ||
fcbc51e5 PZ |
202 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, |
203 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
204 | if (ret) |
205 | return ret; | |
fcbc51e5 PZ |
206 | |
207 | /* set configuration register */ | |
208 | mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; | |
209 | val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; | |
210 | mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; | |
211 | val |= TVE_TV_STAND_HD_1080P30 | 0; | |
212 | mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; | |
213 | val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; | |
214 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); | |
f555e7ea | 215 | if (ret) |
fcbc51e5 | 216 | return ret; |
fcbc51e5 PZ |
217 | |
218 | /* set test mode (as documented) */ | |
f555e7ea | 219 | return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, |
fcbc51e5 | 220 | TVE_TVDAC_TEST_MODE_MASK, 1); |
fcbc51e5 PZ |
221 | } |
222 | ||
223 | static enum drm_connector_status imx_tve_connector_detect( | |
224 | struct drm_connector *connector, bool force) | |
225 | { | |
226 | return connector_status_connected; | |
227 | } | |
228 | ||
fcbc51e5 PZ |
229 | static int imx_tve_connector_get_modes(struct drm_connector *connector) |
230 | { | |
231 | struct imx_tve *tve = con_to_tve(connector); | |
232 | struct edid *edid; | |
233 | int ret = 0; | |
234 | ||
235 | if (!tve->ddc) | |
236 | return 0; | |
237 | ||
238 | edid = drm_get_edid(connector, tve->ddc); | |
239 | if (edid) { | |
240 | drm_mode_connector_update_edid_property(connector, edid); | |
241 | ret = drm_add_edid_modes(connector, edid); | |
242 | kfree(edid); | |
243 | } | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | static int imx_tve_connector_mode_valid(struct drm_connector *connector, | |
249 | struct drm_display_mode *mode) | |
250 | { | |
251 | struct imx_tve *tve = con_to_tve(connector); | |
252 | unsigned long rate; | |
baa68c4b | 253 | |
fcbc51e5 PZ |
254 | /* pixel clock with 2x oversampling */ |
255 | rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; | |
256 | if (rate == mode->clock) | |
257 | return MODE_OK; | |
258 | ||
259 | /* pixel clock without oversampling */ | |
260 | rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; | |
261 | if (rate == mode->clock) | |
262 | return MODE_OK; | |
263 | ||
264 | dev_warn(tve->dev, "ignoring mode %dx%d\n", | |
265 | mode->hdisplay, mode->vdisplay); | |
266 | ||
267 | return MODE_BAD; | |
268 | } | |
269 | ||
270 | static struct drm_encoder *imx_tve_connector_best_encoder( | |
271 | struct drm_connector *connector) | |
272 | { | |
273 | struct imx_tve *tve = con_to_tve(connector); | |
274 | ||
275 | return &tve->encoder; | |
276 | } | |
277 | ||
278 | static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode) | |
279 | { | |
280 | struct imx_tve *tve = enc_to_tve(encoder); | |
281 | int ret; | |
282 | ||
283 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
284 | TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE); | |
285 | if (ret < 0) | |
286 | dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret); | |
287 | } | |
288 | ||
289 | static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder, | |
290 | const struct drm_display_mode *mode, | |
291 | struct drm_display_mode *adjusted_mode) | |
292 | { | |
293 | return true; | |
294 | } | |
295 | ||
296 | static void imx_tve_encoder_prepare(struct drm_encoder *encoder) | |
297 | { | |
298 | struct imx_tve *tve = enc_to_tve(encoder); | |
299 | ||
300 | tve_disable(tve); | |
301 | ||
302 | switch (tve->mode) { | |
303 | case TVE_MODE_VGA: | |
f2d66aad | 304 | imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, |
fcbc51e5 PZ |
305 | tve->hsync_pin, tve->vsync_pin); |
306 | break; | |
307 | case TVE_MODE_TVOUT: | |
f2d66aad | 308 | imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444); |
fcbc51e5 PZ |
309 | break; |
310 | } | |
311 | } | |
312 | ||
313 | static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, | |
eb10d635 SL |
314 | struct drm_display_mode *orig_mode, |
315 | struct drm_display_mode *mode) | |
fcbc51e5 PZ |
316 | { |
317 | struct imx_tve *tve = enc_to_tve(encoder); | |
318 | unsigned long rounded_rate; | |
319 | unsigned long rate; | |
320 | int div = 1; | |
321 | int ret; | |
322 | ||
323 | /* | |
324 | * FIXME | |
325 | * we should try 4k * mode->clock first, | |
326 | * and enable 4x oversampling for lower resolutions | |
327 | */ | |
328 | rate = 2000UL * mode->clock; | |
329 | clk_set_rate(tve->clk, rate); | |
330 | rounded_rate = clk_get_rate(tve->clk); | |
331 | if (rounded_rate >= rate) | |
332 | div = 2; | |
333 | clk_set_rate(tve->di_clk, rounded_rate / div); | |
334 | ||
335 | ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); | |
336 | if (ret < 0) { | |
337 | dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", | |
338 | ret); | |
339 | } | |
340 | ||
341 | if (tve->mode == TVE_MODE_VGA) | |
f555e7ea | 342 | ret = tve_setup_vga(tve); |
fcbc51e5 | 343 | else |
f555e7ea FE |
344 | ret = tve_setup_tvout(tve); |
345 | if (ret) | |
346 | dev_err(tve->dev, "failed to set configuration: %d\n", ret); | |
fcbc51e5 PZ |
347 | } |
348 | ||
349 | static void imx_tve_encoder_commit(struct drm_encoder *encoder) | |
350 | { | |
351 | struct imx_tve *tve = enc_to_tve(encoder); | |
352 | ||
353 | tve_enable(tve); | |
354 | } | |
355 | ||
356 | static void imx_tve_encoder_disable(struct drm_encoder *encoder) | |
357 | { | |
358 | struct imx_tve *tve = enc_to_tve(encoder); | |
359 | ||
360 | tve_disable(tve); | |
361 | } | |
362 | ||
fcbc51e5 PZ |
363 | static struct drm_connector_funcs imx_tve_connector_funcs = { |
364 | .dpms = drm_helper_connector_dpms, | |
365 | .fill_modes = drm_helper_probe_single_connector_modes, | |
366 | .detect = imx_tve_connector_detect, | |
1b3f7675 | 367 | .destroy = imx_drm_connector_destroy, |
fcbc51e5 PZ |
368 | }; |
369 | ||
370 | static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { | |
371 | .get_modes = imx_tve_connector_get_modes, | |
372 | .best_encoder = imx_tve_connector_best_encoder, | |
373 | .mode_valid = imx_tve_connector_mode_valid, | |
374 | }; | |
375 | ||
376 | static struct drm_encoder_funcs imx_tve_encoder_funcs = { | |
1b3f7675 | 377 | .destroy = imx_drm_encoder_destroy, |
fcbc51e5 PZ |
378 | }; |
379 | ||
380 | static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { | |
381 | .dpms = imx_tve_encoder_dpms, | |
382 | .mode_fixup = imx_tve_encoder_mode_fixup, | |
383 | .prepare = imx_tve_encoder_prepare, | |
384 | .mode_set = imx_tve_encoder_mode_set, | |
385 | .commit = imx_tve_encoder_commit, | |
386 | .disable = imx_tve_encoder_disable, | |
387 | }; | |
388 | ||
389 | static irqreturn_t imx_tve_irq_handler(int irq, void *data) | |
390 | { | |
391 | struct imx_tve *tve = data; | |
392 | unsigned int val; | |
393 | ||
394 | regmap_read(tve->regmap, TVE_STAT_REG, &val); | |
395 | ||
396 | /* clear interrupt status register */ | |
397 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
398 | ||
399 | return IRQ_HANDLED; | |
400 | } | |
401 | ||
402 | static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, | |
403 | unsigned long parent_rate) | |
404 | { | |
405 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
406 | unsigned int val; | |
407 | int ret; | |
408 | ||
409 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
410 | if (ret < 0) | |
411 | return 0; | |
412 | ||
413 | switch (val & TVE_DAC_SAMP_RATE_MASK) { | |
414 | case TVE_DAC_DIV4_RATE: | |
415 | return parent_rate / 4; | |
416 | case TVE_DAC_DIV2_RATE: | |
417 | return parent_rate / 2; | |
418 | case TVE_DAC_FULL_RATE: | |
419 | default: | |
420 | return parent_rate; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, | |
427 | unsigned long *prate) | |
428 | { | |
429 | unsigned long div; | |
430 | ||
431 | div = *prate / rate; | |
432 | if (div >= 4) | |
433 | return *prate / 4; | |
434 | else if (div >= 2) | |
435 | return *prate / 2; | |
7557b6e1 | 436 | return *prate; |
fcbc51e5 PZ |
437 | } |
438 | ||
439 | static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, | |
440 | unsigned long parent_rate) | |
441 | { | |
442 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
443 | unsigned long div; | |
444 | u32 val; | |
445 | int ret; | |
446 | ||
447 | div = parent_rate / rate; | |
448 | if (div >= 4) | |
449 | val = TVE_DAC_DIV4_RATE; | |
450 | else if (div >= 2) | |
451 | val = TVE_DAC_DIV2_RATE; | |
452 | else | |
453 | val = TVE_DAC_FULL_RATE; | |
454 | ||
89911e58 AW |
455 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
456 | TVE_DAC_SAMP_RATE_MASK, val); | |
457 | ||
fcbc51e5 PZ |
458 | if (ret < 0) { |
459 | dev_err(tve->dev, "failed to set divider: %d\n", ret); | |
460 | return ret; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static struct clk_ops clk_tve_di_ops = { | |
467 | .round_rate = clk_tve_di_round_rate, | |
468 | .set_rate = clk_tve_di_set_rate, | |
469 | .recalc_rate = clk_tve_di_recalc_rate, | |
470 | }; | |
471 | ||
472 | static int tve_clk_init(struct imx_tve *tve, void __iomem *base) | |
473 | { | |
474 | const char *tve_di_parent[1]; | |
475 | struct clk_init_data init = { | |
476 | .name = "tve_di", | |
477 | .ops = &clk_tve_di_ops, | |
478 | .num_parents = 1, | |
479 | .flags = 0, | |
480 | }; | |
481 | ||
482 | tve_di_parent[0] = __clk_get_name(tve->clk); | |
483 | init.parent_names = (const char **)&tve_di_parent; | |
484 | ||
485 | tve->clk_hw_di.init = &init; | |
486 | tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); | |
487 | if (IS_ERR(tve->di_clk)) { | |
488 | dev_err(tve->dev, "failed to register TVE output clock: %ld\n", | |
489 | PTR_ERR(tve->di_clk)); | |
490 | return PTR_ERR(tve->di_clk); | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
1b3f7675 | 496 | static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) |
fcbc51e5 | 497 | { |
f2d66aad | 498 | int encoder_type; |
fcbc51e5 PZ |
499 | int ret; |
500 | ||
f2d66aad RK |
501 | encoder_type = tve->mode == TVE_MODE_VGA ? |
502 | DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; | |
503 | ||
1b3f7675 RK |
504 | ret = imx_drm_encoder_parse_of(drm, &tve->encoder, |
505 | tve->dev->of_node); | |
506 | if (ret) | |
507 | return ret; | |
fcbc51e5 PZ |
508 | |
509 | drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); | |
1b3f7675 RK |
510 | drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, |
511 | encoder_type); | |
fcbc51e5 PZ |
512 | |
513 | drm_connector_helper_add(&tve->connector, | |
514 | &imx_tve_connector_helper_funcs); | |
1b3f7675 RK |
515 | drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs, |
516 | DRM_MODE_CONNECTOR_VGA); | |
fcbc51e5 PZ |
517 | |
518 | drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) | |
524 | { | |
525 | return (reg % 4 == 0) && (reg <= 0xdc); | |
526 | } | |
527 | ||
528 | static struct regmap_config tve_regmap_config = { | |
529 | .reg_bits = 32, | |
530 | .val_bits = 32, | |
531 | .reg_stride = 4, | |
532 | ||
533 | .readable_reg = imx_tve_readable_reg, | |
534 | ||
535 | .lock = tve_lock, | |
536 | .unlock = tve_unlock, | |
537 | ||
538 | .max_register = 0xdc, | |
539 | }; | |
540 | ||
8684ba72 | 541 | static const char * const imx_tve_modes[] = { |
fcbc51e5 PZ |
542 | [TVE_MODE_TVOUT] = "tvout", |
543 | [TVE_MODE_VGA] = "vga", | |
544 | }; | |
545 | ||
7fc6cb28 | 546 | static const int of_get_tve_mode(struct device_node *np) |
fcbc51e5 PZ |
547 | { |
548 | const char *bm; | |
549 | int ret, i; | |
550 | ||
551 | ret = of_property_read_string(np, "fsl,tve-mode", &bm); | |
552 | if (ret < 0) | |
553 | return ret; | |
554 | ||
555 | for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) | |
556 | if (!strcasecmp(bm, imx_tve_modes[i])) | |
557 | return i; | |
558 | ||
559 | return -EINVAL; | |
560 | } | |
561 | ||
17b5001b | 562 | static int imx_tve_bind(struct device *dev, struct device *master, void *data) |
fcbc51e5 | 563 | { |
17b5001b | 564 | struct platform_device *pdev = to_platform_device(dev); |
1b3f7675 | 565 | struct drm_device *drm = data; |
17b5001b | 566 | struct device_node *np = dev->of_node; |
fcbc51e5 PZ |
567 | struct device_node *ddc_node; |
568 | struct imx_tve *tve; | |
569 | struct resource *res; | |
570 | void __iomem *base; | |
571 | unsigned int val; | |
572 | int irq; | |
573 | int ret; | |
574 | ||
17b5001b | 575 | tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL); |
fcbc51e5 PZ |
576 | if (!tve) |
577 | return -ENOMEM; | |
578 | ||
17b5001b | 579 | tve->dev = dev; |
fcbc51e5 | 580 | spin_lock_init(&tve->lock); |
fcbc51e5 | 581 | |
a3fe9641 | 582 | ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); |
fcbc51e5 PZ |
583 | if (ddc_node) { |
584 | tve->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
585 | of_node_put(ddc_node); | |
586 | } | |
587 | ||
588 | tve->mode = of_get_tve_mode(np); | |
589 | if (tve->mode != TVE_MODE_VGA) { | |
17b5001b | 590 | dev_err(dev, "only VGA mode supported, currently\n"); |
fcbc51e5 PZ |
591 | return -EINVAL; |
592 | } | |
593 | ||
594 | if (tve->mode == TVE_MODE_VGA) { | |
89911e58 AW |
595 | ret = of_property_read_u32(np, "fsl,hsync-pin", |
596 | &tve->hsync_pin); | |
597 | ||
fcbc51e5 | 598 | if (ret < 0) { |
17b5001b | 599 | dev_err(dev, "failed to get vsync pin\n"); |
fcbc51e5 PZ |
600 | return ret; |
601 | } | |
602 | ||
89911e58 AW |
603 | ret |= of_property_read_u32(np, "fsl,vsync-pin", |
604 | &tve->vsync_pin); | |
605 | ||
fcbc51e5 | 606 | if (ret < 0) { |
17b5001b | 607 | dev_err(dev, "failed to get vsync pin\n"); |
fcbc51e5 PZ |
608 | return ret; |
609 | } | |
610 | } | |
611 | ||
612 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
17b5001b | 613 | base = devm_ioremap_resource(dev, res); |
9b43b56f LN |
614 | if (IS_ERR(base)) |
615 | return PTR_ERR(base); | |
fcbc51e5 PZ |
616 | |
617 | tve_regmap_config.lock_arg = tve; | |
17b5001b | 618 | tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, |
fcbc51e5 PZ |
619 | &tve_regmap_config); |
620 | if (IS_ERR(tve->regmap)) { | |
17b5001b | 621 | dev_err(dev, "failed to init regmap: %ld\n", |
fcbc51e5 PZ |
622 | PTR_ERR(tve->regmap)); |
623 | return PTR_ERR(tve->regmap); | |
624 | } | |
625 | ||
626 | irq = platform_get_irq(pdev, 0); | |
627 | if (irq < 0) { | |
17b5001b | 628 | dev_err(dev, "failed to get irq\n"); |
fcbc51e5 PZ |
629 | return irq; |
630 | } | |
631 | ||
17b5001b | 632 | ret = devm_request_threaded_irq(dev, irq, NULL, |
fcbc51e5 PZ |
633 | imx_tve_irq_handler, IRQF_ONESHOT, |
634 | "imx-tve", tve); | |
635 | if (ret < 0) { | |
17b5001b | 636 | dev_err(dev, "failed to request irq: %d\n", ret); |
fcbc51e5 PZ |
637 | return ret; |
638 | } | |
639 | ||
17b5001b | 640 | tve->dac_reg = devm_regulator_get(dev, "dac"); |
fcbc51e5 PZ |
641 | if (!IS_ERR(tve->dac_reg)) { |
642 | regulator_set_voltage(tve->dac_reg, 2750000, 2750000); | |
c7b0cf3e FE |
643 | ret = regulator_enable(tve->dac_reg); |
644 | if (ret) | |
645 | return ret; | |
fcbc51e5 PZ |
646 | } |
647 | ||
17b5001b | 648 | tve->clk = devm_clk_get(dev, "tve"); |
fcbc51e5 | 649 | if (IS_ERR(tve->clk)) { |
17b5001b | 650 | dev_err(dev, "failed to get high speed tve clock: %ld\n", |
fcbc51e5 PZ |
651 | PTR_ERR(tve->clk)); |
652 | return PTR_ERR(tve->clk); | |
653 | } | |
654 | ||
655 | /* this is the IPU DI clock input selector, can be parented to tve_di */ | |
17b5001b | 656 | tve->di_sel_clk = devm_clk_get(dev, "di_sel"); |
fcbc51e5 | 657 | if (IS_ERR(tve->di_sel_clk)) { |
17b5001b | 658 | dev_err(dev, "failed to get ipu di mux clock: %ld\n", |
fcbc51e5 PZ |
659 | PTR_ERR(tve->di_sel_clk)); |
660 | return PTR_ERR(tve->di_sel_clk); | |
661 | } | |
662 | ||
663 | ret = tve_clk_init(tve, base); | |
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
667 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
668 | if (ret < 0) { | |
f582d9a8 RK |
669 | dev_err(dev, "failed to read configuration register: %d\n", |
670 | ret); | |
fcbc51e5 PZ |
671 | return ret; |
672 | } | |
673 | if (val != 0x00100000) { | |
17b5001b | 674 | dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); |
fcbc51e5 | 675 | return -ENODEV; |
a22526e4 | 676 | } |
fcbc51e5 PZ |
677 | |
678 | /* disable cable detection for VGA mode */ | |
679 | ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); | |
f555e7ea FE |
680 | if (ret) |
681 | return ret; | |
fcbc51e5 | 682 | |
1b3f7675 | 683 | ret = imx_tve_register(drm, tve); |
fcbc51e5 PZ |
684 | if (ret) |
685 | return ret; | |
686 | ||
17b5001b | 687 | dev_set_drvdata(dev, tve); |
fcbc51e5 PZ |
688 | |
689 | return 0; | |
690 | } | |
691 | ||
17b5001b RK |
692 | static void imx_tve_unbind(struct device *dev, struct device *master, |
693 | void *data) | |
fcbc51e5 | 694 | { |
17b5001b | 695 | struct imx_tve *tve = dev_get_drvdata(dev); |
fcbc51e5 | 696 | |
1b3f7675 RK |
697 | tve->connector.funcs->destroy(&tve->connector); |
698 | tve->encoder.funcs->destroy(&tve->encoder); | |
fcbc51e5 PZ |
699 | |
700 | if (!IS_ERR(tve->dac_reg)) | |
701 | regulator_disable(tve->dac_reg); | |
17b5001b | 702 | } |
fcbc51e5 | 703 | |
17b5001b RK |
704 | static const struct component_ops imx_tve_ops = { |
705 | .bind = imx_tve_bind, | |
706 | .unbind = imx_tve_unbind, | |
707 | }; | |
708 | ||
709 | static int imx_tve_probe(struct platform_device *pdev) | |
710 | { | |
711 | return component_add(&pdev->dev, &imx_tve_ops); | |
712 | } | |
713 | ||
714 | static int imx_tve_remove(struct platform_device *pdev) | |
715 | { | |
716 | component_del(&pdev->dev, &imx_tve_ops); | |
fcbc51e5 PZ |
717 | return 0; |
718 | } | |
719 | ||
720 | static const struct of_device_id imx_tve_dt_ids[] = { | |
721 | { .compatible = "fsl,imx53-tve", }, | |
722 | { /* sentinel */ } | |
723 | }; | |
724 | ||
725 | static struct platform_driver imx_tve_driver = { | |
726 | .probe = imx_tve_probe, | |
727 | .remove = imx_tve_remove, | |
728 | .driver = { | |
729 | .of_match_table = imx_tve_dt_ids, | |
730 | .name = "imx-tve", | |
fcbc51e5 PZ |
731 | }, |
732 | }; | |
733 | ||
734 | module_platform_driver(imx_tve_driver); | |
735 | ||
736 | MODULE_DESCRIPTION("i.MX Television Encoder driver"); | |
737 | MODULE_AUTHOR("Philipp Zabel, Pengutronix"); | |
738 | MODULE_LICENSE("GPL"); | |
52db752c | 739 | MODULE_ALIAS("platform:imx-tve"); |