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fcbc51e5 PZ |
1 | /* |
2 | * i.MX drm driver - Television Encoder (TVEv2) | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
fcbc51e5 PZ |
14 | */ |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/clk-provider.h> | |
17b5001b | 18 | #include <linux/component.h> |
fcbc51e5 | 19 | #include <linux/module.h> |
687b81d0 | 20 | #include <linux/i2c.h> |
fcbc51e5 PZ |
21 | #include <linux/regmap.h> |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/videodev2.h> | |
25 | #include <drm/drmP.h> | |
255c35f8 | 26 | #include <drm/drm_atomic_helper.h> |
fcbc51e5 PZ |
27 | #include <drm/drm_fb_helper.h> |
28 | #include <drm/drm_crtc_helper.h> | |
39b9004d | 29 | #include <video/imx-ipu-v3.h> |
fcbc51e5 PZ |
30 | |
31 | #include "imx-drm.h" | |
32 | ||
33 | #define TVE_COM_CONF_REG 0x00 | |
34 | #define TVE_TVDAC0_CONT_REG 0x28 | |
35 | #define TVE_TVDAC1_CONT_REG 0x2c | |
36 | #define TVE_TVDAC2_CONT_REG 0x30 | |
37 | #define TVE_CD_CONT_REG 0x34 | |
38 | #define TVE_INT_CONT_REG 0x64 | |
39 | #define TVE_STAT_REG 0x68 | |
40 | #define TVE_TST_MODE_REG 0x6c | |
41 | #define TVE_MV_CONT_REG 0xdc | |
42 | ||
43 | /* TVE_COM_CONF_REG */ | |
44 | #define TVE_SYNC_CH_2_EN BIT(22) | |
45 | #define TVE_SYNC_CH_1_EN BIT(21) | |
46 | #define TVE_SYNC_CH_0_EN BIT(20) | |
47 | #define TVE_TV_OUT_MODE_MASK (0x7 << 12) | |
48 | #define TVE_TV_OUT_DISABLE (0x0 << 12) | |
49 | #define TVE_TV_OUT_CVBS_0 (0x1 << 12) | |
50 | #define TVE_TV_OUT_CVBS_2 (0x2 << 12) | |
51 | #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) | |
52 | #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) | |
53 | #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) | |
54 | #define TVE_TV_OUT_YPBPR (0x6 << 12) | |
55 | #define TVE_TV_OUT_RGB (0x7 << 12) | |
56 | #define TVE_TV_STAND_MASK (0xf << 8) | |
57 | #define TVE_TV_STAND_HD_1080P30 (0xc << 8) | |
58 | #define TVE_P2I_CONV_EN BIT(7) | |
59 | #define TVE_INP_VIDEO_FORM BIT(6) | |
60 | #define TVE_INP_YCBCR_422 (0x0 << 6) | |
61 | #define TVE_INP_YCBCR_444 (0x1 << 6) | |
62 | #define TVE_DATA_SOURCE_MASK (0x3 << 4) | |
63 | #define TVE_DATA_SOURCE_BUS1 (0x0 << 4) | |
64 | #define TVE_DATA_SOURCE_BUS2 (0x1 << 4) | |
65 | #define TVE_DATA_SOURCE_EXT (0x2 << 4) | |
66 | #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) | |
67 | #define TVE_IPU_CLK_EN_OFS 3 | |
68 | #define TVE_IPU_CLK_EN BIT(3) | |
69 | #define TVE_DAC_SAMP_RATE_OFS 1 | |
70 | #define TVE_DAC_SAMP_RATE_WIDTH 2 | |
71 | #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) | |
72 | #define TVE_DAC_FULL_RATE (0x0 << 1) | |
73 | #define TVE_DAC_DIV2_RATE (0x1 << 1) | |
74 | #define TVE_DAC_DIV4_RATE (0x2 << 1) | |
75 | #define TVE_EN BIT(0) | |
76 | ||
77 | /* TVE_TVDACx_CONT_REG */ | |
78 | #define TVE_TVDAC_GAIN_MASK (0x3f << 0) | |
79 | ||
80 | /* TVE_CD_CONT_REG */ | |
81 | #define TVE_CD_CH_2_SM_EN BIT(22) | |
82 | #define TVE_CD_CH_1_SM_EN BIT(21) | |
83 | #define TVE_CD_CH_0_SM_EN BIT(20) | |
84 | #define TVE_CD_CH_2_LM_EN BIT(18) | |
85 | #define TVE_CD_CH_1_LM_EN BIT(17) | |
86 | #define TVE_CD_CH_0_LM_EN BIT(16) | |
87 | #define TVE_CD_CH_2_REF_LVL BIT(10) | |
88 | #define TVE_CD_CH_1_REF_LVL BIT(9) | |
89 | #define TVE_CD_CH_0_REF_LVL BIT(8) | |
90 | #define TVE_CD_EN BIT(0) | |
91 | ||
92 | /* TVE_INT_CONT_REG */ | |
93 | #define TVE_FRAME_END_IEN BIT(13) | |
94 | #define TVE_CD_MON_END_IEN BIT(2) | |
95 | #define TVE_CD_SM_IEN BIT(1) | |
96 | #define TVE_CD_LM_IEN BIT(0) | |
97 | ||
98 | /* TVE_TST_MODE_REG */ | |
99 | #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) | |
100 | ||
fcbc51e5 PZ |
101 | enum { |
102 | TVE_MODE_TVOUT, | |
103 | TVE_MODE_VGA, | |
104 | }; | |
105 | ||
106 | struct imx_tve { | |
107 | struct drm_connector connector; | |
49f98bc4 | 108 | struct drm_encoder encoder; |
fcbc51e5 | 109 | struct device *dev; |
fcbc51e5 PZ |
110 | spinlock_t lock; /* register lock */ |
111 | bool enabled; | |
112 | int mode; | |
49f98bc4 PZ |
113 | int di_hsync_pin; |
114 | int di_vsync_pin; | |
fcbc51e5 PZ |
115 | |
116 | struct regmap *regmap; | |
117 | struct regulator *dac_reg; | |
118 | struct i2c_adapter *ddc; | |
119 | struct clk *clk; | |
120 | struct clk *di_sel_clk; | |
121 | struct clk_hw clk_hw_di; | |
122 | struct clk *di_clk; | |
fcbc51e5 PZ |
123 | }; |
124 | ||
3df07390 PZ |
125 | static inline struct imx_tve *con_to_tve(struct drm_connector *c) |
126 | { | |
127 | return container_of(c, struct imx_tve, connector); | |
128 | } | |
129 | ||
49f98bc4 PZ |
130 | static inline struct imx_tve *enc_to_tve(struct drm_encoder *e) |
131 | { | |
132 | return container_of(e, struct imx_tve, encoder); | |
133 | } | |
134 | ||
fcbc51e5 | 135 | static void tve_lock(void *__tve) |
5d78bf80 | 136 | __acquires(&tve->lock) |
fcbc51e5 PZ |
137 | { |
138 | struct imx_tve *tve = __tve; | |
63bc5164 | 139 | |
fcbc51e5 PZ |
140 | spin_lock(&tve->lock); |
141 | } | |
142 | ||
143 | static void tve_unlock(void *__tve) | |
5d78bf80 | 144 | __releases(&tve->lock) |
fcbc51e5 PZ |
145 | { |
146 | struct imx_tve *tve = __tve; | |
63bc5164 | 147 | |
fcbc51e5 PZ |
148 | spin_unlock(&tve->lock); |
149 | } | |
150 | ||
151 | static void tve_enable(struct imx_tve *tve) | |
152 | { | |
fcbc51e5 PZ |
153 | int ret; |
154 | ||
fcbc51e5 | 155 | if (!tve->enabled) { |
89bc5be7 | 156 | tve->enabled = true; |
fcbc51e5 PZ |
157 | clk_prepare_enable(tve->clk); |
158 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
f6e396e5 | 159 | TVE_EN, TVE_EN); |
fcbc51e5 PZ |
160 | } |
161 | ||
162 | /* clear interrupt status register */ | |
163 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
164 | ||
165 | /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ | |
166 | if (tve->mode == TVE_MODE_VGA) | |
167 | regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); | |
168 | else | |
169 | regmap_write(tve->regmap, TVE_INT_CONT_REG, | |
89911e58 AW |
170 | TVE_CD_SM_IEN | |
171 | TVE_CD_LM_IEN | | |
172 | TVE_CD_MON_END_IEN); | |
fcbc51e5 PZ |
173 | } |
174 | ||
175 | static void tve_disable(struct imx_tve *tve) | |
176 | { | |
fcbc51e5 PZ |
177 | int ret; |
178 | ||
fcbc51e5 | 179 | if (tve->enabled) { |
89bc5be7 | 180 | tve->enabled = false; |
fcbc51e5 | 181 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
f6e396e5 | 182 | TVE_EN, 0); |
fcbc51e5 PZ |
183 | clk_disable_unprepare(tve->clk); |
184 | } | |
fcbc51e5 PZ |
185 | } |
186 | ||
187 | static int tve_setup_tvout(struct imx_tve *tve) | |
188 | { | |
189 | return -ENOTSUPP; | |
190 | } | |
191 | ||
192 | static int tve_setup_vga(struct imx_tve *tve) | |
193 | { | |
194 | unsigned int mask; | |
195 | unsigned int val; | |
196 | int ret; | |
197 | ||
198 | /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ | |
199 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, | |
200 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
201 | if (ret) |
202 | return ret; | |
203 | ||
fcbc51e5 PZ |
204 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, |
205 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
206 | if (ret) |
207 | return ret; | |
208 | ||
fcbc51e5 PZ |
209 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, |
210 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
f555e7ea FE |
211 | if (ret) |
212 | return ret; | |
fcbc51e5 PZ |
213 | |
214 | /* set configuration register */ | |
215 | mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; | |
216 | val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; | |
217 | mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; | |
218 | val |= TVE_TV_STAND_HD_1080P30 | 0; | |
219 | mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; | |
220 | val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; | |
221 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); | |
f555e7ea | 222 | if (ret) |
fcbc51e5 | 223 | return ret; |
fcbc51e5 PZ |
224 | |
225 | /* set test mode (as documented) */ | |
f555e7ea | 226 | return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, |
fcbc51e5 | 227 | TVE_TVDAC_TEST_MODE_MASK, 1); |
fcbc51e5 PZ |
228 | } |
229 | ||
230 | static enum drm_connector_status imx_tve_connector_detect( | |
231 | struct drm_connector *connector, bool force) | |
232 | { | |
233 | return connector_status_connected; | |
234 | } | |
235 | ||
fcbc51e5 PZ |
236 | static int imx_tve_connector_get_modes(struct drm_connector *connector) |
237 | { | |
238 | struct imx_tve *tve = con_to_tve(connector); | |
239 | struct edid *edid; | |
240 | int ret = 0; | |
241 | ||
242 | if (!tve->ddc) | |
243 | return 0; | |
244 | ||
245 | edid = drm_get_edid(connector, tve->ddc); | |
246 | if (edid) { | |
247 | drm_mode_connector_update_edid_property(connector, edid); | |
248 | ret = drm_add_edid_modes(connector, edid); | |
249 | kfree(edid); | |
250 | } | |
251 | ||
252 | return ret; | |
253 | } | |
254 | ||
255 | static int imx_tve_connector_mode_valid(struct drm_connector *connector, | |
256 | struct drm_display_mode *mode) | |
257 | { | |
258 | struct imx_tve *tve = con_to_tve(connector); | |
259 | unsigned long rate; | |
baa68c4b | 260 | |
fcbc51e5 PZ |
261 | /* pixel clock with 2x oversampling */ |
262 | rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; | |
263 | if (rate == mode->clock) | |
264 | return MODE_OK; | |
265 | ||
266 | /* pixel clock without oversampling */ | |
267 | rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; | |
268 | if (rate == mode->clock) | |
269 | return MODE_OK; | |
270 | ||
271 | dev_warn(tve->dev, "ignoring mode %dx%d\n", | |
272 | mode->hdisplay, mode->vdisplay); | |
273 | ||
274 | return MODE_BAD; | |
275 | } | |
276 | ||
277 | static struct drm_encoder *imx_tve_connector_best_encoder( | |
278 | struct drm_connector *connector) | |
279 | { | |
280 | struct imx_tve *tve = con_to_tve(connector); | |
281 | ||
49f98bc4 | 282 | return &tve->encoder; |
fcbc51e5 PZ |
283 | } |
284 | ||
fcbc51e5 | 285 | static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, |
eb10d635 SL |
286 | struct drm_display_mode *orig_mode, |
287 | struct drm_display_mode *mode) | |
fcbc51e5 | 288 | { |
49f98bc4 | 289 | struct imx_tve *tve = enc_to_tve(encoder); |
fcbc51e5 PZ |
290 | unsigned long rounded_rate; |
291 | unsigned long rate; | |
292 | int div = 1; | |
293 | int ret; | |
294 | ||
295 | /* | |
296 | * FIXME | |
297 | * we should try 4k * mode->clock first, | |
298 | * and enable 4x oversampling for lower resolutions | |
299 | */ | |
300 | rate = 2000UL * mode->clock; | |
301 | clk_set_rate(tve->clk, rate); | |
302 | rounded_rate = clk_get_rate(tve->clk); | |
303 | if (rounded_rate >= rate) | |
304 | div = 2; | |
305 | clk_set_rate(tve->di_clk, rounded_rate / div); | |
306 | ||
307 | ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); | |
308 | if (ret < 0) { | |
309 | dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", | |
310 | ret); | |
311 | } | |
312 | ||
f6e396e5 LY |
313 | regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
314 | TVE_IPU_CLK_EN, TVE_IPU_CLK_EN); | |
315 | ||
fcbc51e5 | 316 | if (tve->mode == TVE_MODE_VGA) |
f555e7ea | 317 | ret = tve_setup_vga(tve); |
fcbc51e5 | 318 | else |
f555e7ea FE |
319 | ret = tve_setup_tvout(tve); |
320 | if (ret) | |
321 | dev_err(tve->dev, "failed to set configuration: %d\n", ret); | |
fcbc51e5 PZ |
322 | } |
323 | ||
f6e396e5 | 324 | static void imx_tve_encoder_enable(struct drm_encoder *encoder) |
fcbc51e5 | 325 | { |
49f98bc4 | 326 | struct imx_tve *tve = enc_to_tve(encoder); |
fcbc51e5 PZ |
327 | |
328 | tve_enable(tve); | |
329 | } | |
330 | ||
331 | static void imx_tve_encoder_disable(struct drm_encoder *encoder) | |
332 | { | |
49f98bc4 | 333 | struct imx_tve *tve = enc_to_tve(encoder); |
fcbc51e5 PZ |
334 | |
335 | tve_disable(tve); | |
336 | } | |
337 | ||
49f98bc4 PZ |
338 | static int imx_tve_atomic_check(struct drm_encoder *encoder, |
339 | struct drm_crtc_state *crtc_state, | |
340 | struct drm_connector_state *conn_state) | |
341 | { | |
342 | struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); | |
343 | struct imx_tve *tve = enc_to_tve(encoder); | |
344 | ||
345 | imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24; | |
346 | imx_crtc_state->di_hsync_pin = tve->di_hsync_pin; | |
347 | imx_crtc_state->di_vsync_pin = tve->di_vsync_pin; | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
7ae847dd | 352 | static const struct drm_connector_funcs imx_tve_connector_funcs = { |
f6e396e5 | 353 | .dpms = drm_atomic_helper_connector_dpms, |
fcbc51e5 PZ |
354 | .fill_modes = drm_helper_probe_single_connector_modes, |
355 | .detect = imx_tve_connector_detect, | |
1b3f7675 | 356 | .destroy = imx_drm_connector_destroy, |
255c35f8 LY |
357 | .reset = drm_atomic_helper_connector_reset, |
358 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
359 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
fcbc51e5 PZ |
360 | }; |
361 | ||
7ae847dd | 362 | static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { |
fcbc51e5 PZ |
363 | .get_modes = imx_tve_connector_get_modes, |
364 | .best_encoder = imx_tve_connector_best_encoder, | |
365 | .mode_valid = imx_tve_connector_mode_valid, | |
366 | }; | |
367 | ||
7ae847dd | 368 | static const struct drm_encoder_funcs imx_tve_encoder_funcs = { |
1b3f7675 | 369 | .destroy = imx_drm_encoder_destroy, |
fcbc51e5 PZ |
370 | }; |
371 | ||
7ae847dd | 372 | static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { |
fcbc51e5 | 373 | .mode_set = imx_tve_encoder_mode_set, |
f6e396e5 | 374 | .enable = imx_tve_encoder_enable, |
fcbc51e5 | 375 | .disable = imx_tve_encoder_disable, |
49f98bc4 | 376 | .atomic_check = imx_tve_atomic_check, |
fcbc51e5 PZ |
377 | }; |
378 | ||
379 | static irqreturn_t imx_tve_irq_handler(int irq, void *data) | |
380 | { | |
381 | struct imx_tve *tve = data; | |
382 | unsigned int val; | |
383 | ||
384 | regmap_read(tve->regmap, TVE_STAT_REG, &val); | |
385 | ||
386 | /* clear interrupt status register */ | |
387 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
388 | ||
389 | return IRQ_HANDLED; | |
390 | } | |
391 | ||
392 | static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, | |
393 | unsigned long parent_rate) | |
394 | { | |
395 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
396 | unsigned int val; | |
397 | int ret; | |
398 | ||
399 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
400 | if (ret < 0) | |
401 | return 0; | |
402 | ||
403 | switch (val & TVE_DAC_SAMP_RATE_MASK) { | |
404 | case TVE_DAC_DIV4_RATE: | |
405 | return parent_rate / 4; | |
406 | case TVE_DAC_DIV2_RATE: | |
407 | return parent_rate / 2; | |
408 | case TVE_DAC_FULL_RATE: | |
409 | default: | |
410 | return parent_rate; | |
411 | } | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, | |
417 | unsigned long *prate) | |
418 | { | |
419 | unsigned long div; | |
420 | ||
421 | div = *prate / rate; | |
422 | if (div >= 4) | |
423 | return *prate / 4; | |
424 | else if (div >= 2) | |
425 | return *prate / 2; | |
7557b6e1 | 426 | return *prate; |
fcbc51e5 PZ |
427 | } |
428 | ||
429 | static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, | |
430 | unsigned long parent_rate) | |
431 | { | |
432 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
433 | unsigned long div; | |
434 | u32 val; | |
435 | int ret; | |
436 | ||
437 | div = parent_rate / rate; | |
438 | if (div >= 4) | |
439 | val = TVE_DAC_DIV4_RATE; | |
440 | else if (div >= 2) | |
441 | val = TVE_DAC_DIV2_RATE; | |
442 | else | |
443 | val = TVE_DAC_FULL_RATE; | |
444 | ||
89911e58 AW |
445 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
446 | TVE_DAC_SAMP_RATE_MASK, val); | |
447 | ||
fcbc51e5 PZ |
448 | if (ret < 0) { |
449 | dev_err(tve->dev, "failed to set divider: %d\n", ret); | |
450 | return ret; | |
451 | } | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | static struct clk_ops clk_tve_di_ops = { | |
457 | .round_rate = clk_tve_di_round_rate, | |
458 | .set_rate = clk_tve_di_set_rate, | |
459 | .recalc_rate = clk_tve_di_recalc_rate, | |
460 | }; | |
461 | ||
462 | static int tve_clk_init(struct imx_tve *tve, void __iomem *base) | |
463 | { | |
464 | const char *tve_di_parent[1]; | |
465 | struct clk_init_data init = { | |
466 | .name = "tve_di", | |
467 | .ops = &clk_tve_di_ops, | |
468 | .num_parents = 1, | |
469 | .flags = 0, | |
470 | }; | |
471 | ||
472 | tve_di_parent[0] = __clk_get_name(tve->clk); | |
473 | init.parent_names = (const char **)&tve_di_parent; | |
474 | ||
475 | tve->clk_hw_di.init = &init; | |
476 | tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); | |
477 | if (IS_ERR(tve->di_clk)) { | |
478 | dev_err(tve->dev, "failed to register TVE output clock: %ld\n", | |
479 | PTR_ERR(tve->di_clk)); | |
480 | return PTR_ERR(tve->di_clk); | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
1b3f7675 | 486 | static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) |
fcbc51e5 | 487 | { |
f2d66aad | 488 | int encoder_type; |
fcbc51e5 PZ |
489 | int ret; |
490 | ||
f2d66aad RK |
491 | encoder_type = tve->mode == TVE_MODE_VGA ? |
492 | DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; | |
493 | ||
49f98bc4 | 494 | ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node); |
1b3f7675 RK |
495 | if (ret) |
496 | return ret; | |
fcbc51e5 | 497 | |
49f98bc4 PZ |
498 | drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); |
499 | drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, | |
13a3d91f | 500 | encoder_type, NULL); |
fcbc51e5 PZ |
501 | |
502 | drm_connector_helper_add(&tve->connector, | |
503 | &imx_tve_connector_helper_funcs); | |
1b3f7675 RK |
504 | drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs, |
505 | DRM_MODE_CONNECTOR_VGA); | |
fcbc51e5 | 506 | |
49f98bc4 | 507 | drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder); |
fcbc51e5 PZ |
508 | |
509 | return 0; | |
510 | } | |
511 | ||
512 | static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) | |
513 | { | |
514 | return (reg % 4 == 0) && (reg <= 0xdc); | |
515 | } | |
516 | ||
517 | static struct regmap_config tve_regmap_config = { | |
518 | .reg_bits = 32, | |
519 | .val_bits = 32, | |
520 | .reg_stride = 4, | |
521 | ||
522 | .readable_reg = imx_tve_readable_reg, | |
523 | ||
524 | .lock = tve_lock, | |
525 | .unlock = tve_unlock, | |
526 | ||
527 | .max_register = 0xdc, | |
528 | }; | |
529 | ||
8684ba72 | 530 | static const char * const imx_tve_modes[] = { |
fcbc51e5 PZ |
531 | [TVE_MODE_TVOUT] = "tvout", |
532 | [TVE_MODE_VGA] = "vga", | |
533 | }; | |
534 | ||
7fc6cb28 | 535 | static const int of_get_tve_mode(struct device_node *np) |
fcbc51e5 PZ |
536 | { |
537 | const char *bm; | |
538 | int ret, i; | |
539 | ||
540 | ret = of_property_read_string(np, "fsl,tve-mode", &bm); | |
541 | if (ret < 0) | |
542 | return ret; | |
543 | ||
544 | for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) | |
545 | if (!strcasecmp(bm, imx_tve_modes[i])) | |
546 | return i; | |
547 | ||
548 | return -EINVAL; | |
549 | } | |
550 | ||
17b5001b | 551 | static int imx_tve_bind(struct device *dev, struct device *master, void *data) |
fcbc51e5 | 552 | { |
17b5001b | 553 | struct platform_device *pdev = to_platform_device(dev); |
1b3f7675 | 554 | struct drm_device *drm = data; |
17b5001b | 555 | struct device_node *np = dev->of_node; |
fcbc51e5 PZ |
556 | struct device_node *ddc_node; |
557 | struct imx_tve *tve; | |
558 | struct resource *res; | |
559 | void __iomem *base; | |
560 | unsigned int val; | |
561 | int irq; | |
562 | int ret; | |
563 | ||
17b5001b | 564 | tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL); |
fcbc51e5 PZ |
565 | if (!tve) |
566 | return -ENOMEM; | |
567 | ||
17b5001b | 568 | tve->dev = dev; |
fcbc51e5 | 569 | spin_lock_init(&tve->lock); |
fcbc51e5 | 570 | |
a3fe9641 | 571 | ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); |
fcbc51e5 PZ |
572 | if (ddc_node) { |
573 | tve->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
574 | of_node_put(ddc_node); | |
575 | } | |
576 | ||
577 | tve->mode = of_get_tve_mode(np); | |
578 | if (tve->mode != TVE_MODE_VGA) { | |
17b5001b | 579 | dev_err(dev, "only VGA mode supported, currently\n"); |
fcbc51e5 PZ |
580 | return -EINVAL; |
581 | } | |
582 | ||
583 | if (tve->mode == TVE_MODE_VGA) { | |
89911e58 | 584 | ret = of_property_read_u32(np, "fsl,hsync-pin", |
49f98bc4 | 585 | &tve->di_hsync_pin); |
89911e58 | 586 | |
fcbc51e5 | 587 | if (ret < 0) { |
ae8308b2 | 588 | dev_err(dev, "failed to get hsync pin\n"); |
fcbc51e5 PZ |
589 | return ret; |
590 | } | |
591 | ||
4f7a5129 FE |
592 | ret = of_property_read_u32(np, "fsl,vsync-pin", |
593 | &tve->di_vsync_pin); | |
89911e58 | 594 | |
fcbc51e5 | 595 | if (ret < 0) { |
17b5001b | 596 | dev_err(dev, "failed to get vsync pin\n"); |
fcbc51e5 PZ |
597 | return ret; |
598 | } | |
599 | } | |
600 | ||
601 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
17b5001b | 602 | base = devm_ioremap_resource(dev, res); |
9b43b56f LN |
603 | if (IS_ERR(base)) |
604 | return PTR_ERR(base); | |
fcbc51e5 PZ |
605 | |
606 | tve_regmap_config.lock_arg = tve; | |
17b5001b | 607 | tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, |
fcbc51e5 PZ |
608 | &tve_regmap_config); |
609 | if (IS_ERR(tve->regmap)) { | |
17b5001b | 610 | dev_err(dev, "failed to init regmap: %ld\n", |
fcbc51e5 PZ |
611 | PTR_ERR(tve->regmap)); |
612 | return PTR_ERR(tve->regmap); | |
613 | } | |
614 | ||
615 | irq = platform_get_irq(pdev, 0); | |
616 | if (irq < 0) { | |
17b5001b | 617 | dev_err(dev, "failed to get irq\n"); |
fcbc51e5 PZ |
618 | return irq; |
619 | } | |
620 | ||
17b5001b | 621 | ret = devm_request_threaded_irq(dev, irq, NULL, |
fcbc51e5 PZ |
622 | imx_tve_irq_handler, IRQF_ONESHOT, |
623 | "imx-tve", tve); | |
624 | if (ret < 0) { | |
17b5001b | 625 | dev_err(dev, "failed to request irq: %d\n", ret); |
fcbc51e5 PZ |
626 | return ret; |
627 | } | |
628 | ||
17b5001b | 629 | tve->dac_reg = devm_regulator_get(dev, "dac"); |
fcbc51e5 | 630 | if (!IS_ERR(tve->dac_reg)) { |
deb65870 FE |
631 | ret = regulator_set_voltage(tve->dac_reg, 2750000, 2750000); |
632 | if (ret) | |
633 | return ret; | |
c7b0cf3e FE |
634 | ret = regulator_enable(tve->dac_reg); |
635 | if (ret) | |
636 | return ret; | |
fcbc51e5 PZ |
637 | } |
638 | ||
17b5001b | 639 | tve->clk = devm_clk_get(dev, "tve"); |
fcbc51e5 | 640 | if (IS_ERR(tve->clk)) { |
17b5001b | 641 | dev_err(dev, "failed to get high speed tve clock: %ld\n", |
fcbc51e5 PZ |
642 | PTR_ERR(tve->clk)); |
643 | return PTR_ERR(tve->clk); | |
644 | } | |
645 | ||
646 | /* this is the IPU DI clock input selector, can be parented to tve_di */ | |
17b5001b | 647 | tve->di_sel_clk = devm_clk_get(dev, "di_sel"); |
fcbc51e5 | 648 | if (IS_ERR(tve->di_sel_clk)) { |
17b5001b | 649 | dev_err(dev, "failed to get ipu di mux clock: %ld\n", |
fcbc51e5 PZ |
650 | PTR_ERR(tve->di_sel_clk)); |
651 | return PTR_ERR(tve->di_sel_clk); | |
652 | } | |
653 | ||
654 | ret = tve_clk_init(tve, base); | |
655 | if (ret < 0) | |
656 | return ret; | |
657 | ||
658 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
659 | if (ret < 0) { | |
f582d9a8 RK |
660 | dev_err(dev, "failed to read configuration register: %d\n", |
661 | ret); | |
fcbc51e5 PZ |
662 | return ret; |
663 | } | |
664 | if (val != 0x00100000) { | |
17b5001b | 665 | dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); |
fcbc51e5 | 666 | return -ENODEV; |
a22526e4 | 667 | } |
fcbc51e5 PZ |
668 | |
669 | /* disable cable detection for VGA mode */ | |
670 | ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); | |
f555e7ea FE |
671 | if (ret) |
672 | return ret; | |
fcbc51e5 | 673 | |
1b3f7675 | 674 | ret = imx_tve_register(drm, tve); |
fcbc51e5 PZ |
675 | if (ret) |
676 | return ret; | |
677 | ||
17b5001b | 678 | dev_set_drvdata(dev, tve); |
fcbc51e5 PZ |
679 | |
680 | return 0; | |
681 | } | |
682 | ||
17b5001b RK |
683 | static void imx_tve_unbind(struct device *dev, struct device *master, |
684 | void *data) | |
fcbc51e5 | 685 | { |
17b5001b | 686 | struct imx_tve *tve = dev_get_drvdata(dev); |
fcbc51e5 | 687 | |
1b3f7675 | 688 | tve->connector.funcs->destroy(&tve->connector); |
49f98bc4 | 689 | tve->encoder.funcs->destroy(&tve->encoder); |
fcbc51e5 PZ |
690 | |
691 | if (!IS_ERR(tve->dac_reg)) | |
692 | regulator_disable(tve->dac_reg); | |
17b5001b | 693 | } |
fcbc51e5 | 694 | |
17b5001b RK |
695 | static const struct component_ops imx_tve_ops = { |
696 | .bind = imx_tve_bind, | |
697 | .unbind = imx_tve_unbind, | |
698 | }; | |
699 | ||
700 | static int imx_tve_probe(struct platform_device *pdev) | |
701 | { | |
702 | return component_add(&pdev->dev, &imx_tve_ops); | |
703 | } | |
704 | ||
705 | static int imx_tve_remove(struct platform_device *pdev) | |
706 | { | |
707 | component_del(&pdev->dev, &imx_tve_ops); | |
fcbc51e5 PZ |
708 | return 0; |
709 | } | |
710 | ||
711 | static const struct of_device_id imx_tve_dt_ids[] = { | |
712 | { .compatible = "fsl,imx53-tve", }, | |
713 | { /* sentinel */ } | |
714 | }; | |
5e4789d3 | 715 | MODULE_DEVICE_TABLE(of, imx_tve_dt_ids); |
fcbc51e5 PZ |
716 | |
717 | static struct platform_driver imx_tve_driver = { | |
718 | .probe = imx_tve_probe, | |
719 | .remove = imx_tve_remove, | |
720 | .driver = { | |
721 | .of_match_table = imx_tve_dt_ids, | |
722 | .name = "imx-tve", | |
fcbc51e5 PZ |
723 | }, |
724 | }; | |
725 | ||
726 | module_platform_driver(imx_tve_driver); | |
727 | ||
728 | MODULE_DESCRIPTION("i.MX Television Encoder driver"); | |
729 | MODULE_AUTHOR("Philipp Zabel, Pengutronix"); | |
730 | MODULE_LICENSE("GPL"); | |
52db752c | 731 | MODULE_ALIAS("platform:imx-tve"); |