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Merge tag 'hsi-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi
[deliverable/linux.git] / drivers / gpu / drm / imx / imx-tve.c
CommitLineData
fcbc51e5
PZ		 1/*
2 * i.MX drm driver - Television Encoder (TVEv2)
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
fcbc51e5
PZ		 14 */
15
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
17b5001b 18#include <linux/component.h>
fcbc51e5 19#include <linux/module.h>
687b81d0 20#include <linux/i2c.h>
fcbc51e5
PZ		 21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/spinlock.h>
24#include <linux/videodev2.h>
25#include <drm/drmP.h>
26#include <drm/drm_fb_helper.h>
27#include <drm/drm_crtc_helper.h>
39b9004d 28#include <video/imx-ipu-v3.h>
fcbc51e5
PZ		 29
30#include "imx-drm.h"
31
32#define TVE_COM_CONF_REG 0x00
33#define TVE_TVDAC0_CONT_REG 0x28
34#define TVE_TVDAC1_CONT_REG 0x2c
35#define TVE_TVDAC2_CONT_REG 0x30
36#define TVE_CD_CONT_REG 0x34
37#define TVE_INT_CONT_REG 0x64
38#define TVE_STAT_REG 0x68
39#define TVE_TST_MODE_REG 0x6c
40#define TVE_MV_CONT_REG 0xdc
41
42/* TVE_COM_CONF_REG */
43#define TVE_SYNC_CH_2_EN BIT(22)
44#define TVE_SYNC_CH_1_EN BIT(21)
45#define TVE_SYNC_CH_0_EN BIT(20)
46#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
47#define TVE_TV_OUT_DISABLE (0x0 << 12)
48#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
49#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
50#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
51#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
52#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
53#define TVE_TV_OUT_YPBPR (0x6 << 12)
54#define TVE_TV_OUT_RGB (0x7 << 12)
55#define TVE_TV_STAND_MASK (0xf << 8)
56#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
57#define TVE_P2I_CONV_EN BIT(7)
58#define TVE_INP_VIDEO_FORM BIT(6)
59#define TVE_INP_YCBCR_422 (0x0 << 6)
60#define TVE_INP_YCBCR_444 (0x1 << 6)
61#define TVE_DATA_SOURCE_MASK (0x3 << 4)
62#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
63#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
64#define TVE_DATA_SOURCE_EXT (0x2 << 4)
65#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
66#define TVE_IPU_CLK_EN_OFS 3
67#define TVE_IPU_CLK_EN BIT(3)
68#define TVE_DAC_SAMP_RATE_OFS 1
69#define TVE_DAC_SAMP_RATE_WIDTH 2
70#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
71#define TVE_DAC_FULL_RATE (0x0 << 1)
72#define TVE_DAC_DIV2_RATE (0x1 << 1)
73#define TVE_DAC_DIV4_RATE (0x2 << 1)
74#define TVE_EN BIT(0)
75
76/* TVE_TVDACx_CONT_REG */
77#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
78
79/* TVE_CD_CONT_REG */
80#define TVE_CD_CH_2_SM_EN BIT(22)
81#define TVE_CD_CH_1_SM_EN BIT(21)
82#define TVE_CD_CH_0_SM_EN BIT(20)
83#define TVE_CD_CH_2_LM_EN BIT(18)
84#define TVE_CD_CH_1_LM_EN BIT(17)
85#define TVE_CD_CH_0_LM_EN BIT(16)
86#define TVE_CD_CH_2_REF_LVL BIT(10)
87#define TVE_CD_CH_1_REF_LVL BIT(9)
88#define TVE_CD_CH_0_REF_LVL BIT(8)
89#define TVE_CD_EN BIT(0)
90
91/* TVE_INT_CONT_REG */
92#define TVE_FRAME_END_IEN BIT(13)
93#define TVE_CD_MON_END_IEN BIT(2)
94#define TVE_CD_SM_IEN BIT(1)
95#define TVE_CD_LM_IEN BIT(0)
96
97/* TVE_TST_MODE_REG */
98#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
99
100#define con_to_tve(x) container_of(x, struct imx_tve, connector)
101#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
102
103enum {
104 TVE_MODE_TVOUT,
105 TVE_MODE_VGA,
106};
107
108struct imx_tve {
109 struct drm_connector connector;
fcbc51e5 110 struct drm_encoder encoder;
fcbc51e5 111 struct device *dev;
fcbc51e5
PZ		 112 spinlock_t lock; /* register lock */
113 bool enabled;
114 int mode;
115
116 struct regmap *regmap;
117 struct regulator *dac_reg;
118 struct i2c_adapter *ddc;
119 struct clk *clk;
120 struct clk *di_sel_clk;
121 struct clk_hw clk_hw_di;
122 struct clk *di_clk;
123 int vsync_pin;
124 int hsync_pin;
125};
126
127static void tve_lock(void *__tve)
5d78bf80 128__acquires(&tve->lock)
fcbc51e5
PZ		 129{
130 struct imx_tve *tve = __tve;
63bc5164 131
fcbc51e5
PZ		 132 spin_lock(&tve->lock);
133}
134
135static void tve_unlock(void *__tve)
5d78bf80 136__releases(&tve->lock)
fcbc51e5
PZ		 137{
138 struct imx_tve *tve = __tve;
63bc5164 139
fcbc51e5
PZ		 140 spin_unlock(&tve->lock);
141}
142
143static void tve_enable(struct imx_tve *tve)
144{
fcbc51e5
PZ		 145 int ret;
146
fcbc51e5 147 if (!tve->enabled) {
89bc5be7 148 tve->enabled = true;
fcbc51e5
PZ		 149 clk_prepare_enable(tve->clk);
150 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
151 TVE_IPU_CLK_EN | TVE_EN,
152 TVE_IPU_CLK_EN | TVE_EN);
153 }
154
155 /* clear interrupt status register */
156 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
157
158 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
159 if (tve->mode == TVE_MODE_VGA)
160 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
161 else
162 regmap_write(tve->regmap, TVE_INT_CONT_REG,
89911e58
AW		 163 TVE_CD_SM_IEN |
164 TVE_CD_LM_IEN |
165 TVE_CD_MON_END_IEN);
fcbc51e5
PZ		 166}
167
168static void tve_disable(struct imx_tve *tve)
169{
fcbc51e5
PZ		 170 int ret;
171
fcbc51e5 172 if (tve->enabled) {
89bc5be7 173 tve->enabled = false;
fcbc51e5
PZ		 174 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
175 TVE_IPU_CLK_EN | TVE_EN, 0);
176 clk_disable_unprepare(tve->clk);
177 }
fcbc51e5
PZ		 178}
179
180static int tve_setup_tvout(struct imx_tve *tve)
181{
182 return -ENOTSUPP;
183}
184
185static int tve_setup_vga(struct imx_tve *tve)
186{
187 unsigned int mask;
188 unsigned int val;
189 int ret;
190
191 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
192 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
193 TVE_TVDAC_GAIN_MASK, 0x0a);
f555e7ea
FE		 194 if (ret)
195 return ret;
196
fcbc51e5
PZ		 197 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
198 TVE_TVDAC_GAIN_MASK, 0x0a);
f555e7ea
FE		 199 if (ret)
200 return ret;
201
fcbc51e5
PZ		 202 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
203 TVE_TVDAC_GAIN_MASK, 0x0a);
f555e7ea
FE		 204 if (ret)
205 return ret;
fcbc51e5
PZ		 206
207 /* set configuration register */
208 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
209 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
210 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
211 val |= TVE_TV_STAND_HD_1080P30 | 0;
212 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
213 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
214 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
f555e7ea 215 if (ret)
fcbc51e5 216 return ret;
fcbc51e5
PZ		 217
218 /* set test mode (as documented) */
f555e7ea 219 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
fcbc51e5 220 TVE_TVDAC_TEST_MODE_MASK, 1);
fcbc51e5
PZ		 221}
222
223static enum drm_connector_status imx_tve_connector_detect(
224 struct drm_connector *connector, bool force)
225{
226 return connector_status_connected;
227}
228
fcbc51e5
PZ		 229static int imx_tve_connector_get_modes(struct drm_connector *connector)
230{
231 struct imx_tve *tve = con_to_tve(connector);
232 struct edid *edid;
233 int ret = 0;
234
235 if (!tve->ddc)
236 return 0;
237
238 edid = drm_get_edid(connector, tve->ddc);
239 if (edid) {
240 drm_mode_connector_update_edid_property(connector, edid);
241 ret = drm_add_edid_modes(connector, edid);
242 kfree(edid);
243 }
244
245 return ret;
246}
247
248static int imx_tve_connector_mode_valid(struct drm_connector *connector,
249 struct drm_display_mode *mode)
250{
251 struct imx_tve *tve = con_to_tve(connector);
252 unsigned long rate;
baa68c4b 253
fcbc51e5
PZ		 254 /* pixel clock with 2x oversampling */
255 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
256 if (rate == mode->clock)
257 return MODE_OK;
258
259 /* pixel clock without oversampling */
260 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
261 if (rate == mode->clock)
262 return MODE_OK;
263
264 dev_warn(tve->dev, "ignoring mode %dx%d\n",
265 mode->hdisplay, mode->vdisplay);
266
267 return MODE_BAD;
268}
269
270static struct drm_encoder *imx_tve_connector_best_encoder(
271 struct drm_connector *connector)
272{
273 struct imx_tve *tve = con_to_tve(connector);
274
275 return &tve->encoder;
276}
277
278static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
279{
280 struct imx_tve *tve = enc_to_tve(encoder);
281 int ret;
282
283 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
284 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
285 if (ret < 0)
286 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
287}
288
fcbc51e5
PZ		 289static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
290{
291 struct imx_tve *tve = enc_to_tve(encoder);
292
293 tve_disable(tve);
294
295 switch (tve->mode) {
296 case TVE_MODE_VGA:
4ed094fd
PZ		 297 imx_drm_set_bus_config(encoder, MEDIA_BUS_FMT_GBR888_1X24,
298 tve->hsync_pin, tve->vsync_pin,
299 DRM_BUS_FLAG_DE_HIGH |
300 DRM_BUS_FLAG_PIXDATA_NEGEDGE);
fcbc51e5
PZ		 301 break;
302 case TVE_MODE_TVOUT:
2872c807 303 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24);
fcbc51e5
PZ		 304 break;
305 }
306}
307
308static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
eb10d635
SL		 309 struct drm_display_mode *orig_mode,
310 struct drm_display_mode *mode)
fcbc51e5
PZ		 311{
312 struct imx_tve *tve = enc_to_tve(encoder);
313 unsigned long rounded_rate;
314 unsigned long rate;
315 int div = 1;
316 int ret;
317
318 /*
319 * FIXME
320 * we should try 4k * mode->clock first,
321 * and enable 4x oversampling for lower resolutions
322 */
323 rate = 2000UL * mode->clock;
324 clk_set_rate(tve->clk, rate);
325 rounded_rate = clk_get_rate(tve->clk);
326 if (rounded_rate >= rate)
327 div = 2;
328 clk_set_rate(tve->di_clk, rounded_rate / div);
329
330 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
331 if (ret < 0) {
332 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
333 ret);
334 }
335
336 if (tve->mode == TVE_MODE_VGA)
f555e7ea 337 ret = tve_setup_vga(tve);
fcbc51e5 338 else
f555e7ea
FE		 339 ret = tve_setup_tvout(tve);
340 if (ret)
341 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
fcbc51e5
PZ		 342}
343
344static void imx_tve_encoder_commit(struct drm_encoder *encoder)
345{
346 struct imx_tve *tve = enc_to_tve(encoder);
347
348 tve_enable(tve);
349}
350
351static void imx_tve_encoder_disable(struct drm_encoder *encoder)
352{
353 struct imx_tve *tve = enc_to_tve(encoder);
354
355 tve_disable(tve);
356}
357
7ae847dd 358static const struct drm_connector_funcs imx_tve_connector_funcs = {
fcbc51e5
PZ		 359 .dpms = drm_helper_connector_dpms,
360 .fill_modes = drm_helper_probe_single_connector_modes,
361 .detect = imx_tve_connector_detect,
1b3f7675 362 .destroy = imx_drm_connector_destroy,
fcbc51e5
PZ		 363};
364
7ae847dd 365static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
fcbc51e5
PZ		 366 .get_modes = imx_tve_connector_get_modes,
367 .best_encoder = imx_tve_connector_best_encoder,
368 .mode_valid = imx_tve_connector_mode_valid,
369};
370
7ae847dd 371static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
1b3f7675 372 .destroy = imx_drm_encoder_destroy,
fcbc51e5
PZ		 373};
374
7ae847dd 375static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
fcbc51e5 376 .dpms = imx_tve_encoder_dpms,
fcbc51e5
PZ		 377 .prepare = imx_tve_encoder_prepare,
378 .mode_set = imx_tve_encoder_mode_set,
379 .commit = imx_tve_encoder_commit,
380 .disable = imx_tve_encoder_disable,
381};
382
383static irqreturn_t imx_tve_irq_handler(int irq, void *data)
384{
385 struct imx_tve *tve = data;
386 unsigned int val;
387
388 regmap_read(tve->regmap, TVE_STAT_REG, &val);
389
390 /* clear interrupt status register */
391 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
392
393 return IRQ_HANDLED;
394}
395
396static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
397 unsigned long parent_rate)
398{
399 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
400 unsigned int val;
401 int ret;
402
403 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
404 if (ret < 0)
405 return 0;
406
407 switch (val & TVE_DAC_SAMP_RATE_MASK) {
408 case TVE_DAC_DIV4_RATE:
409 return parent_rate / 4;
410 case TVE_DAC_DIV2_RATE:
411 return parent_rate / 2;
412 case TVE_DAC_FULL_RATE:
413 default:
414 return parent_rate;
415 }
416
417 return 0;
418}
419
420static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long *prate)
422{
423 unsigned long div;
424
425 div = *prate / rate;
426 if (div >= 4)
427 return *prate / 4;
428 else if (div >= 2)
429 return *prate / 2;
7557b6e1 430 return *prate;
fcbc51e5
PZ		 431}
432
433static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
434 unsigned long parent_rate)
435{
436 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
437 unsigned long div;
438 u32 val;
439 int ret;
440
441 div = parent_rate / rate;
442 if (div >= 4)
443 val = TVE_DAC_DIV4_RATE;
444 else if (div >= 2)
445 val = TVE_DAC_DIV2_RATE;
446 else
447 val = TVE_DAC_FULL_RATE;
448
89911e58
AW		 449 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
450 TVE_DAC_SAMP_RATE_MASK, val);
451
fcbc51e5
PZ		 452 if (ret < 0) {
453 dev_err(tve->dev, "failed to set divider: %d\n", ret);
454 return ret;
455 }
456
457 return 0;
458}
459
460static struct clk_ops clk_tve_di_ops = {
461 .round_rate = clk_tve_di_round_rate,
462 .set_rate = clk_tve_di_set_rate,
463 .recalc_rate = clk_tve_di_recalc_rate,
464};
465
466static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
467{
468 const char *tve_di_parent[1];
469 struct clk_init_data init = {
470 .name = "tve_di",
471 .ops = &clk_tve_di_ops,
472 .num_parents = 1,
473 .flags = 0,
474 };
475
476 tve_di_parent[0] = __clk_get_name(tve->clk);
477 init.parent_names = (const char **)&tve_di_parent;
478
479 tve->clk_hw_di.init = &init;
480 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
481 if (IS_ERR(tve->di_clk)) {
482 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
483 PTR_ERR(tve->di_clk));
484 return PTR_ERR(tve->di_clk);
485 }
486
487 return 0;
488}
489
1b3f7675 490static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
fcbc51e5 491{
f2d66aad 492 int encoder_type;
fcbc51e5
PZ		 493 int ret;
494
f2d66aad
RK		 495 encoder_type = tve->mode == TVE_MODE_VGA ?
496 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
497
1b3f7675
RK		 498 ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
499 tve->dev->of_node);
500 if (ret)
501 return ret;
fcbc51e5
PZ		 502
503 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
1b3f7675 504 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
13a3d91f 505 encoder_type, NULL);
fcbc51e5
PZ		 506
507 drm_connector_helper_add(&tve->connector,
508 &imx_tve_connector_helper_funcs);
1b3f7675
RK		 509 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
510 DRM_MODE_CONNECTOR_VGA);
fcbc51e5
PZ		 511
512 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
513
514 return 0;
515}
516
517static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
518{
519 return (reg % 4 == 0) && (reg <= 0xdc);
520}
521
522static struct regmap_config tve_regmap_config = {
523 .reg_bits = 32,
524 .val_bits = 32,
525 .reg_stride = 4,
526
527 .readable_reg = imx_tve_readable_reg,
528
529 .lock = tve_lock,
530 .unlock = tve_unlock,
531
532 .max_register = 0xdc,
533};
534
8684ba72 535static const char * const imx_tve_modes[] = {
fcbc51e5
PZ		 536 [TVE_MODE_TVOUT] = "tvout",
537 [TVE_MODE_VGA] = "vga",
538};
539
7fc6cb28 540static const int of_get_tve_mode(struct device_node *np)
fcbc51e5
PZ		 541{
542 const char *bm;
543 int ret, i;
544
545 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
546 if (ret < 0)
547 return ret;
548
549 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
550 if (!strcasecmp(bm, imx_tve_modes[i]))
551 return i;
552
553 return -EINVAL;
554}
555
17b5001b 556static int imx_tve_bind(struct device *dev, struct device *master, void *data)
fcbc51e5 557{
17b5001b 558 struct platform_device *pdev = to_platform_device(dev);
1b3f7675 559 struct drm_device *drm = data;
17b5001b 560 struct device_node *np = dev->of_node;
fcbc51e5
PZ		 561 struct device_node *ddc_node;
562 struct imx_tve *tve;
563 struct resource *res;
564 void __iomem *base;
565 unsigned int val;
566 int irq;
567 int ret;
568
17b5001b 569 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
fcbc51e5
PZ		 570 if (!tve)
571 return -ENOMEM;
572
17b5001b 573 tve->dev = dev;
fcbc51e5 574 spin_lock_init(&tve->lock);
fcbc51e5 575
a3fe9641 576 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
fcbc51e5
PZ		 577 if (ddc_node) {
578 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
579 of_node_put(ddc_node);
580 }
581
582 tve->mode = of_get_tve_mode(np);
583 if (tve->mode != TVE_MODE_VGA) {
17b5001b 584 dev_err(dev, "only VGA mode supported, currently\n");
fcbc51e5
PZ		 585 return -EINVAL;
586 }
587
588 if (tve->mode == TVE_MODE_VGA) {
89911e58
AW		 589 ret = of_property_read_u32(np, "fsl,hsync-pin",
590 &tve->hsync_pin);
591
fcbc51e5 592 if (ret < 0) {
17b5001b 593 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 594 return ret;
595 }
596
89911e58
AW		 597 ret |= of_property_read_u32(np, "fsl,vsync-pin",
598 &tve->vsync_pin);
599
fcbc51e5 600 if (ret < 0) {
17b5001b 601 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 602 return ret;
603 }
604 }
605
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b 607 base = devm_ioremap_resource(dev, res);
9b43b56f
LN		 608 if (IS_ERR(base))
609 return PTR_ERR(base);
fcbc51e5
PZ		 610
611 tve_regmap_config.lock_arg = tve;
17b5001b 612 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
fcbc51e5
PZ		 613 &tve_regmap_config);
614 if (IS_ERR(tve->regmap)) {
17b5001b 615 dev_err(dev, "failed to init regmap: %ld\n",
fcbc51e5
PZ		 616 PTR_ERR(tve->regmap));
617 return PTR_ERR(tve->regmap);
618 }
619
620 irq = platform_get_irq(pdev, 0);
621 if (irq < 0) {
17b5001b 622 dev_err(dev, "failed to get irq\n");
fcbc51e5
PZ		 623 return irq;
624 }
625
17b5001b 626 ret = devm_request_threaded_irq(dev, irq, NULL,
fcbc51e5
PZ		 627 imx_tve_irq_handler, IRQF_ONESHOT,
628 "imx-tve", tve);
629 if (ret < 0) {
17b5001b 630 dev_err(dev, "failed to request irq: %d\n", ret);
fcbc51e5
PZ		 631 return ret;
632 }
633
17b5001b 634 tve->dac_reg = devm_regulator_get(dev, "dac");
fcbc51e5
PZ		 635 if (!IS_ERR(tve->dac_reg)) {
636 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
c7b0cf3e
FE		 637 ret = regulator_enable(tve->dac_reg);
638 if (ret)
639 return ret;
fcbc51e5
PZ		 640 }
641
17b5001b 642 tve->clk = devm_clk_get(dev, "tve");
fcbc51e5 643 if (IS_ERR(tve->clk)) {
17b5001b 644 dev_err(dev, "failed to get high speed tve clock: %ld\n",
fcbc51e5
PZ		 645 PTR_ERR(tve->clk));
646 return PTR_ERR(tve->clk);
647 }
648
649 /* this is the IPU DI clock input selector, can be parented to tve_di */
17b5001b 650 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
fcbc51e5 651 if (IS_ERR(tve->di_sel_clk)) {
17b5001b 652 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
fcbc51e5
PZ		 653 PTR_ERR(tve->di_sel_clk));
654 return PTR_ERR(tve->di_sel_clk);
655 }
656
657 ret = tve_clk_init(tve, base);
658 if (ret < 0)
659 return ret;
660
661 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
662 if (ret < 0) {
f582d9a8
RK		 663 dev_err(dev, "failed to read configuration register: %d\n",
664 ret);
fcbc51e5
PZ		 665 return ret;
666 }
667 if (val != 0x00100000) {
17b5001b 668 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
fcbc51e5 669 return -ENODEV;
a22526e4 670 }
fcbc51e5
PZ		 671
672 /* disable cable detection for VGA mode */
673 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
f555e7ea
FE		 674 if (ret)
675 return ret;
fcbc51e5 676
1b3f7675 677 ret = imx_tve_register(drm, tve);
fcbc51e5
PZ		 678 if (ret)
679 return ret;
680
17b5001b 681 dev_set_drvdata(dev, tve);
fcbc51e5
PZ		 682
683 return 0;
684}
685
17b5001b
RK		 686static void imx_tve_unbind(struct device *dev, struct device *master,
687 void *data)
fcbc51e5 688{
17b5001b 689 struct imx_tve *tve = dev_get_drvdata(dev);
fcbc51e5 690
1b3f7675
RK		 691 tve->connector.funcs->destroy(&tve->connector);
692 tve->encoder.funcs->destroy(&tve->encoder);
fcbc51e5
PZ		 693
694 if (!IS_ERR(tve->dac_reg))
695 regulator_disable(tve->dac_reg);
17b5001b 696}
fcbc51e5 697
17b5001b
RK		 698static const struct component_ops imx_tve_ops = {
699 .bind = imx_tve_bind,
700 .unbind = imx_tve_unbind,
701};
702
703static int imx_tve_probe(struct platform_device *pdev)
704{
705 return component_add(&pdev->dev, &imx_tve_ops);
706}
707
708static int imx_tve_remove(struct platform_device *pdev)
709{
710 component_del(&pdev->dev, &imx_tve_ops);
fcbc51e5
PZ		 711 return 0;
712}
713
714static const struct of_device_id imx_tve_dt_ids[] = {
715 { .compatible = "fsl,imx53-tve", },
716 { /* sentinel */ }
717};
5e4789d3 718MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
fcbc51e5
PZ		 719
720static struct platform_driver imx_tve_driver = {
721 .probe = imx_tve_probe,
722 .remove = imx_tve_remove,
723 .driver = {
724 .of_match_table = imx_tve_dt_ids,
725 .name = "imx-tve",
fcbc51e5
PZ		 726 },
727};
728
729module_platform_driver(imx_tve_driver);
730
731MODULE_DESCRIPTION("i.MX Television Encoder driver");
732MODULE_AUTHOR("Philipp Zabel, Pengutronix");
733MODULE_LICENSE("GPL");
52db752c 734MODULE_ALIAS("platform:imx-tve");
Linux kernel - Deliverables
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