[deliverable/linux.git] / drivers / gpu / drm / imx / imx-tve.c

/*
 * i.MX drm driver - Television Encoder (TVEv2)
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spinlock.h>
#include <linux/videodev2.h>
#include <drm/drmP.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_crtc_helper.h>
#include <video/imx-ipu-v3.h>

#include "imx-drm.h"

#define TVE_COM_CONF_REG	0x00
#define TVE_TVDAC0_CONT_REG	0x28
#define TVE_TVDAC1_CONT_REG	0x2c
#define TVE_TVDAC2_CONT_REG	0x30
#define TVE_CD_CONT_REG		0x34
#define TVE_INT_CONT_REG	0x64
#define TVE_STAT_REG		0x68
#define TVE_TST_MODE_REG	0x6c
#define TVE_MV_CONT_REG		0xdc

/* TVE_COM_CONF_REG */
#define TVE_SYNC_CH_2_EN	BIT(22)
#define TVE_SYNC_CH_1_EN	BIT(21)
#define TVE_SYNC_CH_0_EN	BIT(20)
#define TVE_TV_OUT_MODE_MASK	(0x7 << 12)
#define TVE_TV_OUT_DISABLE	(0x0 << 12)
#define TVE_TV_OUT_CVBS_0	(0x1 << 12)
#define TVE_TV_OUT_CVBS_2	(0x2 << 12)
#define TVE_TV_OUT_CVBS_0_2	(0x3 << 12)
#define TVE_TV_OUT_SVIDEO_0_1	(0x4 << 12)
#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2	(0x5 << 12)
#define TVE_TV_OUT_YPBPR	(0x6 << 12)
#define TVE_TV_OUT_RGB		(0x7 << 12)
#define TVE_TV_STAND_MASK	(0xf << 8)
#define TVE_TV_STAND_HD_1080P30	(0xc << 8)
#define TVE_P2I_CONV_EN		BIT(7)
#define TVE_INP_VIDEO_FORM	BIT(6)
#define TVE_INP_YCBCR_422	(0x0 << 6)
#define TVE_INP_YCBCR_444	(0x1 << 6)
#define TVE_DATA_SOURCE_MASK	(0x3 << 4)
#define TVE_DATA_SOURCE_BUS1	(0x0 << 4)
#define TVE_DATA_SOURCE_BUS2	(0x1 << 4)
#define TVE_DATA_SOURCE_EXT	(0x2 << 4)
#define TVE_DATA_SOURCE_TESTGEN	(0x3 << 4)
#define TVE_IPU_CLK_EN_OFS	3
#define TVE_IPU_CLK_EN		BIT(3)
#define TVE_DAC_SAMP_RATE_OFS	1
#define TVE_DAC_SAMP_RATE_WIDTH	2
#define TVE_DAC_SAMP_RATE_MASK	(0x3 << 1)
#define TVE_DAC_FULL_RATE	(0x0 << 1)
#define TVE_DAC_DIV2_RATE	(0x1 << 1)
#define TVE_DAC_DIV4_RATE	(0x2 << 1)
#define TVE_EN			BIT(0)

/* TVE_TVDACx_CONT_REG */
#define TVE_TVDAC_GAIN_MASK	(0x3f << 0)

/* TVE_CD_CONT_REG */
#define TVE_CD_CH_2_SM_EN	BIT(22)
#define TVE_CD_CH_1_SM_EN	BIT(21)
#define TVE_CD_CH_0_SM_EN	BIT(20)
#define TVE_CD_CH_2_LM_EN	BIT(18)
#define TVE_CD_CH_1_LM_EN	BIT(17)
#define TVE_CD_CH_0_LM_EN	BIT(16)
#define TVE_CD_CH_2_REF_LVL	BIT(10)
#define TVE_CD_CH_1_REF_LVL	BIT(9)
#define TVE_CD_CH_0_REF_LVL	BIT(8)
#define TVE_CD_EN		BIT(0)

/* TVE_INT_CONT_REG */
#define TVE_FRAME_END_IEN	BIT(13)
#define TVE_CD_MON_END_IEN	BIT(2)
#define TVE_CD_SM_IEN		BIT(1)
#define TVE_CD_LM_IEN		BIT(0)

/* TVE_TST_MODE_REG */
#define TVE_TVDAC_TEST_MODE_MASK	(0x7 << 0)

#define con_to_tve(x) container_of(x, struct imx_tve, connector)
#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)

enum {
	TVE_MODE_TVOUT,
	TVE_MODE_VGA,
};

struct imx_tve {
	struct drm_connector connector;
	struct drm_encoder encoder;
	struct device *dev;
	spinlock_t lock;	/* register lock */
	bool enabled;
	int mode;

	struct regmap *regmap;
	struct regulator *dac_reg;
	struct i2c_adapter *ddc;
	struct clk *clk;
	struct clk *di_sel_clk;
	struct clk_hw clk_hw_di;
	struct clk *di_clk;
	int vsync_pin;
	int hsync_pin;
};

static void tve_lock(void *__tve)
__acquires(&tve->lock)
{
	struct imx_tve *tve = __tve;

	spin_lock(&tve->lock);
}

static void tve_unlock(void *__tve)
__releases(&tve->lock)
{
	struct imx_tve *tve = __tve;

	spin_unlock(&tve->lock);
}

static void tve_enable(struct imx_tve *tve)
{
	int ret;

	if (!tve->enabled) {
		tve->enabled = true;
		clk_prepare_enable(tve->clk);
		ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
					 TVE_IPU_CLK_EN | TVE_EN,
					 TVE_IPU_CLK_EN | TVE_EN);
	}

	/* clear interrupt status register */
	regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);

	/* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
	if (tve->mode == TVE_MODE_VGA)
		regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
	else
		regmap_write(tve->regmap, TVE_INT_CONT_REG,
			     TVE_CD_SM_IEN |
			     TVE_CD_LM_IEN |
			     TVE_CD_MON_END_IEN);
}

static void tve_disable(struct imx_tve *tve)
{
	int ret;

	if (tve->enabled) {
		tve->enabled = false;
		ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
					 TVE_IPU_CLK_EN | TVE_EN, 0);
		clk_disable_unprepare(tve->clk);
	}
}

static int tve_setup_tvout(struct imx_tve *tve)
{
	return -ENOTSUPP;
}

static int tve_setup_vga(struct imx_tve *tve)
{
	unsigned int mask;
	unsigned int val;
	int ret;

	/* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
	ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
				 TVE_TVDAC_GAIN_MASK, 0x0a);
	ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
				 TVE_TVDAC_GAIN_MASK, 0x0a);
	ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
				 TVE_TVDAC_GAIN_MASK, 0x0a);

	/* set configuration register */
	mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
	val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
	mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
	val  |= TVE_TV_STAND_HD_1080P30 | 0;
	mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
	val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
	if (ret < 0) {
		dev_err(tve->dev, "failed to set configuration: %d\n", ret);
		return ret;
	}

	/* set test mode (as documented) */
	ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
				 TVE_TVDAC_TEST_MODE_MASK, 1);

	return 0;
}

static enum drm_connector_status imx_tve_connector_detect(
				struct drm_connector *connector, bool force)
{
	return connector_status_connected;
}

static int imx_tve_connector_get_modes(struct drm_connector *connector)
{
	struct imx_tve *tve = con_to_tve(connector);
	struct edid *edid;
	int ret = 0;

	if (!tve->ddc)
		return 0;

	edid = drm_get_edid(connector, tve->ddc);
	if (edid) {
		drm_mode_connector_update_edid_property(connector, edid);
		ret = drm_add_edid_modes(connector, edid);
		kfree(edid);
	}

	return ret;
}

static int imx_tve_connector_mode_valid(struct drm_connector *connector,
					struct drm_display_mode *mode)
{
	struct imx_tve *tve = con_to_tve(connector);
	unsigned long rate;

	/* pixel clock with 2x oversampling */
	rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
	if (rate == mode->clock)
		return MODE_OK;

	/* pixel clock without oversampling */
	rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
	if (rate == mode->clock)
		return MODE_OK;

	dev_warn(tve->dev, "ignoring mode %dx%d\n",
		 mode->hdisplay, mode->vdisplay);

	return MODE_BAD;
}

static struct drm_encoder *imx_tve_connector_best_encoder(
		struct drm_connector *connector)
{
	struct imx_tve *tve = con_to_tve(connector);

	return &tve->encoder;
}

static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
{
	struct imx_tve *tve = enc_to_tve(encoder);
	int ret;

	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
				 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
	if (ret < 0)
		dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
}

static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
				       const struct drm_display_mode *mode,
				       struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
{
	struct imx_tve *tve = enc_to_tve(encoder);

	tve_disable(tve);

	switch (tve->mode) {
	case TVE_MODE_VGA:
		imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
				tve->hsync_pin, tve->vsync_pin);
		break;
	case TVE_MODE_TVOUT:
		imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
		break;
	}
}

static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
				     struct drm_display_mode *mode,
				     struct drm_display_mode *adjusted_mode)
{
	struct imx_tve *tve = enc_to_tve(encoder);
	unsigned long rounded_rate;
	unsigned long rate;
	int div = 1;
	int ret;

	/*
	 * FIXME
	 * we should try 4k * mode->clock first,
	 * and enable 4x oversampling for lower resolutions
	 */
	rate = 2000UL * mode->clock;
	clk_set_rate(tve->clk, rate);
	rounded_rate = clk_get_rate(tve->clk);
	if (rounded_rate >= rate)
		div = 2;
	clk_set_rate(tve->di_clk, rounded_rate / div);

	ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
	if (ret < 0) {
		dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
			ret);
	}

	if (tve->mode == TVE_MODE_VGA)
		tve_setup_vga(tve);
	else
		tve_setup_tvout(tve);
}

static void imx_tve_encoder_commit(struct drm_encoder *encoder)
{
	struct imx_tve *tve = enc_to_tve(encoder);

	tve_enable(tve);
}

static void imx_tve_encoder_disable(struct drm_encoder *encoder)
{
	struct imx_tve *tve = enc_to_tve(encoder);

	tve_disable(tve);
}

static struct drm_connector_funcs imx_tve_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.detect = imx_tve_connector_detect,
	.destroy = imx_drm_connector_destroy,
};

static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
	.get_modes = imx_tve_connector_get_modes,
	.best_encoder = imx_tve_connector_best_encoder,
	.mode_valid = imx_tve_connector_mode_valid,
};

static struct drm_encoder_funcs imx_tve_encoder_funcs = {
	.destroy = imx_drm_encoder_destroy,
};

static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
	.dpms = imx_tve_encoder_dpms,
	.mode_fixup = imx_tve_encoder_mode_fixup,
	.prepare = imx_tve_encoder_prepare,
	.mode_set = imx_tve_encoder_mode_set,
	.commit = imx_tve_encoder_commit,
	.disable = imx_tve_encoder_disable,
};

static irqreturn_t imx_tve_irq_handler(int irq, void *data)
{
	struct imx_tve *tve = data;
	unsigned int val;

	regmap_read(tve->regmap, TVE_STAT_REG, &val);

	/* clear interrupt status register */
	regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);

	return IRQ_HANDLED;
}

static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{
	struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
	unsigned int val;
	int ret;

	ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
	if (ret < 0)
		return 0;

	switch (val & TVE_DAC_SAMP_RATE_MASK) {
	case TVE_DAC_DIV4_RATE:
		return parent_rate / 4;
	case TVE_DAC_DIV2_RATE:
		return parent_rate / 2;
	case TVE_DAC_FULL_RATE:
	default:
		return parent_rate;
	}

	return 0;
}

static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
				  unsigned long *prate)
{
	unsigned long div;

	div = *prate / rate;
	if (div >= 4)
		return *prate / 4;
	else if (div >= 2)
		return *prate / 2;
	return *prate;
}

static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long parent_rate)
{
	struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
	unsigned long div;
	u32 val;
	int ret;

	div = parent_rate / rate;
	if (div >= 4)
		val = TVE_DAC_DIV4_RATE;
	else if (div >= 2)
		val = TVE_DAC_DIV2_RATE;
	else
		val = TVE_DAC_FULL_RATE;

	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
				 TVE_DAC_SAMP_RATE_MASK, val);

	if (ret < 0) {
		dev_err(tve->dev, "failed to set divider: %d\n", ret);
		return ret;
	}

	return 0;
}

static struct clk_ops clk_tve_di_ops = {
	.round_rate = clk_tve_di_round_rate,
	.set_rate = clk_tve_di_set_rate,
	.recalc_rate = clk_tve_di_recalc_rate,
};

static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
{
	const char *tve_di_parent[1];
	struct clk_init_data init = {
		.name = "tve_di",
		.ops = &clk_tve_di_ops,
		.num_parents = 1,
		.flags = 0,
	};

	tve_di_parent[0] = __clk_get_name(tve->clk);
	init.parent_names = (const char **)&tve_di_parent;

	tve->clk_hw_di.init = &init;
	tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
	if (IS_ERR(tve->di_clk)) {
		dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
			PTR_ERR(tve->di_clk));
		return PTR_ERR(tve->di_clk);
	}

	return 0;
}

static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
{
	int encoder_type;
	int ret;

	encoder_type = tve->mode == TVE_MODE_VGA ?
				DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;

	ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
				       tve->dev->of_node);
	if (ret)
		return ret;

	drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
	drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
			 encoder_type);

	drm_connector_helper_add(&tve->connector,
			&imx_tve_connector_helper_funcs);
	drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
			   DRM_MODE_CONNECTOR_VGA);

	drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);

	return 0;
}

static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
{
	return (reg % 4 == 0) && (reg <= 0xdc);
}

static struct regmap_config tve_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,

	.readable_reg = imx_tve_readable_reg,

	.lock = tve_lock,
	.unlock = tve_unlock,

	.max_register = 0xdc,
};

static const char * const imx_tve_modes[] = {
	[TVE_MODE_TVOUT]  = "tvout",
	[TVE_MODE_VGA] = "vga",
};

static const int of_get_tve_mode(struct device_node *np)
{
	const char *bm;
	int ret, i;

	ret = of_property_read_string(np, "fsl,tve-mode", &bm);
	if (ret < 0)
		return ret;

	for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
		if (!strcasecmp(bm, imx_tve_modes[i]))
			return i;

	return -EINVAL;
}

static int imx_tve_bind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct drm_device *drm = data;
	struct device_node *np = dev->of_node;
	struct device_node *ddc_node;
	struct imx_tve *tve;
	struct resource *res;
	void __iomem *base;
	unsigned int val;
	int irq;
	int ret;

	tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
	if (!tve)
		return -ENOMEM;

	tve->dev = dev;
	spin_lock_init(&tve->lock);

	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
	if (ddc_node) {
		tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
		of_node_put(ddc_node);
	}

	tve->mode = of_get_tve_mode(np);
	if (tve->mode != TVE_MODE_VGA) {
		dev_err(dev, "only VGA mode supported, currently\n");
		return -EINVAL;
	}

	if (tve->mode == TVE_MODE_VGA) {
		ret = of_property_read_u32(np, "fsl,hsync-pin",
					   &tve->hsync_pin);

		if (ret < 0) {
			dev_err(dev, "failed to get vsync pin\n");
			return ret;
		}

		ret |= of_property_read_u32(np, "fsl,vsync-pin",
					    &tve->vsync_pin);

		if (ret < 0) {
			dev_err(dev, "failed to get vsync pin\n");
			return ret;
		}
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	tve_regmap_config.lock_arg = tve;
	tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
						&tve_regmap_config);
	if (IS_ERR(tve->regmap)) {
		dev_err(dev, "failed to init regmap: %ld\n",
			PTR_ERR(tve->regmap));
		return PTR_ERR(tve->regmap);
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "failed to get irq\n");
		return irq;
	}

	ret = devm_request_threaded_irq(dev, irq, NULL,
					imx_tve_irq_handler, IRQF_ONESHOT,
					"imx-tve", tve);
	if (ret < 0) {
		dev_err(dev, "failed to request irq: %d\n", ret);
		return ret;
	}

	tve->dac_reg = devm_regulator_get(dev, "dac");
	if (!IS_ERR(tve->dac_reg)) {
		regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
		ret = regulator_enable(tve->dac_reg);
		if (ret)
			return ret;
	}

	tve->clk = devm_clk_get(dev, "tve");
	if (IS_ERR(tve->clk)) {
		dev_err(dev, "failed to get high speed tve clock: %ld\n",
			PTR_ERR(tve->clk));
		return PTR_ERR(tve->clk);
	}

	/* this is the IPU DI clock input selector, can be parented to tve_di */
	tve->di_sel_clk = devm_clk_get(dev, "di_sel");
	if (IS_ERR(tve->di_sel_clk)) {
		dev_err(dev, "failed to get ipu di mux clock: %ld\n",
			PTR_ERR(tve->di_sel_clk));
		return PTR_ERR(tve->di_sel_clk);
	}

	ret = tve_clk_init(tve, base);
	if (ret < 0)
		return ret;

	ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
	if (ret < 0) {
		dev_err(dev, "failed to read configuration register: %d\n",
			ret);
		return ret;
	}
	if (val != 0x00100000) {
		dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
		return -ENODEV;
	}

	/* disable cable detection for VGA mode */
	ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);

	ret = imx_tve_register(drm, tve);
	if (ret)
		return ret;

	dev_set_drvdata(dev, tve);

	return 0;
}

static void imx_tve_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct imx_tve *tve = dev_get_drvdata(dev);

	tve->connector.funcs->destroy(&tve->connector);
	tve->encoder.funcs->destroy(&tve->encoder);

	if (!IS_ERR(tve->dac_reg))
		regulator_disable(tve->dac_reg);
}

static const struct component_ops imx_tve_ops = {
	.bind	= imx_tve_bind,
	.unbind	= imx_tve_unbind,
};

static int imx_tve_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &imx_tve_ops);
}

static int imx_tve_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &imx_tve_ops);
	return 0;
}

static const struct of_device_id imx_tve_dt_ids[] = {
	{ .compatible = "fsl,imx53-tve", },
	{ /* sentinel */ }
};

static struct platform_driver imx_tve_driver = {
	.probe		= imx_tve_probe,
	.remove		= imx_tve_remove,
	.driver		= {
		.of_match_table = imx_tve_dt_ids,
		.name	= "imx-tve",
	},
};

module_platform_driver(imx_tve_driver);

MODULE_DESCRIPTION("i.MX Television Encoder driver");
MODULE_AUTHOR("Philipp Zabel, Pengutronix");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-tve");
Commit	Line	Data
fcbc51e5 PZ	1	/*
	2	* i.MX drm driver - Television Encoder (TVEv2)
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
fcbc51e5 PZ	14	*/
	15
	16	#include <linux/clk.h>
	17	#include <linux/clk-provider.h>
17b5001b	18	#include <linux/component.h>
fcbc51e5	19	#include <linux/module.h>
687b81d0	20	#include <linux/i2c.h>
fcbc51e5 PZ	21	#include <linux/regmap.h>
	22	#include <linux/regulator/consumer.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/videodev2.h>
	25	#include <drm/drmP.h>
	26	#include <drm/drm_fb_helper.h>
	27	#include <drm/drm_crtc_helper.h>
39b9004d	28	#include <video/imx-ipu-v3.h>
fcbc51e5 PZ	29
	30	#include "imx-drm.h"
	31
	32	#define TVE_COM_CONF_REG 0x00
	33	#define TVE_TVDAC0_CONT_REG 0x28
	34	#define TVE_TVDAC1_CONT_REG 0x2c
	35	#define TVE_TVDAC2_CONT_REG 0x30
	36	#define TVE_CD_CONT_REG 0x34
	37	#define TVE_INT_CONT_REG 0x64
	38	#define TVE_STAT_REG 0x68
	39	#define TVE_TST_MODE_REG 0x6c
	40	#define TVE_MV_CONT_REG 0xdc
	41
	42	/* TVE_COM_CONF_REG */
	43	#define TVE_SYNC_CH_2_EN BIT(22)
	44	#define TVE_SYNC_CH_1_EN BIT(21)
	45	#define TVE_SYNC_CH_0_EN BIT(20)
	46	#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
	47	#define TVE_TV_OUT_DISABLE (0x0 << 12)
	48	#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
	49	#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
	50	#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
	51	#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
	52	#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
	53	#define TVE_TV_OUT_YPBPR (0x6 << 12)
	54	#define TVE_TV_OUT_RGB (0x7 << 12)
	55	#define TVE_TV_STAND_MASK (0xf << 8)
	56	#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
	57	#define TVE_P2I_CONV_EN BIT(7)
	58	#define TVE_INP_VIDEO_FORM BIT(6)
	59	#define TVE_INP_YCBCR_422 (0x0 << 6)
	60	#define TVE_INP_YCBCR_444 (0x1 << 6)
	61	#define TVE_DATA_SOURCE_MASK (0x3 << 4)
	62	#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
	63	#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
	64	#define TVE_DATA_SOURCE_EXT (0x2 << 4)
	65	#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
	66	#define TVE_IPU_CLK_EN_OFS 3
	67	#define TVE_IPU_CLK_EN BIT(3)
	68	#define TVE_DAC_SAMP_RATE_OFS 1
	69	#define TVE_DAC_SAMP_RATE_WIDTH 2
	70	#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
	71	#define TVE_DAC_FULL_RATE (0x0 << 1)
	72	#define TVE_DAC_DIV2_RATE (0x1 << 1)
	73	#define TVE_DAC_DIV4_RATE (0x2 << 1)
	74	#define TVE_EN BIT(0)
	75
	76	/* TVE_TVDACx_CONT_REG */
	77	#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
	78
	79	/* TVE_CD_CONT_REG */
	80	#define TVE_CD_CH_2_SM_EN BIT(22)
	81	#define TVE_CD_CH_1_SM_EN BIT(21)
	82	#define TVE_CD_CH_0_SM_EN BIT(20)
	83	#define TVE_CD_CH_2_LM_EN BIT(18)
	84	#define TVE_CD_CH_1_LM_EN BIT(17)
	85	#define TVE_CD_CH_0_LM_EN BIT(16)
	86	#define TVE_CD_CH_2_REF_LVL BIT(10)
	87	#define TVE_CD_CH_1_REF_LVL BIT(9)
	88	#define TVE_CD_CH_0_REF_LVL BIT(8)
	89	#define TVE_CD_EN BIT(0)
	90
	91	/* TVE_INT_CONT_REG */
	92	#define TVE_FRAME_END_IEN BIT(13)
93	#define TVE_CD_MON_END_IEN BIT(2)
94	#define TVE_CD_SM_IEN BIT(1)
95	#define TVE_CD_LM_IEN BIT(0)
96
97	/* TVE_TST_MODE_REG */
98	#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
99
100	#define con_to_tve(x) container_of(x, struct imx_tve, connector)
101	#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
102
103	enum {
104	TVE_MODE_TVOUT,
105	TVE_MODE_VGA,
106	};
107
108	struct imx_tve {
109	struct drm_connector connector;
fcbc51e5	110	struct drm_encoder encoder;
fcbc51e5	111	struct device *dev;
fcbc51e5 PZ	112	spinlock_t lock; /* register lock */
	113	bool enabled;
	114	int mode;
	115
	116	struct regmap *regmap;
	117	struct regulator *dac_reg;
	118	struct i2c_adapter *ddc;
	119	struct clk *clk;
	120	struct clk *di_sel_clk;
	121	struct clk_hw clk_hw_di;
	122	struct clk *di_clk;
	123	int vsync_pin;
	124	int hsync_pin;
	125	};
	126
	127	static void tve_lock(void *__tve)
5d78bf80	128	__acquires(&tve->lock)
fcbc51e5 PZ	129	{
fcbc51e5 PZ	130	struct imx_tve *tve = __tve;
63bc5164	131
fcbc51e5 PZ	132	spin_lock(&tve->lock);
	133	}
	134
	135	static void tve_unlock(void *__tve)
5d78bf80	136	__releases(&tve->lock)
fcbc51e5 PZ	137	{
fcbc51e5 PZ	138	struct imx_tve *tve = __tve;
63bc5164	139
fcbc51e5 PZ	140	spin_unlock(&tve->lock);
	141	}
	142
	143	static void tve_enable(struct imx_tve *tve)
	144	{
fcbc51e5 PZ	145	int ret;
fcbc51e5 PZ	146
fcbc51e5	147	if (!tve->enabled) {
89bc5be7	148	tve->enabled = true;
fcbc51e5 PZ	149	clk_prepare_enable(tve->clk);
	150	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
	151	TVE_IPU_CLK_EN \| TVE_EN,
	152	TVE_IPU_CLK_EN \| TVE_EN);
	153	}
	154
	155	/* clear interrupt status register */
	156	regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
	157
	158	/* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
	159	if (tve->mode == TVE_MODE_VGA)
	160	regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
	161	else
	162	regmap_write(tve->regmap, TVE_INT_CONT_REG,
89911e58 AW	163	TVE_CD_SM_IEN \|
	164	TVE_CD_LM_IEN \|
	165	TVE_CD_MON_END_IEN);
fcbc51e5 PZ	166	}
	167
	168	static void tve_disable(struct imx_tve *tve)
	169	{
fcbc51e5 PZ	170	int ret;
fcbc51e5 PZ	171
fcbc51e5	172	if (tve->enabled) {
89bc5be7	173	tve->enabled = false;
fcbc51e5 PZ	174	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
	175	TVE_IPU_CLK_EN \| TVE_EN, 0);
	176	clk_disable_unprepare(tve->clk);
	177	}
fcbc51e5 PZ	178	}
	179
	180	static int tve_setup_tvout(struct imx_tve *tve)
	181	{
	182	return -ENOTSUPP;
	183	}
	184
	185	static int tve_setup_vga(struct imx_tve *tve)
	186	{
	187	unsigned int mask;
	188	unsigned int val;
	189	int ret;
	190
	191	/* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
	192	ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
	193	TVE_TVDAC_GAIN_MASK, 0x0a);
	194	ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
	195	TVE_TVDAC_GAIN_MASK, 0x0a);
	196	ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
	197	TVE_TVDAC_GAIN_MASK, 0x0a);
	198
	199	/* set configuration register */
	200	mask = TVE_DATA_SOURCE_MASK \| TVE_INP_VIDEO_FORM;
	201	val = TVE_DATA_SOURCE_BUS2 \| TVE_INP_YCBCR_444;
	202	mask \|= TVE_TV_STAND_MASK \| TVE_P2I_CONV_EN;
	203	val \|= TVE_TV_STAND_HD_1080P30 \| 0;
	204	mask \|= TVE_TV_OUT_MODE_MASK \| TVE_SYNC_CH_0_EN;
	205	val \|= TVE_TV_OUT_RGB \| TVE_SYNC_CH_0_EN;
	206	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
	207	if (ret < 0) {
	208	dev_err(tve->dev, "failed to set configuration: %d\n", ret);
	209	return ret;
	210	}
	211
	212	/* set test mode (as documented) */
	213	ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
	214	TVE_TVDAC_TEST_MODE_MASK, 1);
	215
	216	return 0;
	217	}
	218
	219	static enum drm_connector_status imx_tve_connector_detect(
	220	struct drm_connector *connector, bool force)
	221	{
	222	return connector_status_connected;
	223	}
	224
fcbc51e5 PZ	225	static int imx_tve_connector_get_modes(struct drm_connector *connector)
	226	{
	227	struct imx_tve *tve = con_to_tve(connector);
	228	struct edid *edid;
	229	int ret = 0;
	230
	231	if (!tve->ddc)
	232	return 0;
	233
	234	edid = drm_get_edid(connector, tve->ddc);
	235	if (edid) {
	236	drm_mode_connector_update_edid_property(connector, edid);
	237	ret = drm_add_edid_modes(connector, edid);
	238	kfree(edid);
	239	}
	240
	241	return ret;
	242	}
	243
	244	static int imx_tve_connector_mode_valid(struct drm_connector *connector,
	245	struct drm_display_mode *mode)
	246	{
	247	struct imx_tve *tve = con_to_tve(connector);
	248	unsigned long rate;
baa68c4b	249
fcbc51e5 PZ	250	/* pixel clock with 2x oversampling */
	251	rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
	252	if (rate == mode->clock)
	253	return MODE_OK;
	254
	255	/* pixel clock without oversampling */
	256	rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
	257	if (rate == mode->clock)
	258	return MODE_OK;
	259
	260	dev_warn(tve->dev, "ignoring mode %dx%d\n",
	261	mode->hdisplay, mode->vdisplay);
	262
	263	return MODE_BAD;
	264	}
	265
	266	static struct drm_encoder *imx_tve_connector_best_encoder(
	267	struct drm_connector *connector)
	268	{
	269	struct imx_tve *tve = con_to_tve(connector);
	270
	271	return &tve->encoder;
	272	}
	273
	274	static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
	275	{
	276	struct imx_tve *tve = enc_to_tve(encoder);
	277	int ret;
	278
	279	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
	280	TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
	281	if (ret < 0)
	282	dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
	283	}
	284
	285	static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
	286	const struct drm_display_mode *mode,
	287	struct drm_display_mode *adjusted_mode)
	288	{
	289	return true;
	290	}
	291
	292	static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
	293	{
	294	struct imx_tve *tve = enc_to_tve(encoder);
	295
	296	tve_disable(tve);
	297
	298	switch (tve->mode) {
	299	case TVE_MODE_VGA:
f2d66aad	300	imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
fcbc51e5 PZ	301	tve->hsync_pin, tve->vsync_pin);
	302	break;
	303	case TVE_MODE_TVOUT:
f2d66aad	304	imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
fcbc51e5 PZ	305	break;
	306	}
	307	}
	308
	309	static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
	310	struct drm_display_mode *mode,
	311	struct drm_display_mode *adjusted_mode)
	312	{
	313	struct imx_tve *tve = enc_to_tve(encoder);
	314	unsigned long rounded_rate;
	315	unsigned long rate;
	316	int div = 1;
	317	int ret;
	318
	319	/*
	320	* FIXME
	321	* we should try 4k * mode->clock first,
	322	* and enable 4x oversampling for lower resolutions
	323	*/
	324	rate = 2000UL * mode->clock;
	325	clk_set_rate(tve->clk, rate);
	326	rounded_rate = clk_get_rate(tve->clk);
	327	if (rounded_rate >= rate)
	328	div = 2;
	329	clk_set_rate(tve->di_clk, rounded_rate / div);
	330
	331	ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
	332	if (ret < 0) {
	333	dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
	334	ret);
	335	}
	336
	337	if (tve->mode == TVE_MODE_VGA)
	338	tve_setup_vga(tve);
	339	else
	340	tve_setup_tvout(tve);
	341	}
	342
	343	static void imx_tve_encoder_commit(struct drm_encoder *encoder)
	344	{
	345	struct imx_tve *tve = enc_to_tve(encoder);
	346
	347	tve_enable(tve);
	348	}
	349
	350	static void imx_tve_encoder_disable(struct drm_encoder *encoder)
	351	{
	352	struct imx_tve *tve = enc_to_tve(encoder);
	353
	354	tve_disable(tve);
	355	}
	356
fcbc51e5 PZ	357	static struct drm_connector_funcs imx_tve_connector_funcs = {
	358	.dpms = drm_helper_connector_dpms,
	359	.fill_modes = drm_helper_probe_single_connector_modes,
	360	.detect = imx_tve_connector_detect,
1b3f7675	361	.destroy = imx_drm_connector_destroy,
fcbc51e5 PZ	362	};
	363
	364	static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
	365	.get_modes = imx_tve_connector_get_modes,
	366	.best_encoder = imx_tve_connector_best_encoder,
	367	.mode_valid = imx_tve_connector_mode_valid,
	368	};
	369
	370	static struct drm_encoder_funcs imx_tve_encoder_funcs = {
1b3f7675	371	.destroy = imx_drm_encoder_destroy,
fcbc51e5 PZ	372	};
	373
	374	static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
	375	.dpms = imx_tve_encoder_dpms,
	376	.mode_fixup = imx_tve_encoder_mode_fixup,
	377	.prepare = imx_tve_encoder_prepare,
	378	.mode_set = imx_tve_encoder_mode_set,
	379	.commit = imx_tve_encoder_commit,
	380	.disable = imx_tve_encoder_disable,
	381	};
	382
	383	static irqreturn_t imx_tve_irq_handler(int irq, void *data)
	384	{
	385	struct imx_tve *tve = data;
	386	unsigned int val;
	387
	388	regmap_read(tve->regmap, TVE_STAT_REG, &val);
	389
	390	/* clear interrupt status register */
	391	regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
	392
	393	return IRQ_HANDLED;
	394	}
	395
	396	static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
	397	unsigned long parent_rate)
	398	{
	399	struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
	400	unsigned int val;
	401	int ret;
	402
	403	ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
	404	if (ret < 0)
	405	return 0;
	406
	407	switch (val & TVE_DAC_SAMP_RATE_MASK) {
	408	case TVE_DAC_DIV4_RATE:
	409	return parent_rate / 4;
	410	case TVE_DAC_DIV2_RATE:
	411	return parent_rate / 2;
	412	case TVE_DAC_FULL_RATE:
	413	default:
	414	return parent_rate;
	415	}
	416
	417	return 0;
	418	}
	419
	420	static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
	421	unsigned long *prate)
	422	{
	423	unsigned long div;
	424
	425	div = *prate / rate;
	426	if (div >= 4)
	427	return *prate / 4;
	428	else if (div >= 2)
	429	return *prate / 2;
7557b6e1	430	return *prate;
fcbc51e5 PZ	431	}
	432
	433	static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
	434	unsigned long parent_rate)
	435	{
	436	struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
	437	unsigned long div;
	438	u32 val;
	439	int ret;
	440
	441	div = parent_rate / rate;
	442	if (div >= 4)
	443	val = TVE_DAC_DIV4_RATE;
	444	else if (div >= 2)
	445	val = TVE_DAC_DIV2_RATE;
	446	else
	447	val = TVE_DAC_FULL_RATE;
	448
89911e58 AW	449	ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
	450	TVE_DAC_SAMP_RATE_MASK, val);
	451
fcbc51e5 PZ	452	if (ret < 0) {
	453	dev_err(tve->dev, "failed to set divider: %d\n", ret);
	454	return ret;
	455	}
	456
	457	return 0;
	458	}
	459
	460	static struct clk_ops clk_tve_di_ops = {
	461	.round_rate = clk_tve_di_round_rate,
	462	.set_rate = clk_tve_di_set_rate,
	463	.recalc_rate = clk_tve_di_recalc_rate,
	464	};
	465
	466	static int tve_clk_init(struct imx_tve tve, void __iomem base)
	467	{
	468	const char *tve_di_parent[1];
	469	struct clk_init_data init = {
	470	.name = "tve_di",
	471	.ops = &clk_tve_di_ops,
	472	.num_parents = 1,
	473	.flags = 0,
	474	};
	475
	476	tve_di_parent[0] = __clk_get_name(tve->clk);
	477	init.parent_names = (const char **)&tve_di_parent;
	478
	479	tve->clk_hw_di.init = &init;
	480	tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
	481	if (IS_ERR(tve->di_clk)) {
	482	dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
	483	PTR_ERR(tve->di_clk));
	484	return PTR_ERR(tve->di_clk);
	485	}
	486
	487	return 0;
	488	}
	489
1b3f7675	490	static int imx_tve_register(struct drm_device drm, struct imx_tve tve)
fcbc51e5	491	{
f2d66aad	492	int encoder_type;
fcbc51e5 PZ	493	int ret;
fcbc51e5 PZ	494
f2d66aad RK	495	encoder_type = tve->mode == TVE_MODE_VGA ?
	496	DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
	497
1b3f7675 RK	498	ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
	499	tve->dev->of_node);
	500	if (ret)
	501	return ret;
fcbc51e5 PZ	502
fcbc51e5 PZ	503	drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
1b3f7675 RK	504	drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
1b3f7675 RK	505	encoder_type);
fcbc51e5 PZ	506
	507	drm_connector_helper_add(&tve->connector,
	508	&imx_tve_connector_helper_funcs);
1b3f7675 RK	509	drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
1b3f7675 RK	510	DRM_MODE_CONNECTOR_VGA);
fcbc51e5 PZ	511
	512	drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
	513
	514	return 0;
	515	}
	516
	517	static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
	518	{
	519	return (reg % 4 == 0) && (reg <= 0xdc);
	520	}
	521
	522	static struct regmap_config tve_regmap_config = {
	523	.reg_bits = 32,
	524	.val_bits = 32,
	525	.reg_stride = 4,
	526
	527	.readable_reg = imx_tve_readable_reg,
	528
	529	.lock = tve_lock,
	530	.unlock = tve_unlock,
	531
	532	.max_register = 0xdc,
	533	};
	534
8684ba72	535	static const char * const imx_tve_modes[] = {
fcbc51e5 PZ	536	[TVE_MODE_TVOUT] = "tvout",
	537	[TVE_MODE_VGA] = "vga",
	538	};
	539
7fc6cb28	540	static const int of_get_tve_mode(struct device_node *np)
fcbc51e5 PZ	541	{
	542	const char *bm;
	543	int ret, i;
	544
	545	ret = of_property_read_string(np, "fsl,tve-mode", &bm);
	546	if (ret < 0)
	547	return ret;
	548
	549	for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
	550	if (!strcasecmp(bm, imx_tve_modes[i]))
	551	return i;
	552
	553	return -EINVAL;
	554	}
	555
17b5001b	556	static int imx_tve_bind(struct device dev, struct device master, void *data)
fcbc51e5	557	{
17b5001b	558	struct platform_device *pdev = to_platform_device(dev);
1b3f7675	559	struct drm_device *drm = data;
17b5001b	560	struct device_node *np = dev->of_node;
fcbc51e5 PZ	561	struct device_node *ddc_node;
	562	struct imx_tve *tve;
	563	struct resource *res;
	564	void __iomem *base;
	565	unsigned int val;
	566	int irq;
	567	int ret;
	568
17b5001b	569	tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
fcbc51e5 PZ	570	if (!tve)
	571	return -ENOMEM;
	572
17b5001b	573	tve->dev = dev;
fcbc51e5	574	spin_lock_init(&tve->lock);
fcbc51e5	575
a3fe9641	576	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
fcbc51e5 PZ	577	if (ddc_node) {
	578	tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
	579	of_node_put(ddc_node);
	580	}
	581
	582	tve->mode = of_get_tve_mode(np);
	583	if (tve->mode != TVE_MODE_VGA) {
17b5001b	584	dev_err(dev, "only VGA mode supported, currently\n");
fcbc51e5 PZ	585	return -EINVAL;
	586	}
	587
	588	if (tve->mode == TVE_MODE_VGA) {
89911e58 AW	589	ret = of_property_read_u32(np, "fsl,hsync-pin",
	590	&tve->hsync_pin);
	591
fcbc51e5	592	if (ret < 0) {
17b5001b	593	dev_err(dev, "failed to get vsync pin\n");
fcbc51e5 PZ	594	return ret;
	595	}
	596
89911e58 AW	597	ret \|= of_property_read_u32(np, "fsl,vsync-pin",
	598	&tve->vsync_pin);
	599
fcbc51e5	600	if (ret < 0) {
17b5001b	601	dev_err(dev, "failed to get vsync pin\n");
fcbc51e5 PZ	602	return ret;
	603	}
	604	}
	605
	606	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b	607	base = devm_ioremap_resource(dev, res);
9b43b56f LN	608	if (IS_ERR(base))
9b43b56f LN	609	return PTR_ERR(base);
fcbc51e5 PZ	610
fcbc51e5 PZ	611	tve_regmap_config.lock_arg = tve;
17b5001b	612	tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
fcbc51e5 PZ	613	&tve_regmap_config);
fcbc51e5 PZ	614	if (IS_ERR(tve->regmap)) {
17b5001b	615	dev_err(dev, "failed to init regmap: %ld\n",
fcbc51e5 PZ	616	PTR_ERR(tve->regmap));
	617	return PTR_ERR(tve->regmap);
	618	}
	619
	620	irq = platform_get_irq(pdev, 0);
	621	if (irq < 0) {
17b5001b	622	dev_err(dev, "failed to get irq\n");
fcbc51e5 PZ	623	return irq;
	624	}
	625
17b5001b	626	ret = devm_request_threaded_irq(dev, irq, NULL,
fcbc51e5 PZ	627	imx_tve_irq_handler, IRQF_ONESHOT,
	628	"imx-tve", tve);
	629	if (ret < 0) {
17b5001b	630	dev_err(dev, "failed to request irq: %d\n", ret);
fcbc51e5 PZ	631	return ret;
	632	}
	633
17b5001b	634	tve->dac_reg = devm_regulator_get(dev, "dac");
fcbc51e5 PZ	635	if (!IS_ERR(tve->dac_reg)) {
fcbc51e5 PZ	636	regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
c7b0cf3e FE	637	ret = regulator_enable(tve->dac_reg);
	638	if (ret)
	639	return ret;
fcbc51e5 PZ	640	}
fcbc51e5 PZ	641
17b5001b	642	tve->clk = devm_clk_get(dev, "tve");
fcbc51e5	643	if (IS_ERR(tve->clk)) {
17b5001b	644	dev_err(dev, "failed to get high speed tve clock: %ld\n",
fcbc51e5 PZ	645	PTR_ERR(tve->clk));
	646	return PTR_ERR(tve->clk);
	647	}
	648
	649	/* this is the IPU DI clock input selector, can be parented to tve_di */
17b5001b	650	tve->di_sel_clk = devm_clk_get(dev, "di_sel");
fcbc51e5	651	if (IS_ERR(tve->di_sel_clk)) {
17b5001b	652	dev_err(dev, "failed to get ipu di mux clock: %ld\n",
fcbc51e5 PZ	653	PTR_ERR(tve->di_sel_clk));
	654	return PTR_ERR(tve->di_sel_clk);
	655	}
	656
	657	ret = tve_clk_init(tve, base);
	658	if (ret < 0)
	659	return ret;
	660
	661	ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
	662	if (ret < 0) {
f582d9a8 RK	663	dev_err(dev, "failed to read configuration register: %d\n",
f582d9a8 RK	664	ret);
fcbc51e5 PZ	665	return ret;
	666	}
	667	if (val != 0x00100000) {
17b5001b	668	dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
fcbc51e5	669	return -ENODEV;
a22526e4	670	}
fcbc51e5 PZ	671
	672	/* disable cable detection for VGA mode */
	673	ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
	674
1b3f7675	675	ret = imx_tve_register(drm, tve);
fcbc51e5 PZ	676	if (ret)
	677	return ret;
	678
17b5001b	679	dev_set_drvdata(dev, tve);
fcbc51e5 PZ	680
	681	return 0;
	682	}
	683
17b5001b RK	684	static void imx_tve_unbind(struct device dev, struct device master,
17b5001b RK	685	void *data)
fcbc51e5	686	{
17b5001b	687	struct imx_tve *tve = dev_get_drvdata(dev);
fcbc51e5	688
1b3f7675 RK	689	tve->connector.funcs->destroy(&tve->connector);
1b3f7675 RK	690	tve->encoder.funcs->destroy(&tve->encoder);
fcbc51e5 PZ	691
	692	if (!IS_ERR(tve->dac_reg))
	693	regulator_disable(tve->dac_reg);
17b5001b	694	}
fcbc51e5	695
17b5001b RK	696	static const struct component_ops imx_tve_ops = {
	697	.bind = imx_tve_bind,
	698	.unbind = imx_tve_unbind,
	699	};
	700
	701	static int imx_tve_probe(struct platform_device *pdev)
	702	{
	703	return component_add(&pdev->dev, &imx_tve_ops);
	704	}
	705
	706	static int imx_tve_remove(struct platform_device *pdev)
	707	{
	708	component_del(&pdev->dev, &imx_tve_ops);
fcbc51e5 PZ	709	return 0;
	710	}
	711
	712	static const struct of_device_id imx_tve_dt_ids[] = {
	713	{ .compatible = "fsl,imx53-tve", },
	714	{ /* sentinel */ }
	715	};
	716
	717	static struct platform_driver imx_tve_driver = {
	718	.probe = imx_tve_probe,
	719	.remove = imx_tve_remove,
	720	.driver = {
	721	.of_match_table = imx_tve_dt_ids,
	722	.name = "imx-tve",
fcbc51e5 PZ	723	},
	724	};
	725
	726	module_platform_driver(imx_tve_driver);
	727
	728	MODULE_DESCRIPTION("i.MX Television Encoder driver");
	729	MODULE_AUTHOR("Philipp Zabel, Pengutronix");
	730	MODULE_LICENSE("GPL");
52db752c	731	MODULE_ALIAS("platform:imx-tve");