[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_unreference_blob(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.disable = ipu_crtc_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799 SH	23	#include <drm/drm_crtc_helper.h>
	24	#include <linux/fb.h>
	25	#include <linux/clk.h>
b8d181e4	26	#include <linux/errno.h>
f326f799 SH	27	#include <drm/drm_gem_cma_helper.h>
	28	#include <drm/drm_fb_cma_helper.h>
	29
39b9004d	30	#include <video/imx-ipu-v3.h>
f326f799	31	#include "imx-drm.h"
b8d181e4	32	#include "ipuv3-plane.h"
f326f799 SH	33
	34	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	35
f326f799	36	struct ipu_crtc {
f326f799 SH	37	struct device *dev;
	38	struct drm_crtc base;
	39	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	40
	41	/* plane[0] is the full plane, plane[1] is the partial plane */
	42	struct ipu_plane *plane[2];
	43
f326f799	44	struct ipu_dc *dc;
f326f799	45	struct ipu_di *di;
f326f799	46	int irq;
f326f799 SH	47	};
f326f799 SH	48
3df07390 PZ	49	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	50	{
	51	return container_of(crtc, struct ipu_crtc, base);
	52	}
f326f799	53
f6e396e5	54	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	55	{
f6e396e5	56	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
1e6d486b	59	ipu_dc_enable(ipu);
c115edb8 PZ	60	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	61	ipu_di_enable(ipu_crtc->di);
f326f799 SH	62	}
f326f799 SH	63
f6e396e5	64	static void ipu_crtc_disable(struct drm_crtc *crtc)
f326f799	65	{
f6e396e5	66	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	67	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	68
f326f799	69	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	70	ipu_di_disable(ipu_crtc->di);
1e6d486b	71	ipu_dc_disable(ipu);
33f14235	72
5f2f9115 LY	73	spin_lock_irq(&crtc->dev->event_lock);
	74	if (crtc->state->event) {
	75	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	76	crtc->state->event = NULL;
	77	}
	78	spin_unlock_irq(&crtc->dev->event_lock);
f326f799 SH	79	}
f326f799 SH	80
49f98bc4 PZ	81	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	82	{
	83	struct imx_crtc_state *state;
	84
	85	if (crtc->state) {
	86	if (crtc->state->mode_blob)
	87	drm_property_unreference_blob(crtc->state->mode_blob);
	88
	89	state = to_imx_crtc_state(crtc->state);
	90	memset(state, 0, sizeof(*state));
	91	} else {
	92	state = kzalloc(sizeof(*state), GFP_KERNEL);
	93	if (!state)
	94	return;
	95	crtc->state = &state->base;
	96	}
	97
	98	state->base.crtc = crtc;
	99	}
	100
	101	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	102	{
	103	struct imx_crtc_state *state;
	104
	105	state = kzalloc(sizeof(*state), GFP_KERNEL);
	106	if (!state)
	107	return NULL;
	108
	109	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	110
	111	WARN_ON(state->base.crtc != crtc);
	112	state->base.crtc = crtc;
	113
	114	return &state->base;
	115	}
	116
	117	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	118	struct drm_crtc_state *state)
	119	{
	120	__drm_atomic_helper_crtc_destroy_state(state);
	121	kfree(to_imx_crtc_state(state));
	122	}
	123
f326f799	124	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	125	.set_config = drm_atomic_helper_set_config,
f326f799	126	.destroy = drm_crtc_cleanup,
5f2f9115	127	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	128	.reset = imx_drm_crtc_reset,
	129	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	130	.atomic_destroy_state = imx_drm_crtc_destroy_state,
f326f799 SH	131	};
f326f799 SH	132
f326f799 SH	133	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	134	{
	135	struct ipu_crtc *ipu_crtc = dev_id;
	136
	137	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	138
f326f799 SH	139	return IRQ_HANDLED;
	140	}
	141
	142	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	143	const struct drm_display_mode *mode,
	144	struct drm_display_mode *adjusted_mode)
	145	{
0c460a55 SL	146	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	147	struct videomode vm;
	148	int ret;
	149
	150	drm_display_mode_to_videomode(adjusted_mode, &vm);
	151
	152	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	153	if (ret)
	154	return false;
	155
33f14235 LY	156	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	157	return false;
	158
0c460a55 SL	159	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	160
f326f799 SH	161	return true;
	162	}
	163
33f14235 LY	164	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	165	struct drm_crtc_state *state)
	166	{
5f2f9115 LY	167	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	168
	169	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	170	return -EINVAL;
	171
33f14235 LY	172	return 0;
	173	}
	174
5f2f9115 LY	175	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	176	struct drm_crtc_state *old_crtc_state)
	177	{
	178	spin_lock_irq(&crtc->dev->event_lock);
	179	if (crtc->state->event) {
	180	WARN_ON(drm_crtc_vblank_get(crtc));
	181	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	182	crtc->state->event = NULL;
	183	}
	184	spin_unlock_irq(&crtc->dev->event_lock);
	185	}
	186
33f14235 LY	187	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	188	{
	189	struct drm_device *dev = crtc->dev;
	190	struct drm_encoder *encoder;
	191	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	192	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	193	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	194	struct ipu_di_signal_cfg sig_cfg = {};
	195	unsigned long encoder_types = 0;
	196
	197	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	198	mode->hdisplay);
	199	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	200	mode->vdisplay);
	201
032003c5	202	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	203	if (encoder->crtc == crtc)
33f14235	204	encoder_types \|= BIT(encoder->encoder_type);
032003c5	205	}
33f14235 LY	206
	207	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	208	__func__, encoder_types);
	209
	210	/*
	211	* If we have DAC or LDB, then we need the IPU DI clock to be
	212	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	213	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	214	*/
	215	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	216	BIT(DRM_MODE_ENCODER_LVDS)))
	217	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	218	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	219	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	220	else
	221	sig_cfg.clkflags = 0;
	222
49f98bc4	223	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	224	/* Default to driving pixel data on negative clock edges */
49f98bc4	225	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	226	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	227	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	228	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	229	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	230	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	231
	232	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	233
	234	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	235	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	236	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	237	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	238	}
f326f799 SH	239
7ae847dd	240	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	241	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	242	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	243	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	244	.atomic_begin = ipu_crtc_atomic_begin,
f6e396e5 LY	245	.disable = ipu_crtc_disable,
f6e396e5 LY	246	.enable = ipu_crtc_enable,
f326f799 SH	247	};
	248
	249	static int ipu_enable_vblank(struct drm_crtc *crtc)
	250	{
411b0336 LS	251	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	252
	253	enable_irq(ipu_crtc->irq);
	254
f326f799 SH	255	return 0;
	256	}
	257
	258	static void ipu_disable_vblank(struct drm_crtc *crtc)
	259	{
411b0336 LS	260	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	261
	262	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	263	}
f326f799 SH	264
f326f799 SH	265	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	266	.enable_vblank = ipu_enable_vblank,
	267	.disable_vblank = ipu_disable_vblank,
f326f799 SH	268	.crtc_funcs = &ipu_crtc_funcs,
	269	.crtc_helper_funcs = &ipu_helper_funcs,
	270	};
	271
	272	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	273	{
b8d181e4 PZ	274	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	275	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	276	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	277	ipu_di_put(ipu_crtc->di);
	278	}
	279
	280	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	281	struct ipu_client_platformdata *pdata)
	282	{
	283	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	284	int ret;
	285
f326f799 SH	286	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	287	if (IS_ERR(ipu_crtc->dc)) {
	288	ret = PTR_ERR(ipu_crtc->dc);
	289	goto err_out;
	290	}
	291
f326f799 SH	292	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	293	if (IS_ERR(ipu_crtc->di)) {
	294	ret = PTR_ERR(ipu_crtc->di);
	295	goto err_out;
	296	}
	297
f326f799 SH	298	return 0;
	299	err_out:
	300	ipu_put_resources(ipu_crtc);
	301
	302	return ret;
	303	}
	304
	305	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	306	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	307	{
47b1be5c	308	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	309	int dp = -EINVAL;
f326f799 SH	310	int ret;
	311
	312	ret = ipu_get_resources(ipu_crtc, pdata);
	313	if (ret) {
	314	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	315	ret);
	316	return ret;
	317	}
	318
43895599 PZ	319	if (pdata->dp >= 0)
	320	dp = IPU_DP_FLOW_SYNC_BG;
	321	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	322	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	323	if (IS_ERR(ipu_crtc->plane[0])) {
	324	ret = PTR_ERR(ipu_crtc->plane[0]);
	325	goto err_put_resources;
	326	}
43895599	327
655b43cc	328	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	329	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	330	pdata->of_node);
f326f799 SH	331	if (ret) {
	332	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	333	goto err_put_resources;
	334	}
	335
b8d181e4 PZ	336	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	337	if (ret) {
	338	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	339	ret);
	340	goto err_remove_crtc;
	341	}
	342
	343	/* If this crtc is using the DP, add an overlay plane */
	344	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	345	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	346	IPU_DP_FLOW_SYNC_FG,
	347	drm_crtc_mask(&ipu_crtc->base),
	348	DRM_PLANE_TYPE_OVERLAY);
33f14235	349	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	350	ipu_crtc->plane[1] = NULL;
33f14235 LY	351	} else {
	352	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	353	if (ret) {
	354	dev_err(ipu_crtc->dev, "getting plane 1 "
	355	"resources failed with %d.\n", ret);
	356	goto err_put_plane0_res;
	357	}
	358	}
b8d181e4 PZ	359	}
	360
	361	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	362	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	363	"imx_drm", ipu_crtc);
	364	if (ret < 0) {
	365	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	366	goto err_put_plane1_res;
47b1be5c	367	}
411b0336 LS	368	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	369	disable_irq(ipu_crtc->irq);
47b1be5c	370
f326f799 SH	371	return 0;
f326f799 SH	372
33f14235 LY	373	err_put_plane1_res:
	374	if (ipu_crtc->plane[1])
	375	ipu_plane_put_resources(ipu_crtc->plane[1]);
	376	err_put_plane0_res:
b8d181e4 PZ	377	ipu_plane_put_resources(ipu_crtc->plane[0]);
	378	err_remove_crtc:
	379	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	380	err_put_resources:
	381	ipu_put_resources(ipu_crtc);
	382
	383	return ret;
	384	}
	385
17b5001b	386	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	387	{
17b5001b	388	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	389	struct drm_device *drm = data;
f326f799 SH	390	struct ipu_crtc *ipu_crtc;
	391	int ret;
	392
17b5001b	393	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	394	if (!ipu_crtc)
	395	return -ENOMEM;
	396
17b5001b	397	ipu_crtc->dev = dev;
f326f799	398
32266b45	399	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	400	if (ret)
9a8f3f44 LW	401	return ret;
f326f799	402
17b5001b	403	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	404
	405	return 0;
	406	}
	407
17b5001b RK	408	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	409	void *data)
f326f799	410	{
17b5001b	411	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	412
	413	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	414
	415	ipu_put_resources(ipu_crtc);
33f14235 LY	416	if (ipu_crtc->plane[1])
	417	ipu_plane_put_resources(ipu_crtc->plane[1]);
	418	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	419	}
	420
	421	static const struct component_ops ipu_crtc_ops = {
	422	.bind = ipu_drm_bind,
	423	.unbind = ipu_drm_unbind,
	424	};
f326f799	425
17b5001b RK	426	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	427	{
655b43cc	428	struct device *dev = &pdev->dev;
17b5001b RK	429	int ret;
17b5001b RK	430
655b43cc	431	if (!dev->platform_data)
17b5001b RK	432	return -EINVAL;
17b5001b RK	433
655b43cc	434	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	435	if (ret)
	436	return ret;
	437
655b43cc	438	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	439	}
	440
	441	static int ipu_drm_remove(struct platform_device *pdev)
	442	{
	443	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	444	return 0;
	445	}
	446
	447	static struct platform_driver ipu_drm_driver = {
	448	.driver = {
	449	.name = "imx-ipuv3-crtc",
	450	},
	451	.probe = ipu_drm_probe,
99c28f10	452	.remove = ipu_drm_remove,
f326f799 SH	453	};
	454	module_platform_driver(ipu_drm_driver);
	455
	456	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	457	MODULE_DESCRIPTION(DRIVER_DESC);
	458	MODULE_LICENSE("GPL");
ce9c1cef	459	MODULE_ALIAS("platform:imx-ipuv3-crtc");