[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			enabled;
	struct drm_pending_vblank_event *page_flip_event;
	struct drm_framebuffer	*newfb;
	int			irq;
	u32			bus_format;
	int			di_hsync_pin;
	int			di_vsync_pin;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (ipu_crtc->enabled)
		return;

	ipu_dc_enable(ipu);
	ipu_plane_enable(ipu_crtc->plane[0]);
	/* Start DC channel and DI after IDMAC */
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
	drm_crtc_vblank_on(&ipu_crtc->base);

	ipu_crtc->enabled = 1;
}

static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (!ipu_crtc->enabled)
		return;

	/* Stop DC channel and DI before IDMAC */
	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_plane_disable(ipu_crtc->plane[0]);
	ipu_dc_disable(ipu);
	drm_crtc_vblank_off(&ipu_crtc->base);

	ipu_crtc->enabled = 0;
}

static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		ipu_fb_enable(ipu_crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		ipu_fb_disable(ipu_crtc);
		break;
	}
}

static int ipu_page_flip(struct drm_crtc *crtc,
		struct drm_framebuffer *fb,
		struct drm_pending_vblank_event *event,
		uint32_t page_flip_flags)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;

	if (ipu_crtc->newfb)
		return -EBUSY;

	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	if (ret) {
		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
		list_del(&event->base.link);

		return ret;
	}

	ipu_crtc->newfb = fb;
	ipu_crtc->page_flip_event = event;
	crtc->primary->fb = fb;

	return 0;
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = ipu_page_flip,
};

static int ipu_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *orig_mode,
			       struct drm_display_mode *mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;
	int ret;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = 1;
	sig_cfg.clk_pol = 0;
	sig_cfg.bus_format = ipu_crtc->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			       mode->flags & DRM_MODE_FLAG_INTERLACE,
			       ipu_crtc->bus_format, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing display controller failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing panel failed with %d\n", ret);
		return ret;
	}

	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
				  crtc->primary->fb,
				  0, 0, mode->hdisplay, mode->vdisplay,
				  x, y, mode->hdisplay, mode->vdisplay,
				  mode->flags & DRM_MODE_FLAG_INTERLACE);
}

static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
	unsigned long flags;
	struct drm_device *drm = ipu_crtc->base.dev;

	spin_lock_irqsave(&drm->event_lock, flags);
	if (ipu_crtc->page_flip_event)
		drm_crtc_send_vblank_event(&ipu_crtc->base,
					   ipu_crtc->page_flip_event);
	ipu_crtc->page_flip_event = NULL;
	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
	spin_unlock_irqrestore(&drm->event_lock, flags);
}

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	if (ipu_crtc->newfb) {
		struct ipu_plane *plane = ipu_crtc->plane[0];

		ipu_crtc->newfb = NULL;
		ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
				   plane->x, plane->y);
		ipu_crtc_handle_pageflip(ipu_crtc);
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static void ipu_crtc_prepare(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_disable(ipu_crtc);
}

static void ipu_crtc_commit(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_enable(ipu_crtc);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.dpms = ipu_crtc_dpms,
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set = ipu_crtc_mode_set,
	.prepare = ipu_crtc_prepare,
	.commit = ipu_crtc_commit,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->page_flip_event = NULL;
	ipu_crtc->newfb = NULL;
}

static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
		u32 bus_format, int hsync_pin, int vsync_pin)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->bus_format = bus_format;
	ipu_crtc->di_hsync_pin = hsync_pin;
	ipu_crtc->di_vsync_pin = vsync_pin;

	return 0;
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			ipu_crtc->dev->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1]))
			ipu_crtc->plane[1] = NULL;
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane_res;
	}

	return 0;

err_put_plane_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_plane_put_resources(ipu_crtc->plane[0]);
	ipu_put_resources(ipu_crtc);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
f326f799 SH	21	#include <drm/drm_crtc_helper.h>
	22	#include <linux/fb.h>
	23	#include <linux/clk.h>
b8d181e4	24	#include <linux/errno.h>
f326f799 SH	25	#include <drm/drm_gem_cma_helper.h>
	26	#include <drm/drm_fb_cma_helper.h>
	27
39b9004d	28	#include <video/imx-ipu-v3.h>
f326f799	29	#include "imx-drm.h"
b8d181e4	30	#include "ipuv3-plane.h"
f326f799 SH	31
	32	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	33
f326f799	34	struct ipu_crtc {
f326f799 SH	35	struct device *dev;
	36	struct drm_crtc base;
	37	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	38
	39	/* plane[0] is the full plane, plane[1] is the partial plane */
	40	struct ipu_plane *plane[2];
	41
f326f799	42	struct ipu_dc *dc;
f326f799 SH	43	struct ipu_di *di;
f326f799 SH	44	int enabled;
f326f799 SH	45	struct drm_pending_vblank_event *page_flip_event;
	46	struct drm_framebuffer *newfb;
	47	int irq;
2872c807	48	u32 bus_format;
2ea42608 PZ	49	int di_hsync_pin;
2ea42608 PZ	50	int di_vsync_pin;
f326f799 SH	51	};
	52
	53	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	54
f326f799 SH	55	static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
f326f799 SH	56	{
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
f326f799 SH	59	if (ipu_crtc->enabled)
	60	return;
	61
1e6d486b	62	ipu_dc_enable(ipu);
b8d181e4	63	ipu_plane_enable(ipu_crtc->plane[0]);
c115edb8 PZ	64	/* Start DC channel and DI after IDMAC */
	65	ipu_dc_enable_channel(ipu_crtc->dc);
	66	ipu_di_enable(ipu_crtc->di);
6c8b66ed	67	drm_crtc_vblank_on(&ipu_crtc->base);
f326f799 SH	68
	69	ipu_crtc->enabled = 1;
	70	}
	71
	72	static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
	73	{
1e6d486b PZ	74	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	75
f326f799 SH	76	if (!ipu_crtc->enabled)
	77	return;
	78
c115edb8	79	/* Stop DC channel and DI before IDMAC */
f326f799	80	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	81	ipu_di_disable(ipu_crtc->di);
c115edb8	82	ipu_plane_disable(ipu_crtc->plane[0]);
1e6d486b	83	ipu_dc_disable(ipu);
6c8b66ed	84	drm_crtc_vblank_off(&ipu_crtc->base);
f326f799 SH	85
	86	ipu_crtc->enabled = 0;
	87	}
	88
	89	static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
	90	{
	91	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	92
a8e4e232	93	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
f326f799 SH	94
	95	switch (mode) {
	96	case DRM_MODE_DPMS_ON:
	97	ipu_fb_enable(ipu_crtc);
	98	break;
	99	case DRM_MODE_DPMS_STANDBY:
	100	case DRM_MODE_DPMS_SUSPEND:
	101	case DRM_MODE_DPMS_OFF:
	102	ipu_fb_disable(ipu_crtc);
	103	break;
	104	}
	105	}
	106
	107	static int ipu_page_flip(struct drm_crtc *crtc,
	108	struct drm_framebuffer *fb,
ed8d1975 KP	109	struct drm_pending_vblank_event *event,
ed8d1975 KP	110	uint32_t page_flip_flags)
f326f799 SH	111	{
	112	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	113	int ret;
	114
	115	if (ipu_crtc->newfb)
	116	return -EBUSY;
	117
	118	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	119	if (ret) {
	120	dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
	121	list_del(&event->base.link);
	122
	123	return ret;
	124	}
	125
	126	ipu_crtc->newfb = fb;
	127	ipu_crtc->page_flip_event = event;
f4510a27	128	crtc->primary->fb = fb;
f326f799 SH	129
	130	return 0;
	131	}
	132
	133	static const struct drm_crtc_funcs ipu_crtc_funcs = {
	134	.set_config = drm_crtc_helper_set_config,
	135	.destroy = drm_crtc_cleanup,
	136	.page_flip = ipu_page_flip,
	137	};
	138
f326f799 SH	139	static int ipu_crtc_mode_set(struct drm_crtc *crtc,
	140	struct drm_display_mode *orig_mode,
	141	struct drm_display_mode *mode,
	142	int x, int y,
	143	struct drm_framebuffer *old_fb)
	144	{
d50141d8 RK	145	struct drm_device *dev = crtc->dev;
d50141d8 RK	146	struct drm_encoder *encoder;
f326f799	147	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
f326f799	148	struct ipu_di_signal_cfg sig_cfg = {};
d50141d8	149	unsigned long encoder_types = 0;
d50141d8	150	int ret;
f326f799 SH	151
	152	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	153	mode->hdisplay);
	154	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	155	mode->vdisplay);
	156
d50141d8 RK	157	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
	158	if (encoder->crtc == crtc)
	159	encoder_types \|= BIT(encoder->encoder_type);
	160
	161	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	162	__func__, encoder_types);
	163
	164	/*
e0d155ca PZ	165	* If we have DAC or LDB, then we need the IPU DI clock to be
	166	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	167	* clock from 27 MHz TVE_DI clock, but allow to divide it.
d50141d8 RK	168	*/
d50141d8 RK	169	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
d50141d8 RK	170	BIT(DRM_MODE_ENCODER_LVDS)))
d50141d8 RK	171	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
e0d155ca PZ	172	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
e0d155ca PZ	173	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
d50141d8 RK	174	else
	175	sig_cfg.clkflags = 0;
	176
f326f799	177	sig_cfg.enable_pol = 1;
85de9d17	178	sig_cfg.clk_pol = 0;
2872c807	179	sig_cfg.bus_format = ipu_crtc->bus_format;
f326f799	180	sig_cfg.v_to_h_sync = 0;
2ea42608 PZ	181	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	182	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
	183
b6835a71 SL	184	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	185
	186	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	187	mode->flags & DRM_MODE_FLAG_INTERLACE,
2872c807	188	ipu_crtc->bus_format, mode->hdisplay);
f326f799 SH	189	if (ret) {
	190	dev_err(ipu_crtc->dev,
	191	"initializing display controller failed with %d\n",
	192	ret);
	193	return ret;
	194	}
	195
	196	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	197	if (ret) {
	198	dev_err(ipu_crtc->dev,
	199	"initializing panel failed with %d\n", ret);
	200	return ret;
	201	}
	202
30e94a56 YD	203	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
30e94a56 YD	204	crtc->primary->fb,
b8d181e4	205	0, 0, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	206	x, y, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	207	mode->flags & DRM_MODE_FLAG_INTERLACE);
f326f799 SH	208	}
	209
	210	static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
	211	{
f326f799 SH	212	unsigned long flags;
	213	struct drm_device *drm = ipu_crtc->base.dev;
	214
	215	spin_lock_irqsave(&drm->event_lock, flags);
0eca56f9	216	if (ipu_crtc->page_flip_event)
69d21fc0 RK	217	drm_crtc_send_vblank_event(&ipu_crtc->base,
69d21fc0 RK	218	ipu_crtc->page_flip_event);
f326f799	219	ipu_crtc->page_flip_event = NULL;
f326f799	220	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
f326f799 SH	221	spin_unlock_irqrestore(&drm->event_lock, flags);
	222	}
	223
	224	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	225	{
	226	struct ipu_crtc *ipu_crtc = dev_id;
	227
	228	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	229
	230	if (ipu_crtc->newfb) {
30e94a56 YD	231	struct ipu_plane *plane = ipu_crtc->plane[0];
30e94a56 YD	232
f326f799	233	ipu_crtc->newfb = NULL;
30e94a56 YD	234	ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
30e94a56 YD	235	plane->x, plane->y);
f326f799 SH	236	ipu_crtc_handle_pageflip(ipu_crtc);
	237	}
	238
	239	return IRQ_HANDLED;
	240	}
	241
	242	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	243	const struct drm_display_mode *mode,
	244	struct drm_display_mode *adjusted_mode)
	245	{
0c460a55 SL	246	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	247	struct videomode vm;
	248	int ret;
	249
	250	drm_display_mode_to_videomode(adjusted_mode, &vm);
	251
	252	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	253	if (ret)
	254	return false;
	255
	256	drm_display_mode_from_videomode(&vm, adjusted_mode);
	257
f326f799 SH	258	return true;
	259	}
	260
	261	static void ipu_crtc_prepare(struct drm_crtc *crtc)
	262	{
	263	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	264
	265	ipu_fb_disable(ipu_crtc);
	266	}
	267
	268	static void ipu_crtc_commit(struct drm_crtc *crtc)
	269	{
	270	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	271
	272	ipu_fb_enable(ipu_crtc);
	273	}
	274
7ae847dd	275	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799 SH	276	.dpms = ipu_crtc_dpms,
	277	.mode_fixup = ipu_crtc_mode_fixup,
	278	.mode_set = ipu_crtc_mode_set,
	279	.prepare = ipu_crtc_prepare,
	280	.commit = ipu_crtc_commit,
f326f799 SH	281	};
	282
	283	static int ipu_enable_vblank(struct drm_crtc *crtc)
	284	{
f326f799 SH	285	return 0;
	286	}
	287
	288	static void ipu_disable_vblank(struct drm_crtc *crtc)
	289	{
	290	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	291
6ee4d7fe SH	292	ipu_crtc->page_flip_event = NULL;
6ee4d7fe SH	293	ipu_crtc->newfb = NULL;
f326f799 SH	294	}
f326f799 SH	295
d50141d8	296	static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
2872c807	297	u32 bus_format, int hsync_pin, int vsync_pin)
f326f799 SH	298	{
	299	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	300
2872c807	301	ipu_crtc->bus_format = bus_format;
2ea42608 PZ	302	ipu_crtc->di_hsync_pin = hsync_pin;
2ea42608 PZ	303	ipu_crtc->di_vsync_pin = vsync_pin;
f326f799	304
f326f799 SH	305	return 0;
	306	}
	307
	308	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	309	.enable_vblank = ipu_enable_vblank,
	310	.disable_vblank = ipu_disable_vblank,
	311	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	312	.crtc_funcs = &ipu_crtc_funcs,
	313	.crtc_helper_funcs = &ipu_helper_funcs,
	314	};
	315
	316	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	317	{
b8d181e4 PZ	318	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	319	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	320	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	321	ipu_di_put(ipu_crtc->di);
	322	}
	323
	324	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	325	struct ipu_client_platformdata *pdata)
	326	{
	327	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	328	int ret;
	329
f326f799 SH	330	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	331	if (IS_ERR(ipu_crtc->dc)) {
	332	ret = PTR_ERR(ipu_crtc->dc);
	333	goto err_out;
	334	}
	335
f326f799 SH	336	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	337	if (IS_ERR(ipu_crtc->di)) {
	338	ret = PTR_ERR(ipu_crtc->di);
	339	goto err_out;
	340	}
	341
f326f799 SH	342	return 0;
	343	err_out:
	344	ipu_put_resources(ipu_crtc);
	345
	346	return ret;
	347	}
	348
	349	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	350	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	351	{
47b1be5c	352	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	353	int dp = -EINVAL;
f326f799 SH	354	int ret;
	355
	356	ret = ipu_get_resources(ipu_crtc, pdata);
	357	if (ret) {
	358	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	359	ret);
	360	return ret;
	361	}
	362
43895599 PZ	363	if (pdata->dp >= 0)
	364	dp = IPU_DP_FLOW_SYNC_BG;
	365	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	366	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	367	if (IS_ERR(ipu_crtc->plane[0])) {
	368	ret = PTR_ERR(ipu_crtc->plane[0]);
	369	goto err_put_resources;
	370	}
43895599	371
655b43cc	372	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599 PZ	373	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
43895599 PZ	374	ipu_crtc->dev->of_node);
f326f799 SH	375	if (ret) {
	376	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	377	goto err_put_resources;
	378	}
	379
b8d181e4 PZ	380	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	381	if (ret) {
	382	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	383	ret);
	384	goto err_remove_crtc;
	385	}
	386
	387	/* If this crtc is using the DP, add an overlay plane */
	388	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	389	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	390	IPU_DP_FLOW_SYNC_FG,
	391	drm_crtc_mask(&ipu_crtc->base),
	392	DRM_PLANE_TYPE_OVERLAY);
b8d181e4 PZ	393	if (IS_ERR(ipu_crtc->plane[1]))
	394	ipu_crtc->plane[1] = NULL;
	395	}
	396
	397	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	398	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	399	"imx_drm", ipu_crtc);
	400	if (ret < 0) {
	401	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
b8d181e4	402	goto err_put_plane_res;
47b1be5c PZ	403	}
47b1be5c PZ	404
f326f799 SH	405	return 0;
f326f799 SH	406
b8d181e4 PZ	407	err_put_plane_res:
	408	ipu_plane_put_resources(ipu_crtc->plane[0]);
	409	err_remove_crtc:
	410	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	411	err_put_resources:
	412	ipu_put_resources(ipu_crtc);
	413
	414	return ret;
	415	}
	416
17b5001b	417	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	418	{
17b5001b	419	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	420	struct drm_device *drm = data;
f326f799 SH	421	struct ipu_crtc *ipu_crtc;
	422	int ret;
	423
17b5001b	424	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	425	if (!ipu_crtc)
	426	return -ENOMEM;
	427
17b5001b	428	ipu_crtc->dev = dev;
f326f799	429
32266b45	430	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	431	if (ret)
9a8f3f44 LW	432	return ret;
f326f799	433
17b5001b	434	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	435
	436	return 0;
	437	}
	438
17b5001b RK	439	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	440	void *data)
f326f799	441	{
17b5001b	442	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	443
	444	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	445
b8d181e4	446	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799	447	ipu_put_resources(ipu_crtc);
17b5001b RK	448	}
	449
	450	static const struct component_ops ipu_crtc_ops = {
	451	.bind = ipu_drm_bind,
	452	.unbind = ipu_drm_unbind,
	453	};
f326f799	454
17b5001b RK	455	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	456	{
655b43cc	457	struct device *dev = &pdev->dev;
17b5001b RK	458	int ret;
17b5001b RK	459
655b43cc	460	if (!dev->platform_data)
17b5001b RK	461	return -EINVAL;
17b5001b RK	462
655b43cc	463	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	464	if (ret)
	465	return ret;
	466
655b43cc	467	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	468	}
	469
	470	static int ipu_drm_remove(struct platform_device *pdev)
	471	{
	472	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	473	return 0;
	474	}
	475
	476	static struct platform_driver ipu_drm_driver = {
	477	.driver = {
	478	.name = "imx-ipuv3-crtc",
	479	},
	480	.probe = ipu_drm_probe,
99c28f10	481	.remove = ipu_drm_remove,
f326f799 SH	482	};
	483	module_platform_driver(ipu_drm_driver);
	484
	485	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	486	MODULE_DESCRIPTION(DRIVER_DESC);
	487	MODULE_LICENSE("GPL");
ce9c1cef	488	MODULE_ALIAS("platform:imx-ipuv3-crtc");