[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			enabled;
	struct drm_pending_vblank_event *page_flip_event;
	struct drm_framebuffer	*newfb;
	int			irq;
	u32			bus_format;
	int			di_hsync_pin;
	int			di_vsync_pin;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (ipu_crtc->enabled)
		return;

	ipu_dc_enable(ipu);
	ipu_plane_enable(ipu_crtc->plane[0]);
	/* Start DC channel and DI after IDMAC */
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);

	ipu_crtc->enabled = 1;
}

static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (!ipu_crtc->enabled)
		return;

	/* Stop DC channel and DI before IDMAC */
	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_plane_disable(ipu_crtc->plane[0]);
	ipu_dc_disable(ipu);

	ipu_crtc->enabled = 0;
}

static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		ipu_fb_enable(ipu_crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		ipu_fb_disable(ipu_crtc);
		break;
	}
}

static int ipu_page_flip(struct drm_crtc *crtc,
		struct drm_framebuffer *fb,
		struct drm_pending_vblank_event *event,
		uint32_t page_flip_flags)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;

	if (ipu_crtc->newfb)
		return -EBUSY;

	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	if (ret) {
		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
		list_del(&event->base.link);

		return ret;
	}

	ipu_crtc->newfb = fb;
	ipu_crtc->page_flip_event = event;
	crtc->primary->fb = fb;

	return 0;
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = ipu_page_flip,
};

static int ipu_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *orig_mode,
			       struct drm_display_mode *mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;
	int ret;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = 1;
	sig_cfg.clk_pol = 0;
	sig_cfg.bus_format = ipu_crtc->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			       mode->flags & DRM_MODE_FLAG_INTERLACE,
			       ipu_crtc->bus_format, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing display controller failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing panel failed with %d\n", ret);
		return ret;
	}

	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
				  crtc->primary->fb,
				  0, 0, mode->hdisplay, mode->vdisplay,
				  x, y, mode->hdisplay, mode->vdisplay,
				  mode->flags & DRM_MODE_FLAG_INTERLACE);
}

static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
	unsigned long flags;
	struct drm_device *drm = ipu_crtc->base.dev;

	spin_lock_irqsave(&drm->event_lock, flags);
	if (ipu_crtc->page_flip_event)
		drm_crtc_send_vblank_event(&ipu_crtc->base,
					   ipu_crtc->page_flip_event);
	ipu_crtc->page_flip_event = NULL;
	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
	spin_unlock_irqrestore(&drm->event_lock, flags);
}

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	if (ipu_crtc->newfb) {
		struct ipu_plane *plane = ipu_crtc->plane[0];

		ipu_crtc->newfb = NULL;
		ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
				   plane->x, plane->y);
		ipu_crtc_handle_pageflip(ipu_crtc);
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static void ipu_crtc_prepare(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_disable(ipu_crtc);
}

static void ipu_crtc_commit(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_enable(ipu_crtc);
}

static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.dpms = ipu_crtc_dpms,
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set = ipu_crtc_mode_set,
	.prepare = ipu_crtc_prepare,
	.commit = ipu_crtc_commit,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->page_flip_event = NULL;
	ipu_crtc->newfb = NULL;
}

static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
		u32 bus_format, int hsync_pin, int vsync_pin)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->bus_format = bus_format;
	ipu_crtc->di_hsync_pin = hsync_pin;
	ipu_crtc->di_vsync_pin = vsync_pin;

	return 0;
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			ipu_crtc->dev->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1]))
			ipu_crtc->plane[1] = NULL;
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane_res;
	}

	return 0;

err_put_plane_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_plane_put_resources(ipu_crtc->plane[0]);
	ipu_put_resources(ipu_crtc);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
f326f799 SH	21	#include <drm/drm_crtc_helper.h>
	22	#include <linux/fb.h>
	23	#include <linux/clk.h>
b8d181e4	24	#include <linux/errno.h>
f326f799 SH	25	#include <drm/drm_gem_cma_helper.h>
	26	#include <drm/drm_fb_cma_helper.h>
	27
39b9004d	28	#include <video/imx-ipu-v3.h>
f326f799	29	#include "imx-drm.h"
b8d181e4	30	#include "ipuv3-plane.h"
f326f799 SH	31
	32	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	33
f326f799	34	struct ipu_crtc {
f326f799 SH	35	struct device *dev;
	36	struct drm_crtc base;
	37	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	38
	39	/* plane[0] is the full plane, plane[1] is the partial plane */
	40	struct ipu_plane *plane[2];
	41
f326f799	42	struct ipu_dc *dc;
f326f799 SH	43	struct ipu_di *di;
f326f799 SH	44	int enabled;
f326f799 SH	45	struct drm_pending_vblank_event *page_flip_event;
	46	struct drm_framebuffer *newfb;
	47	int irq;
2872c807	48	u32 bus_format;
2ea42608 PZ	49	int di_hsync_pin;
2ea42608 PZ	50	int di_vsync_pin;
f326f799 SH	51	};
	52
	53	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	54
f326f799 SH	55	static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
f326f799 SH	56	{
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
f326f799 SH	59	if (ipu_crtc->enabled)
	60	return;
	61
1e6d486b	62	ipu_dc_enable(ipu);
b8d181e4	63	ipu_plane_enable(ipu_crtc->plane[0]);
c115edb8 PZ	64	/* Start DC channel and DI after IDMAC */
	65	ipu_dc_enable_channel(ipu_crtc->dc);
	66	ipu_di_enable(ipu_crtc->di);
f326f799 SH	67
	68	ipu_crtc->enabled = 1;
	69	}
	70
	71	static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
	72	{
1e6d486b PZ	73	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	74
f326f799 SH	75	if (!ipu_crtc->enabled)
	76	return;
	77
c115edb8	78	/* Stop DC channel and DI before IDMAC */
f326f799	79	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	80	ipu_di_disable(ipu_crtc->di);
c115edb8	81	ipu_plane_disable(ipu_crtc->plane[0]);
1e6d486b	82	ipu_dc_disable(ipu);
f326f799 SH	83
	84	ipu_crtc->enabled = 0;
	85	}
	86
	87	static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
	88	{
	89	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	90
a8e4e232	91	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
f326f799 SH	92
	93	switch (mode) {
	94	case DRM_MODE_DPMS_ON:
	95	ipu_fb_enable(ipu_crtc);
	96	break;
	97	case DRM_MODE_DPMS_STANDBY:
	98	case DRM_MODE_DPMS_SUSPEND:
	99	case DRM_MODE_DPMS_OFF:
	100	ipu_fb_disable(ipu_crtc);
	101	break;
	102	}
	103	}
	104
	105	static int ipu_page_flip(struct drm_crtc *crtc,
	106	struct drm_framebuffer *fb,
ed8d1975 KP	107	struct drm_pending_vblank_event *event,
ed8d1975 KP	108	uint32_t page_flip_flags)
f326f799 SH	109	{
	110	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	111	int ret;
	112
	113	if (ipu_crtc->newfb)
	114	return -EBUSY;
	115
	116	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	117	if (ret) {
	118	dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
	119	list_del(&event->base.link);
	120
	121	return ret;
	122	}
	123
	124	ipu_crtc->newfb = fb;
	125	ipu_crtc->page_flip_event = event;
f4510a27	126	crtc->primary->fb = fb;
f326f799 SH	127
	128	return 0;
	129	}
	130
	131	static const struct drm_crtc_funcs ipu_crtc_funcs = {
	132	.set_config = drm_crtc_helper_set_config,
	133	.destroy = drm_crtc_cleanup,
	134	.page_flip = ipu_page_flip,
	135	};
	136
f326f799 SH	137	static int ipu_crtc_mode_set(struct drm_crtc *crtc,
	138	struct drm_display_mode *orig_mode,
	139	struct drm_display_mode *mode,
	140	int x, int y,
	141	struct drm_framebuffer *old_fb)
	142	{
d50141d8 RK	143	struct drm_device *dev = crtc->dev;
d50141d8 RK	144	struct drm_encoder *encoder;
f326f799	145	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
f326f799	146	struct ipu_di_signal_cfg sig_cfg = {};
d50141d8	147	unsigned long encoder_types = 0;
d50141d8	148	int ret;
f326f799 SH	149
	150	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	151	mode->hdisplay);
	152	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	153	mode->vdisplay);
	154
d50141d8 RK	155	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
	156	if (encoder->crtc == crtc)
	157	encoder_types \|= BIT(encoder->encoder_type);
	158
	159	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	160	__func__, encoder_types);
	161
	162	/*
e0d155ca PZ	163	* If we have DAC or LDB, then we need the IPU DI clock to be
	164	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	165	* clock from 27 MHz TVE_DI clock, but allow to divide it.
d50141d8 RK	166	*/
d50141d8 RK	167	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
d50141d8 RK	168	BIT(DRM_MODE_ENCODER_LVDS)))
d50141d8 RK	169	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
e0d155ca PZ	170	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
e0d155ca PZ	171	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
d50141d8 RK	172	else
	173	sig_cfg.clkflags = 0;
	174
f326f799	175	sig_cfg.enable_pol = 1;
85de9d17	176	sig_cfg.clk_pol = 0;
2872c807	177	sig_cfg.bus_format = ipu_crtc->bus_format;
f326f799	178	sig_cfg.v_to_h_sync = 0;
2ea42608 PZ	179	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	180	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
	181
b6835a71 SL	182	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	183
	184	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	185	mode->flags & DRM_MODE_FLAG_INTERLACE,
2872c807	186	ipu_crtc->bus_format, mode->hdisplay);
f326f799 SH	187	if (ret) {
	188	dev_err(ipu_crtc->dev,
	189	"initializing display controller failed with %d\n",
	190	ret);
	191	return ret;
	192	}
	193
	194	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	195	if (ret) {
	196	dev_err(ipu_crtc->dev,
	197	"initializing panel failed with %d\n", ret);
	198	return ret;
	199	}
	200
30e94a56 YD	201	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
30e94a56 YD	202	crtc->primary->fb,
b8d181e4	203	0, 0, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	204	x, y, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	205	mode->flags & DRM_MODE_FLAG_INTERLACE);
f326f799 SH	206	}
	207
	208	static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
	209	{
f326f799 SH	210	unsigned long flags;
	211	struct drm_device *drm = ipu_crtc->base.dev;
	212
	213	spin_lock_irqsave(&drm->event_lock, flags);
0eca56f9	214	if (ipu_crtc->page_flip_event)
69d21fc0 RK	215	drm_crtc_send_vblank_event(&ipu_crtc->base,
69d21fc0 RK	216	ipu_crtc->page_flip_event);
f326f799	217	ipu_crtc->page_flip_event = NULL;
f326f799	218	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
f326f799 SH	219	spin_unlock_irqrestore(&drm->event_lock, flags);
	220	}
	221
	222	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	223	{
	224	struct ipu_crtc *ipu_crtc = dev_id;
	225
	226	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	227
	228	if (ipu_crtc->newfb) {
30e94a56 YD	229	struct ipu_plane *plane = ipu_crtc->plane[0];
30e94a56 YD	230
f326f799	231	ipu_crtc->newfb = NULL;
30e94a56 YD	232	ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
30e94a56 YD	233	plane->x, plane->y);
f326f799 SH	234	ipu_crtc_handle_pageflip(ipu_crtc);
	235	}
	236
	237	return IRQ_HANDLED;
	238	}
	239
	240	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	241	const struct drm_display_mode *mode,
	242	struct drm_display_mode *adjusted_mode)
	243	{
0c460a55 SL	244	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	245	struct videomode vm;
	246	int ret;
	247
	248	drm_display_mode_to_videomode(adjusted_mode, &vm);
	249
	250	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	251	if (ret)
	252	return false;
	253
	254	drm_display_mode_from_videomode(&vm, adjusted_mode);
	255
f326f799 SH	256	return true;
	257	}
	258
	259	static void ipu_crtc_prepare(struct drm_crtc *crtc)
	260	{
	261	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	262
	263	ipu_fb_disable(ipu_crtc);
	264	}
	265
	266	static void ipu_crtc_commit(struct drm_crtc *crtc)
	267	{
	268	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	269
	270	ipu_fb_enable(ipu_crtc);
	271	}
	272
f326f799 SH	273	static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	274	.dpms = ipu_crtc_dpms,
	275	.mode_fixup = ipu_crtc_mode_fixup,
	276	.mode_set = ipu_crtc_mode_set,
	277	.prepare = ipu_crtc_prepare,
	278	.commit = ipu_crtc_commit,
f326f799 SH	279	};
	280
	281	static int ipu_enable_vblank(struct drm_crtc *crtc)
	282	{
f326f799 SH	283	return 0;
	284	}
	285
	286	static void ipu_disable_vblank(struct drm_crtc *crtc)
	287	{
	288	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	289
6ee4d7fe SH	290	ipu_crtc->page_flip_event = NULL;
6ee4d7fe SH	291	ipu_crtc->newfb = NULL;
f326f799 SH	292	}
f326f799 SH	293
d50141d8	294	static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
2872c807	295	u32 bus_format, int hsync_pin, int vsync_pin)
f326f799 SH	296	{
	297	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	298
2872c807	299	ipu_crtc->bus_format = bus_format;
2ea42608 PZ	300	ipu_crtc->di_hsync_pin = hsync_pin;
2ea42608 PZ	301	ipu_crtc->di_vsync_pin = vsync_pin;
f326f799	302
f326f799 SH	303	return 0;
	304	}
	305
	306	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	307	.enable_vblank = ipu_enable_vblank,
	308	.disable_vblank = ipu_disable_vblank,
	309	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	310	.crtc_funcs = &ipu_crtc_funcs,
	311	.crtc_helper_funcs = &ipu_helper_funcs,
	312	};
	313
	314	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	315	{
b8d181e4 PZ	316	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	317	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	318	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	319	ipu_di_put(ipu_crtc->di);
	320	}
	321
	322	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	323	struct ipu_client_platformdata *pdata)
	324	{
	325	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	326	int ret;
	327
f326f799 SH	328	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	329	if (IS_ERR(ipu_crtc->dc)) {
	330	ret = PTR_ERR(ipu_crtc->dc);
	331	goto err_out;
	332	}
	333
f326f799 SH	334	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	335	if (IS_ERR(ipu_crtc->di)) {
	336	ret = PTR_ERR(ipu_crtc->di);
	337	goto err_out;
	338	}
	339
f326f799 SH	340	return 0;
	341	err_out:
	342	ipu_put_resources(ipu_crtc);
	343
	344	return ret;
	345	}
	346
	347	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	348	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	349	{
47b1be5c	350	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	351	int dp = -EINVAL;
f326f799 SH	352	int ret;
	353
	354	ret = ipu_get_resources(ipu_crtc, pdata);
	355	if (ret) {
	356	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	357	ret);
	358	return ret;
	359	}
	360
43895599 PZ	361	if (pdata->dp >= 0)
	362	dp = IPU_DP_FLOW_SYNC_BG;
	363	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	364	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	365	if (IS_ERR(ipu_crtc->plane[0])) {
	366	ret = PTR_ERR(ipu_crtc->plane[0]);
	367	goto err_put_resources;
	368	}
43895599	369
655b43cc	370	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599 PZ	371	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
43895599 PZ	372	ipu_crtc->dev->of_node);
f326f799 SH	373	if (ret) {
	374	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	375	goto err_put_resources;
	376	}
	377
b8d181e4 PZ	378	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	379	if (ret) {
	380	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	381	ret);
	382	goto err_remove_crtc;
	383	}
	384
	385	/* If this crtc is using the DP, add an overlay plane */
	386	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	387	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	388	IPU_DP_FLOW_SYNC_FG,
	389	drm_crtc_mask(&ipu_crtc->base),
	390	DRM_PLANE_TYPE_OVERLAY);
b8d181e4 PZ	391	if (IS_ERR(ipu_crtc->plane[1]))
	392	ipu_crtc->plane[1] = NULL;
	393	}
	394
	395	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	396	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	397	"imx_drm", ipu_crtc);
	398	if (ret < 0) {
	399	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
b8d181e4	400	goto err_put_plane_res;
47b1be5c PZ	401	}
47b1be5c PZ	402
f326f799 SH	403	return 0;
f326f799 SH	404
b8d181e4 PZ	405	err_put_plane_res:
	406	ipu_plane_put_resources(ipu_crtc->plane[0]);
	407	err_remove_crtc:
	408	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	409	err_put_resources:
	410	ipu_put_resources(ipu_crtc);
	411
	412	return ret;
	413	}
	414
17b5001b	415	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	416	{
17b5001b	417	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	418	struct drm_device *drm = data;
f326f799 SH	419	struct ipu_crtc *ipu_crtc;
	420	int ret;
	421
17b5001b	422	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	423	if (!ipu_crtc)
	424	return -ENOMEM;
	425
17b5001b	426	ipu_crtc->dev = dev;
f326f799	427
32266b45	428	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	429	if (ret)
9a8f3f44 LW	430	return ret;
f326f799	431
17b5001b	432	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	433
	434	return 0;
	435	}
	436
17b5001b RK	437	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	438	void *data)
f326f799	439	{
17b5001b	440	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	441
	442	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	443
b8d181e4	444	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799	445	ipu_put_resources(ipu_crtc);
17b5001b RK	446	}
	447
	448	static const struct component_ops ipu_crtc_ops = {
	449	.bind = ipu_drm_bind,
	450	.unbind = ipu_drm_unbind,
	451	};
f326f799	452
17b5001b RK	453	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	454	{
655b43cc	455	struct device *dev = &pdev->dev;
17b5001b RK	456	int ret;
17b5001b RK	457
655b43cc	458	if (!dev->platform_data)
17b5001b RK	459	return -EINVAL;
17b5001b RK	460
655b43cc	461	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	462	if (ret)
	463	return ret;
	464
655b43cc	465	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	466	}
	467
	468	static int ipu_drm_remove(struct platform_device *pdev)
	469	{
	470	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	471	return 0;
	472	}
	473
	474	static struct platform_driver ipu_drm_driver = {
	475	.driver = {
	476	.name = "imx-ipuv3-crtc",
	477	},
	478	.probe = ipu_drm_probe,
99c28f10	479	.remove = ipu_drm_remove,
f326f799 SH	480	};
	481	module_platform_driver(ipu_drm_driver);
	482
	483	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	484	MODULE_DESCRIPTION(DRIVER_DESC);
	485	MODULE_LICENSE("GPL");
ce9c1cef	486	MODULE_ALIAS("platform:imx-ipuv3-crtc");