[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_unreference_blob(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	drm_crtc_handle_vblank(&ipu_crtc->base);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.disable = ipu_crtc_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799	23	#include <drm/drm_crtc_helper.h>
f326f799	24	#include <linux/clk.h>
b8d181e4	25	#include <linux/errno.h>
f326f799 SH	26	#include <drm/drm_gem_cma_helper.h>
	27	#include <drm/drm_fb_cma_helper.h>
	28
39b9004d	29	#include <video/imx-ipu-v3.h>
f326f799	30	#include "imx-drm.h"
b8d181e4	31	#include "ipuv3-plane.h"
f326f799 SH	32
	33	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	34
f326f799	35	struct ipu_crtc {
f326f799 SH	36	struct device *dev;
	37	struct drm_crtc base;
	38	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	39
	40	/* plane[0] is the full plane, plane[1] is the partial plane */
	41	struct ipu_plane *plane[2];
	42
f326f799	43	struct ipu_dc *dc;
f326f799	44	struct ipu_di *di;
f326f799	45	int irq;
f326f799 SH	46	};
f326f799 SH	47
3df07390 PZ	48	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	49	{
	50	return container_of(crtc, struct ipu_crtc, base);
	51	}
f326f799	52
f6e396e5	53	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	54	{
f6e396e5	55	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	56	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	57
1e6d486b	58	ipu_dc_enable(ipu);
c115edb8 PZ	59	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	60	ipu_di_enable(ipu_crtc->di);
f326f799 SH	61	}
f326f799 SH	62
f6e396e5	63	static void ipu_crtc_disable(struct drm_crtc *crtc)
f326f799	64	{
f6e396e5	65	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	66	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	67
f326f799	68	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	69	ipu_di_disable(ipu_crtc->di);
1e6d486b	70	ipu_dc_disable(ipu);
33f14235	71
5f2f9115 LY	72	spin_lock_irq(&crtc->dev->event_lock);
	73	if (crtc->state->event) {
	74	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	75	crtc->state->event = NULL;
	76	}
	77	spin_unlock_irq(&crtc->dev->event_lock);
f326f799 SH	78	}
f326f799 SH	79
49f98bc4 PZ	80	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	81	{
	82	struct imx_crtc_state *state;
	83
	84	if (crtc->state) {
	85	if (crtc->state->mode_blob)
	86	drm_property_unreference_blob(crtc->state->mode_blob);
	87
	88	state = to_imx_crtc_state(crtc->state);
	89	memset(state, 0, sizeof(*state));
	90	} else {
	91	state = kzalloc(sizeof(*state), GFP_KERNEL);
	92	if (!state)
	93	return;
	94	crtc->state = &state->base;
	95	}
	96
	97	state->base.crtc = crtc;
	98	}
	99
	100	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	101	{
	102	struct imx_crtc_state *state;
	103
	104	state = kzalloc(sizeof(*state), GFP_KERNEL);
	105	if (!state)
	106	return NULL;
	107
	108	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	109
	110	WARN_ON(state->base.crtc != crtc);
	111	state->base.crtc = crtc;
	112
	113	return &state->base;
	114	}
	115
	116	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	117	struct drm_crtc_state *state)
	118	{
	119	__drm_atomic_helper_crtc_destroy_state(state);
	120	kfree(to_imx_crtc_state(state));
	121	}
	122
f326f799	123	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	124	.set_config = drm_atomic_helper_set_config,
f326f799	125	.destroy = drm_crtc_cleanup,
5f2f9115	126	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	127	.reset = imx_drm_crtc_reset,
	128	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	129	.atomic_destroy_state = imx_drm_crtc_destroy_state,
f326f799 SH	130	};
f326f799 SH	131
f326f799 SH	132	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	133	{
	134	struct ipu_crtc *ipu_crtc = dev_id;
	135
3ec2e506	136	drm_crtc_handle_vblank(&ipu_crtc->base);
f326f799	137
f326f799 SH	138	return IRQ_HANDLED;
	139	}
	140
	141	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	142	const struct drm_display_mode *mode,
	143	struct drm_display_mode *adjusted_mode)
	144	{
0c460a55 SL	145	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	146	struct videomode vm;
	147	int ret;
	148
	149	drm_display_mode_to_videomode(adjusted_mode, &vm);
	150
	151	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	152	if (ret)
	153	return false;
	154
33f14235 LY	155	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	156	return false;
	157
0c460a55 SL	158	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	159
f326f799 SH	160	return true;
	161	}
	162
33f14235 LY	163	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	164	struct drm_crtc_state *state)
	165	{
5f2f9115 LY	166	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	167
	168	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	169	return -EINVAL;
	170
33f14235 LY	171	return 0;
	172	}
	173
5f2f9115 LY	174	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	175	struct drm_crtc_state *old_crtc_state)
	176	{
	177	spin_lock_irq(&crtc->dev->event_lock);
	178	if (crtc->state->event) {
	179	WARN_ON(drm_crtc_vblank_get(crtc));
	180	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	181	crtc->state->event = NULL;
	182	}
	183	spin_unlock_irq(&crtc->dev->event_lock);
	184	}
	185
33f14235 LY	186	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	187	{
	188	struct drm_device *dev = crtc->dev;
	189	struct drm_encoder *encoder;
	190	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	191	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	192	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	193	struct ipu_di_signal_cfg sig_cfg = {};
	194	unsigned long encoder_types = 0;
	195
	196	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	197	mode->hdisplay);
	198	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	199	mode->vdisplay);
	200
032003c5	201	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	202	if (encoder->crtc == crtc)
33f14235	203	encoder_types \|= BIT(encoder->encoder_type);
032003c5	204	}
33f14235 LY	205
	206	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	207	__func__, encoder_types);
	208
	209	/*
	210	* If we have DAC or LDB, then we need the IPU DI clock to be
	211	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	212	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	213	*/
	214	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	215	BIT(DRM_MODE_ENCODER_LVDS)))
	216	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	217	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	218	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	219	else
	220	sig_cfg.clkflags = 0;
	221
49f98bc4	222	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	223	/* Default to driving pixel data on negative clock edges */
49f98bc4	224	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	225	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	226	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	227	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	228	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	229	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	230
	231	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	232
	233	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	234	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	235	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	236	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	237	}
f326f799 SH	238
7ae847dd	239	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	240	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	241	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	242	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	243	.atomic_begin = ipu_crtc_atomic_begin,
f6e396e5 LY	244	.disable = ipu_crtc_disable,
f6e396e5 LY	245	.enable = ipu_crtc_enable,
f326f799 SH	246	};
	247
	248	static int ipu_enable_vblank(struct drm_crtc *crtc)
	249	{
411b0336 LS	250	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	251
	252	enable_irq(ipu_crtc->irq);
	253
f326f799 SH	254	return 0;
	255	}
	256
	257	static void ipu_disable_vblank(struct drm_crtc *crtc)
	258	{
411b0336 LS	259	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	260
	261	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	262	}
f326f799 SH	263
f326f799 SH	264	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	265	.enable_vblank = ipu_enable_vblank,
	266	.disable_vblank = ipu_disable_vblank,
f326f799 SH	267	.crtc_funcs = &ipu_crtc_funcs,
	268	.crtc_helper_funcs = &ipu_helper_funcs,
	269	};
	270
	271	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	272	{
b8d181e4 PZ	273	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	274	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	275	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	276	ipu_di_put(ipu_crtc->di);
	277	}
	278
	279	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	280	struct ipu_client_platformdata *pdata)
	281	{
	282	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	283	int ret;
	284
f326f799 SH	285	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	286	if (IS_ERR(ipu_crtc->dc)) {
	287	ret = PTR_ERR(ipu_crtc->dc);
	288	goto err_out;
	289	}
	290
f326f799 SH	291	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	292	if (IS_ERR(ipu_crtc->di)) {
	293	ret = PTR_ERR(ipu_crtc->di);
	294	goto err_out;
	295	}
	296
f326f799 SH	297	return 0;
	298	err_out:
	299	ipu_put_resources(ipu_crtc);
	300
	301	return ret;
	302	}
	303
	304	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	305	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	306	{
47b1be5c	307	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	308	int dp = -EINVAL;
f326f799 SH	309	int ret;
	310
	311	ret = ipu_get_resources(ipu_crtc, pdata);
	312	if (ret) {
	313	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	314	ret);
	315	return ret;
	316	}
	317
43895599 PZ	318	if (pdata->dp >= 0)
	319	dp = IPU_DP_FLOW_SYNC_BG;
	320	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	321	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	322	if (IS_ERR(ipu_crtc->plane[0])) {
	323	ret = PTR_ERR(ipu_crtc->plane[0]);
	324	goto err_put_resources;
	325	}
43895599	326
655b43cc	327	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	328	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	329	pdata->of_node);
f326f799 SH	330	if (ret) {
	331	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	332	goto err_put_resources;
	333	}
	334
b8d181e4 PZ	335	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	336	if (ret) {
	337	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	338	ret);
	339	goto err_remove_crtc;
	340	}
	341
	342	/* If this crtc is using the DP, add an overlay plane */
	343	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	344	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	345	IPU_DP_FLOW_SYNC_FG,
	346	drm_crtc_mask(&ipu_crtc->base),
	347	DRM_PLANE_TYPE_OVERLAY);
33f14235	348	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	349	ipu_crtc->plane[1] = NULL;
33f14235 LY	350	} else {
	351	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	352	if (ret) {
	353	dev_err(ipu_crtc->dev, "getting plane 1 "
	354	"resources failed with %d.\n", ret);
	355	goto err_put_plane0_res;
	356	}
	357	}
b8d181e4 PZ	358	}
	359
	360	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	361	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	362	"imx_drm", ipu_crtc);
	363	if (ret < 0) {
	364	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	365	goto err_put_plane1_res;
47b1be5c	366	}
411b0336 LS	367	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	368	disable_irq(ipu_crtc->irq);
47b1be5c	369
f326f799 SH	370	return 0;
f326f799 SH	371
33f14235 LY	372	err_put_plane1_res:
	373	if (ipu_crtc->plane[1])
	374	ipu_plane_put_resources(ipu_crtc->plane[1]);
	375	err_put_plane0_res:
b8d181e4 PZ	376	ipu_plane_put_resources(ipu_crtc->plane[0]);
	377	err_remove_crtc:
	378	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	379	err_put_resources:
	380	ipu_put_resources(ipu_crtc);
	381
	382	return ret;
	383	}
	384
17b5001b	385	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	386	{
17b5001b	387	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	388	struct drm_device *drm = data;
f326f799 SH	389	struct ipu_crtc *ipu_crtc;
	390	int ret;
	391
17b5001b	392	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	393	if (!ipu_crtc)
	394	return -ENOMEM;
	395
17b5001b	396	ipu_crtc->dev = dev;
f326f799	397
32266b45	398	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	399	if (ret)
9a8f3f44 LW	400	return ret;
f326f799	401
17b5001b	402	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	403
	404	return 0;
	405	}
	406
17b5001b RK	407	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	408	void *data)
f326f799	409	{
17b5001b	410	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	411
	412	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	413
	414	ipu_put_resources(ipu_crtc);
33f14235 LY	415	if (ipu_crtc->plane[1])
	416	ipu_plane_put_resources(ipu_crtc->plane[1]);
	417	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	418	}
	419
	420	static const struct component_ops ipu_crtc_ops = {
	421	.bind = ipu_drm_bind,
	422	.unbind = ipu_drm_unbind,
	423	};
f326f799	424
17b5001b RK	425	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	426	{
655b43cc	427	struct device *dev = &pdev->dev;
17b5001b RK	428	int ret;
17b5001b RK	429
655b43cc	430	if (!dev->platform_data)
17b5001b RK	431	return -EINVAL;
17b5001b RK	432
655b43cc	433	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	434	if (ret)
	435	return ret;
	436
655b43cc	437	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	438	}
	439
	440	static int ipu_drm_remove(struct platform_device *pdev)
	441	{
	442	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	443	return 0;
	444	}
	445
	446	static struct platform_driver ipu_drm_driver = {
	447	.driver = {
	448	.name = "imx-ipuv3-crtc",
	449	},
	450	.probe = ipu_drm_probe,
99c28f10	451	.remove = ipu_drm_remove,
f326f799 SH	452	};
	453	module_platform_driver(ipu_drm_driver);
	454
	455	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	456	MODULE_DESCRIPTION(DRIVER_DESC);
	457	MODULE_LICENSE("GPL");
ce9c1cef	458	MODULE_ALIAS("platform:imx-ipuv3-crtc");