Commit | Line | Data |
---|---|---|
f326f799 SH |
1 | /* |
2 | * i.MX IPUv3 Graphics driver | |
3 | * | |
4 | * Copyright (C) 2011 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
f326f799 | 14 | */ |
17b5001b | 15 | #include <linux/component.h> |
f326f799 SH |
16 | #include <linux/module.h> |
17 | #include <linux/export.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <drm/drmP.h> | |
ae2531ab | 21 | #include <drm/drm_atomic.h> |
255c35f8 | 22 | #include <drm/drm_atomic_helper.h> |
f326f799 SH |
23 | #include <drm/drm_crtc_helper.h> |
24 | #include <linux/fb.h> | |
25 | #include <linux/clk.h> | |
b8d181e4 | 26 | #include <linux/errno.h> |
17a8d08d LS |
27 | #include <linux/reservation.h> |
28 | #include <linux/dma-buf.h> | |
f326f799 SH |
29 | #include <drm/drm_gem_cma_helper.h> |
30 | #include <drm/drm_fb_cma_helper.h> | |
31 | ||
39b9004d | 32 | #include <video/imx-ipu-v3.h> |
f326f799 | 33 | #include "imx-drm.h" |
b8d181e4 | 34 | #include "ipuv3-plane.h" |
f326f799 SH |
35 | |
36 | #define DRIVER_DESC "i.MX IPUv3 Graphics" | |
37 | ||
0bfc2b3d LS |
38 | enum ipu_flip_status { |
39 | IPU_FLIP_NONE, | |
40 | IPU_FLIP_PENDING, | |
17a8d08d | 41 | IPU_FLIP_SUBMITTED, |
0bfc2b3d LS |
42 | }; |
43 | ||
0a7ad343 LS |
44 | struct ipu_flip_work { |
45 | struct work_struct unref_work; | |
46 | struct drm_gem_object *bo; | |
47 | struct drm_pending_vblank_event *page_flip_event; | |
17a8d08d LS |
48 | struct work_struct fence_work; |
49 | struct ipu_crtc *crtc; | |
50 | struct fence *excl; | |
51 | unsigned shared_count; | |
52 | struct fence **shared; | |
0a7ad343 LS |
53 | }; |
54 | ||
f326f799 | 55 | struct ipu_crtc { |
f326f799 SH |
56 | struct device *dev; |
57 | struct drm_crtc base; | |
58 | struct imx_drm_crtc *imx_crtc; | |
b8d181e4 PZ |
59 | |
60 | /* plane[0] is the full plane, plane[1] is the partial plane */ | |
61 | struct ipu_plane *plane[2]; | |
62 | ||
f326f799 | 63 | struct ipu_dc *dc; |
f326f799 SH |
64 | struct ipu_di *di; |
65 | int enabled; | |
0bfc2b3d | 66 | enum ipu_flip_status flip_state; |
0a7ad343 LS |
67 | struct workqueue_struct *flip_queue; |
68 | struct ipu_flip_work *flip_work; | |
f326f799 | 69 | int irq; |
f326f799 SH |
70 | }; |
71 | ||
72 | #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base) | |
73 | ||
33f14235 | 74 | static void ipu_crtc_enable(struct ipu_crtc *ipu_crtc) |
f326f799 | 75 | { |
1e6d486b PZ |
76 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
77 | ||
f326f799 SH |
78 | if (ipu_crtc->enabled) |
79 | return; | |
80 | ||
1e6d486b | 81 | ipu_dc_enable(ipu); |
c115edb8 PZ |
82 | ipu_dc_enable_channel(ipu_crtc->dc); |
83 | ipu_di_enable(ipu_crtc->di); | |
f326f799 | 84 | ipu_crtc->enabled = 1; |
33f14235 LY |
85 | |
86 | /* | |
87 | * In order not to be warned on enabling vblank failure, | |
88 | * we should call drm_crtc_vblank_on() after ->enabled is set to 1. | |
89 | */ | |
90 | drm_crtc_vblank_on(&ipu_crtc->base); | |
f326f799 SH |
91 | } |
92 | ||
33f14235 | 93 | static void ipu_crtc_disable(struct ipu_crtc *ipu_crtc) |
f326f799 | 94 | { |
1e6d486b PZ |
95 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
96 | ||
f326f799 SH |
97 | if (!ipu_crtc->enabled) |
98 | return; | |
99 | ||
f326f799 | 100 | ipu_dc_disable_channel(ipu_crtc->dc); |
f326f799 | 101 | ipu_di_disable(ipu_crtc->di); |
1e6d486b | 102 | ipu_dc_disable(ipu); |
f326f799 | 103 | ipu_crtc->enabled = 0; |
33f14235 LY |
104 | |
105 | drm_crtc_vblank_off(&ipu_crtc->base); | |
f326f799 SH |
106 | } |
107 | ||
108 | static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode) | |
109 | { | |
110 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); | |
111 | ||
a8e4e232 | 112 | dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode); |
f326f799 SH |
113 | |
114 | switch (mode) { | |
115 | case DRM_MODE_DPMS_ON: | |
33f14235 | 116 | ipu_crtc_enable(ipu_crtc); |
f326f799 SH |
117 | break; |
118 | case DRM_MODE_DPMS_STANDBY: | |
119 | case DRM_MODE_DPMS_SUSPEND: | |
120 | case DRM_MODE_DPMS_OFF: | |
33f14235 | 121 | ipu_crtc_disable(ipu_crtc); |
f326f799 SH |
122 | break; |
123 | } | |
124 | } | |
125 | ||
0a7ad343 LS |
126 | static void ipu_flip_unref_work_func(struct work_struct *__work) |
127 | { | |
128 | struct ipu_flip_work *work = | |
129 | container_of(__work, struct ipu_flip_work, unref_work); | |
130 | ||
131 | drm_gem_object_unreference_unlocked(work->bo); | |
132 | kfree(work); | |
133 | } | |
134 | ||
17a8d08d LS |
135 | static void ipu_flip_fence_work_func(struct work_struct *__work) |
136 | { | |
137 | struct ipu_flip_work *work = | |
138 | container_of(__work, struct ipu_flip_work, fence_work); | |
139 | int i; | |
140 | ||
141 | /* wait for all fences attached to the FB obj to signal */ | |
142 | if (work->excl) { | |
143 | fence_wait(work->excl, false); | |
144 | fence_put(work->excl); | |
145 | } | |
146 | for (i = 0; i < work->shared_count; i++) { | |
147 | fence_wait(work->shared[i], false); | |
148 | fence_put(work->shared[i]); | |
149 | } | |
150 | ||
151 | work->crtc->flip_state = IPU_FLIP_SUBMITTED; | |
152 | } | |
153 | ||
f326f799 SH |
154 | static int ipu_page_flip(struct drm_crtc *crtc, |
155 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
156 | struct drm_pending_vblank_event *event, |
157 | uint32_t page_flip_flags) | |
f326f799 | 158 | { |
17a8d08d | 159 | struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0); |
f326f799 | 160 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
0a7ad343 | 161 | struct ipu_flip_work *flip_work; |
f326f799 SH |
162 | int ret; |
163 | ||
0bfc2b3d | 164 | if (ipu_crtc->flip_state != IPU_FLIP_NONE) |
f326f799 SH |
165 | return -EBUSY; |
166 | ||
167 | ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc); | |
168 | if (ret) { | |
169 | dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n"); | |
170 | list_del(&event->base.link); | |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
0a7ad343 LS |
175 | flip_work = kzalloc(sizeof *flip_work, GFP_KERNEL); |
176 | if (!flip_work) { | |
177 | ret = -ENOMEM; | |
178 | goto put_vblank; | |
179 | } | |
180 | INIT_WORK(&flip_work->unref_work, ipu_flip_unref_work_func); | |
181 | flip_work->page_flip_event = event; | |
182 | ||
183 | /* get BO backing the old framebuffer and take a reference */ | |
184 | flip_work->bo = &drm_fb_cma_get_gem_obj(crtc->primary->fb, 0)->base; | |
185 | drm_gem_object_reference(flip_work->bo); | |
186 | ||
187 | ipu_crtc->flip_work = flip_work; | |
17a8d08d LS |
188 | /* |
189 | * If the object has a DMABUF attached, we need to wait on its fences | |
190 | * if there are any. | |
191 | */ | |
192 | if (cma_obj->base.dma_buf) { | |
193 | INIT_WORK(&flip_work->fence_work, ipu_flip_fence_work_func); | |
194 | flip_work->crtc = ipu_crtc; | |
195 | ||
196 | ret = reservation_object_get_fences_rcu( | |
197 | cma_obj->base.dma_buf->resv, &flip_work->excl, | |
198 | &flip_work->shared_count, &flip_work->shared); | |
199 | ||
200 | if (unlikely(ret)) { | |
201 | DRM_ERROR("failed to get fences for buffer\n"); | |
202 | goto free_flip_work; | |
203 | } | |
204 | ||
205 | /* No need to queue the worker if the are no fences */ | |
206 | if (!flip_work->excl && !flip_work->shared_count) { | |
207 | ipu_crtc->flip_state = IPU_FLIP_SUBMITTED; | |
208 | } else { | |
209 | ipu_crtc->flip_state = IPU_FLIP_PENDING; | |
210 | queue_work(ipu_crtc->flip_queue, | |
211 | &flip_work->fence_work); | |
212 | } | |
213 | } else { | |
214 | ipu_crtc->flip_state = IPU_FLIP_SUBMITTED; | |
215 | } | |
f326f799 | 216 | |
ae2531ab LY |
217 | if (crtc->primary->state) |
218 | drm_atomic_set_fb_for_plane(crtc->primary->state, fb); | |
219 | ||
f326f799 | 220 | return 0; |
0a7ad343 | 221 | |
17a8d08d LS |
222 | free_flip_work: |
223 | drm_gem_object_unreference_unlocked(flip_work->bo); | |
224 | kfree(flip_work); | |
225 | ipu_crtc->flip_work = NULL; | |
0a7ad343 LS |
226 | put_vblank: |
227 | imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc); | |
228 | ||
229 | return ret; | |
f326f799 SH |
230 | } |
231 | ||
232 | static const struct drm_crtc_funcs ipu_crtc_funcs = { | |
233 | .set_config = drm_crtc_helper_set_config, | |
234 | .destroy = drm_crtc_cleanup, | |
235 | .page_flip = ipu_page_flip, | |
255c35f8 LY |
236 | .reset = drm_atomic_helper_crtc_reset, |
237 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
238 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
f326f799 SH |
239 | }; |
240 | ||
f326f799 SH |
241 | static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc) |
242 | { | |
f326f799 SH |
243 | unsigned long flags; |
244 | struct drm_device *drm = ipu_crtc->base.dev; | |
0a7ad343 | 245 | struct ipu_flip_work *work = ipu_crtc->flip_work; |
f326f799 SH |
246 | |
247 | spin_lock_irqsave(&drm->event_lock, flags); | |
0a7ad343 | 248 | if (work->page_flip_event) |
69d21fc0 | 249 | drm_crtc_send_vblank_event(&ipu_crtc->base, |
0a7ad343 | 250 | work->page_flip_event); |
f326f799 | 251 | imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc); |
f326f799 SH |
252 | spin_unlock_irqrestore(&drm->event_lock, flags); |
253 | } | |
254 | ||
255 | static irqreturn_t ipu_irq_handler(int irq, void *dev_id) | |
256 | { | |
257 | struct ipu_crtc *ipu_crtc = dev_id; | |
258 | ||
259 | imx_drm_handle_vblank(ipu_crtc->imx_crtc); | |
260 | ||
17a8d08d | 261 | if (ipu_crtc->flip_state == IPU_FLIP_SUBMITTED) { |
30e94a56 YD |
262 | struct ipu_plane *plane = ipu_crtc->plane[0]; |
263 | ||
33f14235 | 264 | ipu_plane_set_base(plane, ipu_crtc->base.primary->fb); |
f326f799 | 265 | ipu_crtc_handle_pageflip(ipu_crtc); |
0a7ad343 LS |
266 | queue_work(ipu_crtc->flip_queue, |
267 | &ipu_crtc->flip_work->unref_work); | |
0bfc2b3d | 268 | ipu_crtc->flip_state = IPU_FLIP_NONE; |
f326f799 SH |
269 | } |
270 | ||
271 | return IRQ_HANDLED; | |
272 | } | |
273 | ||
274 | static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, | |
275 | const struct drm_display_mode *mode, | |
276 | struct drm_display_mode *adjusted_mode) | |
277 | { | |
0c460a55 SL |
278 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
279 | struct videomode vm; | |
280 | int ret; | |
281 | ||
282 | drm_display_mode_to_videomode(adjusted_mode, &vm); | |
283 | ||
284 | ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm); | |
285 | if (ret) | |
286 | return false; | |
287 | ||
33f14235 LY |
288 | if ((vm.vsync_len == 0) || (vm.hsync_len == 0)) |
289 | return false; | |
290 | ||
0c460a55 SL |
291 | drm_display_mode_from_videomode(&vm, adjusted_mode); |
292 | ||
f326f799 SH |
293 | return true; |
294 | } | |
295 | ||
296 | static void ipu_crtc_prepare(struct drm_crtc *crtc) | |
297 | { | |
298 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); | |
299 | ||
33f14235 | 300 | ipu_crtc_disable(ipu_crtc); |
f326f799 SH |
301 | } |
302 | ||
303 | static void ipu_crtc_commit(struct drm_crtc *crtc) | |
304 | { | |
305 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); | |
306 | ||
33f14235 LY |
307 | ipu_crtc_enable(ipu_crtc); |
308 | } | |
309 | ||
310 | static int ipu_crtc_atomic_check(struct drm_crtc *crtc, | |
311 | struct drm_crtc_state *state) | |
312 | { | |
313 | return 0; | |
314 | } | |
315 | ||
316 | static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
317 | { | |
318 | struct drm_device *dev = crtc->dev; | |
319 | struct drm_encoder *encoder; | |
032003c5 | 320 | struct imx_drm_encoder *imx_encoder = NULL; |
33f14235 LY |
321 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
322 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; | |
323 | struct ipu_di_signal_cfg sig_cfg = {}; | |
324 | unsigned long encoder_types = 0; | |
325 | ||
326 | dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, | |
327 | mode->hdisplay); | |
328 | dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__, | |
329 | mode->vdisplay); | |
330 | ||
032003c5 LY |
331 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
332 | if (encoder->crtc == crtc) { | |
33f14235 | 333 | encoder_types |= BIT(encoder->encoder_type); |
032003c5 LY |
334 | imx_encoder = enc_to_imx_enc(encoder); |
335 | } | |
336 | } | |
33f14235 LY |
337 | |
338 | dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n", | |
339 | __func__, encoder_types); | |
340 | ||
341 | /* | |
342 | * If we have DAC or LDB, then we need the IPU DI clock to be | |
343 | * the same as the LDB DI clock. For TVDAC, derive the IPU DI | |
344 | * clock from 27 MHz TVE_DI clock, but allow to divide it. | |
345 | */ | |
346 | if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | | |
347 | BIT(DRM_MODE_ENCODER_LVDS))) | |
348 | sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; | |
349 | else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) | |
350 | sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; | |
351 | else | |
352 | sig_cfg.clkflags = 0; | |
353 | ||
032003c5 | 354 | sig_cfg.enable_pol = !(imx_encoder->bus_flags & DRM_BUS_FLAG_DE_LOW); |
33f14235 | 355 | /* Default to driving pixel data on negative clock edges */ |
032003c5 | 356 | sig_cfg.clk_pol = !!(imx_encoder->bus_flags & |
33f14235 | 357 | DRM_BUS_FLAG_PIXDATA_POSEDGE); |
032003c5 | 358 | sig_cfg.bus_format = imx_encoder->bus_format; |
33f14235 | 359 | sig_cfg.v_to_h_sync = 0; |
032003c5 LY |
360 | sig_cfg.hsync_pin = imx_encoder->di_hsync_pin; |
361 | sig_cfg.vsync_pin = imx_encoder->di_vsync_pin; | |
33f14235 LY |
362 | |
363 | drm_display_mode_to_videomode(mode, &sig_cfg.mode); | |
364 | ||
365 | ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, | |
366 | mode->flags & DRM_MODE_FLAG_INTERLACE, | |
032003c5 | 367 | imx_encoder->bus_format, mode->hdisplay); |
33f14235 | 368 | ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg); |
f326f799 SH |
369 | } |
370 | ||
7ae847dd | 371 | static const struct drm_crtc_helper_funcs ipu_helper_funcs = { |
f326f799 SH |
372 | .dpms = ipu_crtc_dpms, |
373 | .mode_fixup = ipu_crtc_mode_fixup, | |
33f14235 LY |
374 | .mode_set = drm_helper_crtc_mode_set, |
375 | .mode_set_nofb = ipu_crtc_mode_set_nofb, | |
f326f799 SH |
376 | .prepare = ipu_crtc_prepare, |
377 | .commit = ipu_crtc_commit, | |
33f14235 | 378 | .atomic_check = ipu_crtc_atomic_check, |
f326f799 SH |
379 | }; |
380 | ||
381 | static int ipu_enable_vblank(struct drm_crtc *crtc) | |
382 | { | |
411b0336 LS |
383 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
384 | ||
33f14235 LY |
385 | /* |
386 | * ->commit is done after ->mode_set in drm_crtc_helper_set_mode(), | |
387 | * so waiting for vblank in drm_plane_helper_commit() will timeout. | |
388 | * Check the state here to avoid the waiting. | |
389 | */ | |
390 | if (!ipu_crtc->enabled) | |
391 | return -EINVAL; | |
392 | ||
411b0336 LS |
393 | enable_irq(ipu_crtc->irq); |
394 | ||
f326f799 SH |
395 | return 0; |
396 | } | |
397 | ||
398 | static void ipu_disable_vblank(struct drm_crtc *crtc) | |
399 | { | |
411b0336 LS |
400 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
401 | ||
402 | disable_irq_nosync(ipu_crtc->irq); | |
f326f799 SH |
403 | } |
404 | ||
f326f799 SH |
405 | static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = { |
406 | .enable_vblank = ipu_enable_vblank, | |
407 | .disable_vblank = ipu_disable_vblank, | |
f326f799 SH |
408 | .crtc_funcs = &ipu_crtc_funcs, |
409 | .crtc_helper_funcs = &ipu_helper_funcs, | |
410 | }; | |
411 | ||
412 | static void ipu_put_resources(struct ipu_crtc *ipu_crtc) | |
413 | { | |
b8d181e4 PZ |
414 | if (!IS_ERR_OR_NULL(ipu_crtc->dc)) |
415 | ipu_dc_put(ipu_crtc->dc); | |
f326f799 SH |
416 | if (!IS_ERR_OR_NULL(ipu_crtc->di)) |
417 | ipu_di_put(ipu_crtc->di); | |
418 | } | |
419 | ||
420 | static int ipu_get_resources(struct ipu_crtc *ipu_crtc, | |
421 | struct ipu_client_platformdata *pdata) | |
422 | { | |
423 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); | |
424 | int ret; | |
425 | ||
f326f799 SH |
426 | ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc); |
427 | if (IS_ERR(ipu_crtc->dc)) { | |
428 | ret = PTR_ERR(ipu_crtc->dc); | |
429 | goto err_out; | |
430 | } | |
431 | ||
f326f799 SH |
432 | ipu_crtc->di = ipu_di_get(ipu, pdata->di); |
433 | if (IS_ERR(ipu_crtc->di)) { | |
434 | ret = PTR_ERR(ipu_crtc->di); | |
435 | goto err_out; | |
436 | } | |
437 | ||
f326f799 SH |
438 | return 0; |
439 | err_out: | |
440 | ipu_put_resources(ipu_crtc); | |
441 | ||
442 | return ret; | |
443 | } | |
444 | ||
445 | static int ipu_crtc_init(struct ipu_crtc *ipu_crtc, | |
32266b45 | 446 | struct ipu_client_platformdata *pdata, struct drm_device *drm) |
f326f799 | 447 | { |
47b1be5c | 448 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
b8d181e4 | 449 | int dp = -EINVAL; |
f326f799 SH |
450 | int ret; |
451 | ||
452 | ret = ipu_get_resources(ipu_crtc, pdata); | |
453 | if (ret) { | |
454 | dev_err(ipu_crtc->dev, "getting resources failed with %d.\n", | |
455 | ret); | |
456 | return ret; | |
457 | } | |
458 | ||
43895599 PZ |
459 | if (pdata->dp >= 0) |
460 | dp = IPU_DP_FLOW_SYNC_BG; | |
461 | ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0, | |
462 | DRM_PLANE_TYPE_PRIMARY); | |
a7ed3c2b LY |
463 | if (IS_ERR(ipu_crtc->plane[0])) { |
464 | ret = PTR_ERR(ipu_crtc->plane[0]); | |
465 | goto err_put_resources; | |
466 | } | |
43895599 | 467 | |
655b43cc | 468 | ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc, |
43895599 | 469 | &ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs, |
310944d1 | 470 | pdata->of_node); |
f326f799 SH |
471 | if (ret) { |
472 | dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret); | |
473 | goto err_put_resources; | |
474 | } | |
475 | ||
b8d181e4 PZ |
476 | ret = ipu_plane_get_resources(ipu_crtc->plane[0]); |
477 | if (ret) { | |
478 | dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n", | |
479 | ret); | |
480 | goto err_remove_crtc; | |
481 | } | |
482 | ||
483 | /* If this crtc is using the DP, add an overlay plane */ | |
484 | if (pdata->dp >= 0 && pdata->dma[1] > 0) { | |
43895599 PZ |
485 | ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1], |
486 | IPU_DP_FLOW_SYNC_FG, | |
487 | drm_crtc_mask(&ipu_crtc->base), | |
488 | DRM_PLANE_TYPE_OVERLAY); | |
33f14235 | 489 | if (IS_ERR(ipu_crtc->plane[1])) { |
b8d181e4 | 490 | ipu_crtc->plane[1] = NULL; |
33f14235 LY |
491 | } else { |
492 | ret = ipu_plane_get_resources(ipu_crtc->plane[1]); | |
493 | if (ret) { | |
494 | dev_err(ipu_crtc->dev, "getting plane 1 " | |
495 | "resources failed with %d.\n", ret); | |
496 | goto err_put_plane0_res; | |
497 | } | |
498 | } | |
b8d181e4 PZ |
499 | } |
500 | ||
501 | ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]); | |
47b1be5c PZ |
502 | ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0, |
503 | "imx_drm", ipu_crtc); | |
504 | if (ret < 0) { | |
505 | dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret); | |
33f14235 | 506 | goto err_put_plane1_res; |
47b1be5c | 507 | } |
411b0336 LS |
508 | /* Only enable IRQ when we actually need it to trigger work. */ |
509 | disable_irq(ipu_crtc->irq); | |
47b1be5c | 510 | |
0a7ad343 LS |
511 | ipu_crtc->flip_queue = create_singlethread_workqueue("ipu-crtc-flip"); |
512 | ||
f326f799 SH |
513 | return 0; |
514 | ||
33f14235 LY |
515 | err_put_plane1_res: |
516 | if (ipu_crtc->plane[1]) | |
517 | ipu_plane_put_resources(ipu_crtc->plane[1]); | |
518 | err_put_plane0_res: | |
b8d181e4 PZ |
519 | ipu_plane_put_resources(ipu_crtc->plane[0]); |
520 | err_remove_crtc: | |
521 | imx_drm_remove_crtc(ipu_crtc->imx_crtc); | |
f326f799 SH |
522 | err_put_resources: |
523 | ipu_put_resources(ipu_crtc); | |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
17b5001b | 528 | static int ipu_drm_bind(struct device *dev, struct device *master, void *data) |
f326f799 | 529 | { |
17b5001b | 530 | struct ipu_client_platformdata *pdata = dev->platform_data; |
32266b45 | 531 | struct drm_device *drm = data; |
f326f799 SH |
532 | struct ipu_crtc *ipu_crtc; |
533 | int ret; | |
534 | ||
17b5001b | 535 | ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL); |
f326f799 SH |
536 | if (!ipu_crtc) |
537 | return -ENOMEM; | |
538 | ||
17b5001b | 539 | ipu_crtc->dev = dev; |
f326f799 | 540 | |
32266b45 | 541 | ret = ipu_crtc_init(ipu_crtc, pdata, drm); |
9a8f3f44 LW |
542 | if (ret) |
543 | return ret; | |
f326f799 | 544 | |
17b5001b | 545 | dev_set_drvdata(dev, ipu_crtc); |
f326f799 SH |
546 | |
547 | return 0; | |
548 | } | |
549 | ||
17b5001b RK |
550 | static void ipu_drm_unbind(struct device *dev, struct device *master, |
551 | void *data) | |
f326f799 | 552 | { |
17b5001b | 553 | struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev); |
f326f799 SH |
554 | |
555 | imx_drm_remove_crtc(ipu_crtc->imx_crtc); | |
556 | ||
0a7ad343 | 557 | destroy_workqueue(ipu_crtc->flip_queue); |
f326f799 | 558 | ipu_put_resources(ipu_crtc); |
33f14235 LY |
559 | if (ipu_crtc->plane[1]) |
560 | ipu_plane_put_resources(ipu_crtc->plane[1]); | |
561 | ipu_plane_put_resources(ipu_crtc->plane[0]); | |
17b5001b RK |
562 | } |
563 | ||
564 | static const struct component_ops ipu_crtc_ops = { | |
565 | .bind = ipu_drm_bind, | |
566 | .unbind = ipu_drm_unbind, | |
567 | }; | |
f326f799 | 568 | |
17b5001b RK |
569 | static int ipu_drm_probe(struct platform_device *pdev) |
570 | { | |
655b43cc | 571 | struct device *dev = &pdev->dev; |
17b5001b RK |
572 | int ret; |
573 | ||
655b43cc | 574 | if (!dev->platform_data) |
17b5001b RK |
575 | return -EINVAL; |
576 | ||
655b43cc | 577 | ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); |
17b5001b RK |
578 | if (ret) |
579 | return ret; | |
580 | ||
655b43cc | 581 | return component_add(dev, &ipu_crtc_ops); |
17b5001b RK |
582 | } |
583 | ||
584 | static int ipu_drm_remove(struct platform_device *pdev) | |
585 | { | |
586 | component_del(&pdev->dev, &ipu_crtc_ops); | |
f326f799 SH |
587 | return 0; |
588 | } | |
589 | ||
590 | static struct platform_driver ipu_drm_driver = { | |
591 | .driver = { | |
592 | .name = "imx-ipuv3-crtc", | |
593 | }, | |
594 | .probe = ipu_drm_probe, | |
99c28f10 | 595 | .remove = ipu_drm_remove, |
f326f799 SH |
596 | }; |
597 | module_platform_driver(ipu_drm_driver); | |
598 | ||
599 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | |
600 | MODULE_DESCRIPTION(DRIVER_DESC); | |
601 | MODULE_LICENSE("GPL"); | |
ce9c1cef | 602 | MODULE_ALIAS("platform:imx-ipuv3-crtc"); |