[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			enabled;
	struct drm_pending_vblank_event *page_flip_event;
	struct drm_framebuffer	*newfb;
	int			irq;
	u32			bus_format;
	int			di_hsync_pin;
	int			di_vsync_pin;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (ipu_crtc->enabled)
		return;

	ipu_dc_enable(ipu);
	ipu_plane_enable(ipu_crtc->plane[0]);
	/* Start DC channel and DI after IDMAC */
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);

	ipu_crtc->enabled = 1;
}

static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	if (!ipu_crtc->enabled)
		return;

	/* Stop DC channel and DI before IDMAC */
	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_plane_disable(ipu_crtc->plane[0]);
	ipu_dc_disable(ipu);

	ipu_crtc->enabled = 0;
}

static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		ipu_fb_enable(ipu_crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		ipu_fb_disable(ipu_crtc);
		break;
	}
}

static int ipu_page_flip(struct drm_crtc *crtc,
		struct drm_framebuffer *fb,
		struct drm_pending_vblank_event *event,
		uint32_t page_flip_flags)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;

	if (ipu_crtc->newfb)
		return -EBUSY;

	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	if (ret) {
		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
		list_del(&event->base.link);

		return ret;
	}

	ipu_crtc->newfb = fb;
	ipu_crtc->page_flip_event = event;
	crtc->primary->fb = fb;

	return 0;
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = ipu_page_flip,
};

static int ipu_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *orig_mode,
			       struct drm_display_mode *mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;
	int ret;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = 1;
	sig_cfg.clk_pol = 0;
	sig_cfg.bus_format = ipu_crtc->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			       mode->flags & DRM_MODE_FLAG_INTERLACE,
			       ipu_crtc->bus_format, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing display controller failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing panel failed with %d\n", ret);
		return ret;
	}

	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
				  crtc->primary->fb,
				  0, 0, mode->hdisplay, mode->vdisplay,
				  x, y, mode->hdisplay, mode->vdisplay,
				  mode->flags & DRM_MODE_FLAG_INTERLACE);
}

static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
	unsigned long flags;
	struct drm_device *drm = ipu_crtc->base.dev;

	spin_lock_irqsave(&drm->event_lock, flags);
	if (ipu_crtc->page_flip_event)
		drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
	ipu_crtc->page_flip_event = NULL;
	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
	spin_unlock_irqrestore(&drm->event_lock, flags);
}

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	if (ipu_crtc->newfb) {
		struct ipu_plane *plane = ipu_crtc->plane[0];

		ipu_crtc->newfb = NULL;
		ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
				   plane->x, plane->y);
		ipu_crtc_handle_pageflip(ipu_crtc);
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static void ipu_crtc_prepare(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_disable(ipu_crtc);
}

static void ipu_crtc_commit(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_enable(ipu_crtc);
}

static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.dpms = ipu_crtc_dpms,
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set = ipu_crtc_mode_set,
	.prepare = ipu_crtc_prepare,
	.commit = ipu_crtc_commit,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->page_flip_event = NULL;
	ipu_crtc->newfb = NULL;
}

static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
		u32 bus_format, int hsync_pin, int vsync_pin)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->bus_format = bus_format;
	ipu_crtc->di_hsync_pin = hsync_pin;
	ipu_crtc->di_vsync_pin = vsync_pin;

	return 0;
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;
	int id;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
					    pdata->dma[0], dp, BIT(id), true);
	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
						    pdata->dma[1],
						    IPU_DP_FLOW_SYNC_FG,
						    BIT(id), false);
		if (IS_ERR(ipu_crtc->plane[1]))
			ipu_crtc->plane[1] = NULL;
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane_res;
	}

	return 0;

err_put_plane_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent,
						  int port_id)
{
	struct device_node *port;
	int id, ret;

	port = of_get_child_by_name(parent, "port");
	while (port) {
		ret = of_property_read_u32(port, "reg", &id);
		if (!ret && id == port_id)
			return port;

		do {
			port = of_get_next_child(parent, port);
			if (!port)
				return NULL;
		} while (of_node_cmp(port->name, "port"));
	}

	return NULL;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_plane_put_resources(ipu_crtc->plane[0]);
	ipu_put_resources(ipu_crtc);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ipu_client_platformdata *pdata = dev->platform_data;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	if (!dev->of_node) {
		/* Associate crtc device with the corresponding DI port node */
		dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
						      pdata->di + 2);
		if (!dev->of_node) {
			dev_err(dev, "missing port@%d node in %s\n",
				pdata->di + 2, dev->parent->of_node->full_name);
			return -ENODEV;
		}
	}

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
f326f799 SH	21	#include <drm/drm_crtc_helper.h>
	22	#include <linux/fb.h>
	23	#include <linux/clk.h>
b8d181e4	24	#include <linux/errno.h>
f326f799 SH	25	#include <drm/drm_gem_cma_helper.h>
	26	#include <drm/drm_fb_cma_helper.h>
	27
39b9004d	28	#include <video/imx-ipu-v3.h>
f326f799	29	#include "imx-drm.h"
b8d181e4	30	#include "ipuv3-plane.h"
f326f799 SH	31
	32	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	33
f326f799	34	struct ipu_crtc {
f326f799 SH	35	struct device *dev;
	36	struct drm_crtc base;
	37	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	38
	39	/* plane[0] is the full plane, plane[1] is the partial plane */
	40	struct ipu_plane *plane[2];
	41
f326f799	42	struct ipu_dc *dc;
f326f799 SH	43	struct ipu_di *di;
f326f799 SH	44	int enabled;
f326f799 SH	45	struct drm_pending_vblank_event *page_flip_event;
	46	struct drm_framebuffer *newfb;
	47	int irq;
2872c807	48	u32 bus_format;
2ea42608 PZ	49	int di_hsync_pin;
2ea42608 PZ	50	int di_vsync_pin;
f326f799 SH	51	};
	52
	53	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	54
f326f799 SH	55	static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
f326f799 SH	56	{
1e6d486b PZ	57	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	58
f326f799 SH	59	if (ipu_crtc->enabled)
	60	return;
	61
1e6d486b	62	ipu_dc_enable(ipu);
b8d181e4	63	ipu_plane_enable(ipu_crtc->plane[0]);
c115edb8 PZ	64	/* Start DC channel and DI after IDMAC */
	65	ipu_dc_enable_channel(ipu_crtc->dc);
	66	ipu_di_enable(ipu_crtc->di);
f326f799 SH	67
	68	ipu_crtc->enabled = 1;
	69	}
	70
	71	static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
	72	{
1e6d486b PZ	73	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	74
f326f799 SH	75	if (!ipu_crtc->enabled)
	76	return;
	77
c115edb8	78	/* Stop DC channel and DI before IDMAC */
f326f799	79	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	80	ipu_di_disable(ipu_crtc->di);
c115edb8	81	ipu_plane_disable(ipu_crtc->plane[0]);
1e6d486b	82	ipu_dc_disable(ipu);
f326f799 SH	83
	84	ipu_crtc->enabled = 0;
	85	}
	86
	87	static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
	88	{
	89	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	90
a8e4e232	91	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
f326f799 SH	92
	93	switch (mode) {
	94	case DRM_MODE_DPMS_ON:
	95	ipu_fb_enable(ipu_crtc);
	96	break;
	97	case DRM_MODE_DPMS_STANDBY:
	98	case DRM_MODE_DPMS_SUSPEND:
	99	case DRM_MODE_DPMS_OFF:
	100	ipu_fb_disable(ipu_crtc);
	101	break;
	102	}
	103	}
	104
	105	static int ipu_page_flip(struct drm_crtc *crtc,
	106	struct drm_framebuffer *fb,
ed8d1975 KP	107	struct drm_pending_vblank_event *event,
ed8d1975 KP	108	uint32_t page_flip_flags)
f326f799 SH	109	{
	110	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	111	int ret;
	112
	113	if (ipu_crtc->newfb)
	114	return -EBUSY;
	115
	116	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	117	if (ret) {
	118	dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
	119	list_del(&event->base.link);
	120
	121	return ret;
	122	}
	123
	124	ipu_crtc->newfb = fb;
	125	ipu_crtc->page_flip_event = event;
f4510a27	126	crtc->primary->fb = fb;
f326f799 SH	127
	128	return 0;
	129	}
	130
	131	static const struct drm_crtc_funcs ipu_crtc_funcs = {
	132	.set_config = drm_crtc_helper_set_config,
	133	.destroy = drm_crtc_cleanup,
	134	.page_flip = ipu_page_flip,
	135	};
	136
f326f799 SH	137	static int ipu_crtc_mode_set(struct drm_crtc *crtc,
	138	struct drm_display_mode *orig_mode,
	139	struct drm_display_mode *mode,
	140	int x, int y,
	141	struct drm_framebuffer *old_fb)
	142	{
d50141d8 RK	143	struct drm_device *dev = crtc->dev;
d50141d8 RK	144	struct drm_encoder *encoder;
f326f799	145	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
f326f799	146	struct ipu_di_signal_cfg sig_cfg = {};
d50141d8	147	unsigned long encoder_types = 0;
d50141d8	148	int ret;
f326f799 SH	149
	150	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	151	mode->hdisplay);
	152	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	153	mode->vdisplay);
	154
d50141d8 RK	155	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
	156	if (encoder->crtc == crtc)
	157	encoder_types \|= BIT(encoder->encoder_type);
	158
	159	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	160	__func__, encoder_types);
	161
	162	/*
e0d155ca PZ	163	* If we have DAC or LDB, then we need the IPU DI clock to be
	164	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	165	* clock from 27 MHz TVE_DI clock, but allow to divide it.
d50141d8 RK	166	*/
d50141d8 RK	167	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
d50141d8 RK	168	BIT(DRM_MODE_ENCODER_LVDS)))
d50141d8 RK	169	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
e0d155ca PZ	170	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
e0d155ca PZ	171	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
d50141d8 RK	172	else
	173	sig_cfg.clkflags = 0;
	174
f326f799	175	sig_cfg.enable_pol = 1;
85de9d17	176	sig_cfg.clk_pol = 0;
2872c807	177	sig_cfg.bus_format = ipu_crtc->bus_format;
f326f799	178	sig_cfg.v_to_h_sync = 0;
2ea42608 PZ	179	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	180	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
	181
b6835a71 SL	182	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	183
	184	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	185	mode->flags & DRM_MODE_FLAG_INTERLACE,
2872c807	186	ipu_crtc->bus_format, mode->hdisplay);
f326f799 SH	187	if (ret) {
	188	dev_err(ipu_crtc->dev,
	189	"initializing display controller failed with %d\n",
	190	ret);
	191	return ret;
	192	}
	193
	194	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	195	if (ret) {
	196	dev_err(ipu_crtc->dev,
	197	"initializing panel failed with %d\n", ret);
	198	return ret;
	199	}
	200
30e94a56 YD	201	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
30e94a56 YD	202	crtc->primary->fb,
b8d181e4	203	0, 0, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	204	x, y, mode->hdisplay, mode->vdisplay,
dd7fa6d8 PZ	205	mode->flags & DRM_MODE_FLAG_INTERLACE);
f326f799 SH	206	}
	207
	208	static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
	209	{
f326f799 SH	210	unsigned long flags;
	211	struct drm_device *drm = ipu_crtc->base.dev;
	212
	213	spin_lock_irqsave(&drm->event_lock, flags);
0eca56f9 RC	214	if (ipu_crtc->page_flip_event)
0eca56f9 RC	215	drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
f326f799	216	ipu_crtc->page_flip_event = NULL;
f326f799	217	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
f326f799 SH	218	spin_unlock_irqrestore(&drm->event_lock, flags);
	219	}
	220
	221	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	222	{
	223	struct ipu_crtc *ipu_crtc = dev_id;
	224
	225	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	226
	227	if (ipu_crtc->newfb) {
30e94a56 YD	228	struct ipu_plane *plane = ipu_crtc->plane[0];
30e94a56 YD	229
f326f799	230	ipu_crtc->newfb = NULL;
30e94a56 YD	231	ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
30e94a56 YD	232	plane->x, plane->y);
f326f799 SH	233	ipu_crtc_handle_pageflip(ipu_crtc);
	234	}
	235
	236	return IRQ_HANDLED;
	237	}
	238
	239	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	240	const struct drm_display_mode *mode,
	241	struct drm_display_mode *adjusted_mode)
	242	{
0c460a55 SL	243	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	244	struct videomode vm;
	245	int ret;
	246
	247	drm_display_mode_to_videomode(adjusted_mode, &vm);
	248
	249	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	250	if (ret)
	251	return false;
	252
	253	drm_display_mode_from_videomode(&vm, adjusted_mode);
	254
f326f799 SH	255	return true;
	256	}
	257
	258	static void ipu_crtc_prepare(struct drm_crtc *crtc)
	259	{
	260	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	261
	262	ipu_fb_disable(ipu_crtc);
	263	}
	264
	265	static void ipu_crtc_commit(struct drm_crtc *crtc)
	266	{
	267	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	268
	269	ipu_fb_enable(ipu_crtc);
	270	}
	271
f326f799 SH	272	static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	273	.dpms = ipu_crtc_dpms,
	274	.mode_fixup = ipu_crtc_mode_fixup,
	275	.mode_set = ipu_crtc_mode_set,
	276	.prepare = ipu_crtc_prepare,
	277	.commit = ipu_crtc_commit,
f326f799 SH	278	};
	279
	280	static int ipu_enable_vblank(struct drm_crtc *crtc)
	281	{
f326f799 SH	282	return 0;
	283	}
	284
	285	static void ipu_disable_vblank(struct drm_crtc *crtc)
	286	{
	287	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	288
6ee4d7fe SH	289	ipu_crtc->page_flip_event = NULL;
6ee4d7fe SH	290	ipu_crtc->newfb = NULL;
f326f799 SH	291	}
f326f799 SH	292
d50141d8	293	static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
2872c807	294	u32 bus_format, int hsync_pin, int vsync_pin)
f326f799 SH	295	{
	296	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	297
2872c807	298	ipu_crtc->bus_format = bus_format;
2ea42608 PZ	299	ipu_crtc->di_hsync_pin = hsync_pin;
2ea42608 PZ	300	ipu_crtc->di_vsync_pin = vsync_pin;
f326f799	301
f326f799 SH	302	return 0;
	303	}
	304
	305	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	306	.enable_vblank = ipu_enable_vblank,
	307	.disable_vblank = ipu_disable_vblank,
	308	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	309	.crtc_funcs = &ipu_crtc_funcs,
	310	.crtc_helper_funcs = &ipu_helper_funcs,
	311	};
	312
	313	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	314	{
b8d181e4 PZ	315	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	316	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	317	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	318	ipu_di_put(ipu_crtc->di);
	319	}
	320
	321	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	322	struct ipu_client_platformdata *pdata)
	323	{
	324	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	325	int ret;
	326
f326f799 SH	327	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	328	if (IS_ERR(ipu_crtc->dc)) {
	329	ret = PTR_ERR(ipu_crtc->dc);
	330	goto err_out;
	331	}
	332
f326f799 SH	333	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	334	if (IS_ERR(ipu_crtc->di)) {
	335	ret = PTR_ERR(ipu_crtc->di);
	336	goto err_out;
	337	}
	338
f326f799 SH	339	return 0;
	340	err_out:
	341	ipu_put_resources(ipu_crtc);
	342
	343	return ret;
	344	}
	345
	346	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	347	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	348	{
47b1be5c	349	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	350	int dp = -EINVAL;
f326f799	351	int ret;
b8d181e4	352	int id;
f326f799 SH	353
	354	ret = ipu_get_resources(ipu_crtc, pdata);
	355	if (ret) {
	356	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	357	ret);
	358	return ret;
	359	}
	360
655b43cc PZ	361	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
655b43cc PZ	362	&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
f326f799 SH	363	if (ret) {
	364	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	365	goto err_put_resources;
	366	}
	367
b8d181e4 PZ	368	if (pdata->dp >= 0)
	369	dp = IPU_DP_FLOW_SYNC_BG;
	370	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
	371	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
	372	pdata->dma[0], dp, BIT(id), true);
	373	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	374	if (ret) {
	375	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	376	ret);
	377	goto err_remove_crtc;
	378	}
	379
	380	/* If this crtc is using the DP, add an overlay plane */
	381	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
	382	ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
	383	pdata->dma[1],
	384	IPU_DP_FLOW_SYNC_FG,
	385	BIT(id), false);
	386	if (IS_ERR(ipu_crtc->plane[1]))
	387	ipu_crtc->plane[1] = NULL;
	388	}
	389
	390	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	391	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	392	"imx_drm", ipu_crtc);
	393	if (ret < 0) {
	394	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
b8d181e4	395	goto err_put_plane_res;
47b1be5c PZ	396	}
47b1be5c PZ	397
f326f799 SH	398	return 0;
f326f799 SH	399
b8d181e4 PZ	400	err_put_plane_res:
	401	ipu_plane_put_resources(ipu_crtc->plane[0]);
	402	err_remove_crtc:
	403	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	404	err_put_resources:
	405	ipu_put_resources(ipu_crtc);
	406
	407	return ret;
	408	}
	409
655b43cc PZ	410	static struct device_node ipu_drm_get_port_by_id(struct device_node parent,
	411	int port_id)
	412	{
	413	struct device_node *port;
	414	int id, ret;
	415
	416	port = of_get_child_by_name(parent, "port");
	417	while (port) {
	418	ret = of_property_read_u32(port, "reg", &id);
	419	if (!ret && id == port_id)
	420	return port;
	421
	422	do {
	423	port = of_get_next_child(parent, port);
	424	if (!port)
	425	return NULL;
	426	} while (of_node_cmp(port->name, "port"));
	427	}
	428
	429	return NULL;
	430	}
	431
17b5001b	432	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	433	{
17b5001b	434	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	435	struct drm_device *drm = data;
f326f799 SH	436	struct ipu_crtc *ipu_crtc;
	437	int ret;
	438
17b5001b	439	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	440	if (!ipu_crtc)
	441	return -ENOMEM;
	442
17b5001b	443	ipu_crtc->dev = dev;
f326f799	444
32266b45	445	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	446	if (ret)
9a8f3f44 LW	447	return ret;
f326f799	448
17b5001b	449	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	450
	451	return 0;
	452	}
	453
17b5001b RK	454	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	455	void *data)
f326f799	456	{
17b5001b	457	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	458
	459	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	460
b8d181e4	461	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799	462	ipu_put_resources(ipu_crtc);
17b5001b RK	463	}
	464
	465	static const struct component_ops ipu_crtc_ops = {
	466	.bind = ipu_drm_bind,
	467	.unbind = ipu_drm_unbind,
	468	};
f326f799	469
17b5001b RK	470	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	471	{
655b43cc PZ	472	struct device *dev = &pdev->dev;
655b43cc PZ	473	struct ipu_client_platformdata *pdata = dev->platform_data;
17b5001b RK	474	int ret;
17b5001b RK	475
655b43cc	476	if (!dev->platform_data)
17b5001b RK	477	return -EINVAL;
17b5001b RK	478
655b43cc PZ	479	if (!dev->of_node) {
	480	/* Associate crtc device with the corresponding DI port node */
	481	dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
	482	pdata->di + 2);
	483	if (!dev->of_node) {
	484	dev_err(dev, "missing port@%d node in %s\n",
	485	pdata->di + 2, dev->parent->of_node->full_name);
	486	return -ENODEV;
	487	}
	488	}
	489
	490	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	491	if (ret)
	492	return ret;
	493
655b43cc	494	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	495	}
	496
	497	static int ipu_drm_remove(struct platform_device *pdev)
	498	{
	499	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	500	return 0;
	501	}
	502
	503	static struct platform_driver ipu_drm_driver = {
	504	.driver = {
	505	.name = "imx-ipuv3-crtc",
	506	},
	507	.probe = ipu_drm_probe,
99c28f10	508	.remove = ipu_drm_remove,
f326f799 SH	509	};
	510	module_platform_driver(ipu_drm_driver);
	511
	512	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	513	MODULE_DESCRIPTION(DRIVER_DESC);
	514	MODULE_LICENSE("GPL");
ce9c1cef	515	MODULE_ALIAS("platform:imx-ipuv3-crtc");