[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct ipu_crtc, base);
}

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);

	drm_crtc_vblank_off(crtc);
}

static void imx_drm_crtc_reset(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	if (crtc->state) {
		if (crtc->state->mode_blob)
			drm_property_unreference_blob(crtc->state->mode_blob);

		state = to_imx_crtc_state(crtc->state);
		memset(state, 0, sizeof(*state));
	} else {
		state = kzalloc(sizeof(*state), GFP_KERNEL);
		if (!state)
			return;
		crtc->state = &state->base;
	}

	state->base.crtc = crtc;
}

static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct imx_crtc_state *state;

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	WARN_ON(state->base.crtc != crtc);
	state->base.crtc = crtc;

	return &state->base;
}

static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
{
	__drm_atomic_helper_crtc_destroy_state(state);
	kfree(to_imx_crtc_state(state));
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = imx_drm_crtc_reset,
	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	.atomic_destroy_state = imx_drm_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	drm_crtc_handle_vblank(&ipu_crtc->base);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	drm_crtc_vblank_on(crtc);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc)
			encoder_types |= BIT(encoder->encoder_type);
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_crtc_state->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_crtc_state->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.disable = ipu_crtc_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799	23	#include <drm/drm_crtc_helper.h>
f326f799	24	#include <linux/clk.h>
b8d181e4	25	#include <linux/errno.h>
f326f799 SH	26	#include <drm/drm_gem_cma_helper.h>
	27	#include <drm/drm_fb_cma_helper.h>
	28
39b9004d	29	#include <video/imx-ipu-v3.h>
f326f799	30	#include "imx-drm.h"
b8d181e4	31	#include "ipuv3-plane.h"
f326f799 SH	32
	33	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	34
f326f799	35	struct ipu_crtc {
f326f799 SH	36	struct device *dev;
	37	struct drm_crtc base;
	38	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	39
	40	/* plane[0] is the full plane, plane[1] is the partial plane */
	41	struct ipu_plane *plane[2];
	42
f326f799	43	struct ipu_dc *dc;
f326f799	44	struct ipu_di *di;
f326f799	45	int irq;
f326f799 SH	46	};
f326f799 SH	47
3df07390 PZ	48	static inline struct ipu_crtc to_ipu_crtc(struct drm_crtc crtc)
	49	{
	50	return container_of(crtc, struct ipu_crtc, base);
	51	}
f326f799	52
f6e396e5	53	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	54	{
f6e396e5	55	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	56	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	57
1e6d486b	58	ipu_dc_enable(ipu);
c115edb8 PZ	59	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	60	ipu_di_enable(ipu_crtc->di);
f326f799 SH	61	}
f326f799 SH	62
f6e396e5	63	static void ipu_crtc_disable(struct drm_crtc *crtc)
f326f799	64	{
f6e396e5	65	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	66	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	67
f326f799	68	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	69	ipu_di_disable(ipu_crtc->di);
1e6d486b	70	ipu_dc_disable(ipu);
33f14235	71
5f2f9115 LY	72	spin_lock_irq(&crtc->dev->event_lock);
	73	if (crtc->state->event) {
	74	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	75	crtc->state->event = NULL;
	76	}
	77	spin_unlock_irq(&crtc->dev->event_lock);
a4744786 LS	78
a4744786 LS	79	drm_crtc_vblank_off(crtc);
f326f799 SH	80	}
f326f799 SH	81
49f98bc4 PZ	82	static void imx_drm_crtc_reset(struct drm_crtc *crtc)
	83	{
	84	struct imx_crtc_state *state;
	85
	86	if (crtc->state) {
	87	if (crtc->state->mode_blob)
	88	drm_property_unreference_blob(crtc->state->mode_blob);
	89
	90	state = to_imx_crtc_state(crtc->state);
	91	memset(state, 0, sizeof(*state));
	92	} else {
	93	state = kzalloc(sizeof(*state), GFP_KERNEL);
	94	if (!state)
	95	return;
	96	crtc->state = &state->base;
	97	}
	98
	99	state->base.crtc = crtc;
	100	}
	101
	102	static struct drm_crtc_state imx_drm_crtc_duplicate_state(struct drm_crtc crtc)
	103	{
	104	struct imx_crtc_state *state;
	105
	106	state = kzalloc(sizeof(*state), GFP_KERNEL);
	107	if (!state)
	108	return NULL;
	109
	110	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
	111
	112	WARN_ON(state->base.crtc != crtc);
	113	state->base.crtc = crtc;
	114
	115	return &state->base;
	116	}
	117
	118	static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
	119	struct drm_crtc_state *state)
	120	{
	121	__drm_atomic_helper_crtc_destroy_state(state);
	122	kfree(to_imx_crtc_state(state));
	123	}
	124
f326f799	125	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	126	.set_config = drm_atomic_helper_set_config,
f326f799	127	.destroy = drm_crtc_cleanup,
5f2f9115	128	.page_flip = drm_atomic_helper_page_flip,
49f98bc4 PZ	129	.reset = imx_drm_crtc_reset,
	130	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
	131	.atomic_destroy_state = imx_drm_crtc_destroy_state,
f326f799 SH	132	};
f326f799 SH	133
f326f799 SH	134	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	135	{
	136	struct ipu_crtc *ipu_crtc = dev_id;
	137
3ec2e506	138	drm_crtc_handle_vblank(&ipu_crtc->base);
f326f799	139
f326f799 SH	140	return IRQ_HANDLED;
	141	}
	142
	143	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	144	const struct drm_display_mode *mode,
	145	struct drm_display_mode *adjusted_mode)
	146	{
0c460a55 SL	147	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	148	struct videomode vm;
	149	int ret;
	150
	151	drm_display_mode_to_videomode(adjusted_mode, &vm);
	152
	153	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	154	if (ret)
	155	return false;
	156
33f14235 LY	157	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	158	return false;
	159
0c460a55 SL	160	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	161
f326f799 SH	162	return true;
	163	}
	164
33f14235 LY	165	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	166	struct drm_crtc_state *state)
	167	{
5f2f9115 LY	168	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	169
	170	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	171	return -EINVAL;
	172
33f14235 LY	173	return 0;
	174	}
	175
5f2f9115 LY	176	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	177	struct drm_crtc_state *old_crtc_state)
	178	{
a4744786 LS	179	drm_crtc_vblank_on(crtc);
a4744786 LS	180
5f2f9115 LY	181	spin_lock_irq(&crtc->dev->event_lock);
	182	if (crtc->state->event) {
	183	WARN_ON(drm_crtc_vblank_get(crtc));
	184	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	185	crtc->state->event = NULL;
	186	}
	187	spin_unlock_irq(&crtc->dev->event_lock);
	188	}
	189
33f14235 LY	190	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	191	{
	192	struct drm_device *dev = crtc->dev;
	193	struct drm_encoder *encoder;
	194	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	195	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
49f98bc4	196	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
33f14235 LY	197	struct ipu_di_signal_cfg sig_cfg = {};
	198	unsigned long encoder_types = 0;
	199
	200	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	201	mode->hdisplay);
	202	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	203	mode->vdisplay);
	204
032003c5	205	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49f98bc4	206	if (encoder->crtc == crtc)
33f14235	207	encoder_types \|= BIT(encoder->encoder_type);
032003c5	208	}
33f14235 LY	209
	210	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	211	__func__, encoder_types);
	212
	213	/*
	214	* If we have DAC or LDB, then we need the IPU DI clock to be
	215	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	216	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	217	*/
	218	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	219	BIT(DRM_MODE_ENCODER_LVDS)))
	220	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	221	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	222	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	223	else
	224	sig_cfg.clkflags = 0;
	225
49f98bc4	226	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	227	/* Default to driving pixel data on negative clock edges */
49f98bc4	228	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
33f14235	229	DRM_BUS_FLAG_PIXDATA_POSEDGE);
49f98bc4	230	sig_cfg.bus_format = imx_crtc_state->bus_format;
33f14235	231	sig_cfg.v_to_h_sync = 0;
49f98bc4 PZ	232	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
49f98bc4 PZ	233	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
33f14235 LY	234
	235	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	236
	237	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	238	mode->flags & DRM_MODE_FLAG_INTERLACE,
49f98bc4	239	imx_crtc_state->bus_format, mode->hdisplay);
33f14235	240	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	241	}
f326f799 SH	242
7ae847dd	243	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	244	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	245	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	246	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	247	.atomic_begin = ipu_crtc_atomic_begin,
f6e396e5 LY	248	.disable = ipu_crtc_disable,
f6e396e5 LY	249	.enable = ipu_crtc_enable,
f326f799 SH	250	};
	251
	252	static int ipu_enable_vblank(struct drm_crtc *crtc)
	253	{
411b0336 LS	254	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	255
	256	enable_irq(ipu_crtc->irq);
	257
f326f799 SH	258	return 0;
	259	}
	260
	261	static void ipu_disable_vblank(struct drm_crtc *crtc)
	262	{
411b0336 LS	263	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	264
	265	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	266	}
f326f799 SH	267
f326f799 SH	268	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	269	.enable_vblank = ipu_enable_vblank,
	270	.disable_vblank = ipu_disable_vblank,
f326f799 SH	271	.crtc_funcs = &ipu_crtc_funcs,
	272	.crtc_helper_funcs = &ipu_helper_funcs,
	273	};
	274
	275	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	276	{
b8d181e4 PZ	277	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	278	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	279	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	280	ipu_di_put(ipu_crtc->di);
	281	}
	282
	283	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	284	struct ipu_client_platformdata *pdata)
	285	{
	286	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	287	int ret;
	288
f326f799 SH	289	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	290	if (IS_ERR(ipu_crtc->dc)) {
	291	ret = PTR_ERR(ipu_crtc->dc);
	292	goto err_out;
	293	}
	294
f326f799 SH	295	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	296	if (IS_ERR(ipu_crtc->di)) {
	297	ret = PTR_ERR(ipu_crtc->di);
	298	goto err_out;
	299	}
	300
f326f799 SH	301	return 0;
	302	err_out:
	303	ipu_put_resources(ipu_crtc);
	304
	305	return ret;
	306	}
	307
	308	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	309	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	310	{
47b1be5c	311	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	312	int dp = -EINVAL;
f326f799 SH	313	int ret;
	314
	315	ret = ipu_get_resources(ipu_crtc, pdata);
	316	if (ret) {
	317	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	318	ret);
	319	return ret;
	320	}
	321
43895599 PZ	322	if (pdata->dp >= 0)
	323	dp = IPU_DP_FLOW_SYNC_BG;
	324	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	325	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	326	if (IS_ERR(ipu_crtc->plane[0])) {
	327	ret = PTR_ERR(ipu_crtc->plane[0]);
	328	goto err_put_resources;
	329	}
43895599	330
655b43cc	331	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	332	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	333	pdata->of_node);
f326f799 SH	334	if (ret) {
	335	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	336	goto err_put_resources;
	337	}
	338
b8d181e4 PZ	339	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	340	if (ret) {
	341	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	342	ret);
	343	goto err_remove_crtc;
	344	}
	345
	346	/* If this crtc is using the DP, add an overlay plane */
	347	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	348	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	349	IPU_DP_FLOW_SYNC_FG,
	350	drm_crtc_mask(&ipu_crtc->base),
	351	DRM_PLANE_TYPE_OVERLAY);
33f14235	352	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	353	ipu_crtc->plane[1] = NULL;
33f14235 LY	354	} else {
	355	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	356	if (ret) {
	357	dev_err(ipu_crtc->dev, "getting plane 1 "
	358	"resources failed with %d.\n", ret);
	359	goto err_put_plane0_res;
	360	}
	361	}
b8d181e4 PZ	362	}
	363
	364	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	365	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	366	"imx_drm", ipu_crtc);
	367	if (ret < 0) {
	368	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	369	goto err_put_plane1_res;
47b1be5c	370	}
411b0336 LS	371	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	372	disable_irq(ipu_crtc->irq);
47b1be5c	373
f326f799 SH	374	return 0;
f326f799 SH	375
33f14235 LY	376	err_put_plane1_res:
	377	if (ipu_crtc->plane[1])
	378	ipu_plane_put_resources(ipu_crtc->plane[1]);
	379	err_put_plane0_res:
b8d181e4 PZ	380	ipu_plane_put_resources(ipu_crtc->plane[0]);
	381	err_remove_crtc:
	382	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	383	err_put_resources:
	384	ipu_put_resources(ipu_crtc);
	385
	386	return ret;
	387	}
	388
17b5001b	389	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	390	{
17b5001b	391	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	392	struct drm_device *drm = data;
f326f799 SH	393	struct ipu_crtc *ipu_crtc;
	394	int ret;
	395
17b5001b	396	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	397	if (!ipu_crtc)
	398	return -ENOMEM;
	399
17b5001b	400	ipu_crtc->dev = dev;
f326f799	401
32266b45	402	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	403	if (ret)
9a8f3f44 LW	404	return ret;
f326f799	405
17b5001b	406	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	407
	408	return 0;
	409	}
	410
17b5001b RK	411	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	412	void *data)
f326f799	413	{
17b5001b	414	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	415
	416	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	417
	418	ipu_put_resources(ipu_crtc);
33f14235 LY	419	if (ipu_crtc->plane[1])
	420	ipu_plane_put_resources(ipu_crtc->plane[1]);
	421	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	422	}
	423
	424	static const struct component_ops ipu_crtc_ops = {
	425	.bind = ipu_drm_bind,
	426	.unbind = ipu_drm_unbind,
	427	};
f326f799	428
17b5001b RK	429	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	430	{
655b43cc	431	struct device *dev = &pdev->dev;
17b5001b RK	432	int ret;
17b5001b RK	433
655b43cc	434	if (!dev->platform_data)
17b5001b RK	435	return -EINVAL;
17b5001b RK	436
655b43cc	437	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	438	if (ret)
	439	return ret;
	440
655b43cc	441	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	442	}
	443
	444	static int ipu_drm_remove(struct platform_device *pdev)
	445	{
	446	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	447	return 0;
	448	}
	449
	450	static struct platform_driver ipu_drm_driver = {
	451	.driver = {
	452	.name = "imx-ipuv3-crtc",
	453	},
	454	.probe = ipu_drm_probe,
99c28f10	455	.remove = ipu_drm_remove,
f326f799 SH	456	};
	457	module_platform_driver(ipu_drm_driver);
	458
	459	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	460	MODULE_DESCRIPTION(DRIVER_DESC);
	461	MODULE_LICENSE("GPL");
ce9c1cef	462	MODULE_ALIAS("platform:imx-ipuv3-crtc");