[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			irq;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static void ipu_crtc_enable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_enable(ipu);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_di_enable(ipu_crtc->di);
}

static void ipu_crtc_disable(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);

	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);
	ipu_dc_disable(ipu);

	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		drm_crtc_send_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_atomic_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct videomode vm;
	int ret;

	drm_display_mode_to_videomode(adjusted_mode, &vm);

	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	if (ret)
		return false;

	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
		return false;

	drm_display_mode_from_videomode(&vm, adjusted_mode);

	return true;
}

static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
				 struct drm_crtc_state *state)
{
	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);

	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
		return -EINVAL;

	return 0;
}

static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_crtc_state *old_crtc_state)
{
	spin_lock_irq(&crtc->dev->event_lock);
	if (crtc->state->event) {
		WARN_ON(drm_crtc_vblank_get(crtc));
		drm_crtc_arm_vblank_event(crtc, crtc->state->event);
		crtc->state->event = NULL;
	}
	spin_unlock_irq(&crtc->dev->event_lock);
}

static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;
	struct imx_drm_encoder *imx_encoder = NULL;
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	struct ipu_di_signal_cfg sig_cfg = {};
	unsigned long encoder_types = 0;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			encoder_types |= BIT(encoder->encoder_type);
			imx_encoder = enc_to_imx_enc(encoder);
		}
	}

	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
		__func__, encoder_types);

	/*
	 * If we have DAC or LDB, then we need the IPU DI clock to be
	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
	 */
	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
			     BIT(DRM_MODE_ENCODER_LVDS)))
		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	else
		sig_cfg.clkflags = 0;

	sig_cfg.enable_pol = !(imx_encoder->bus_flags & DRM_BUS_FLAG_DE_LOW);
	/* Default to driving pixel data on negative clock edges */
	sig_cfg.clk_pol = !!(imx_encoder->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);
	sig_cfg.bus_format = imx_encoder->bus_format;
	sig_cfg.v_to_h_sync = 0;
	sig_cfg.hsync_pin = imx_encoder->di_hsync_pin;
	sig_cfg.vsync_pin = imx_encoder->di_vsync_pin;

	drm_display_mode_to_videomode(mode, &sig_cfg.mode);

	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
			 mode->flags & DRM_MODE_FLAG_INTERLACE,
			 imx_encoder->bus_format, mode->hdisplay);
	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
}

static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set_nofb = ipu_crtc_mode_set_nofb,
	.atomic_check = ipu_crtc_atomic_check,
	.atomic_begin = ipu_crtc_atomic_begin,
	.disable = ipu_crtc_disable,
	.enable = ipu_crtc_enable,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq_nosync(ipu_crtc->irq);
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
					    DRM_PLANE_TYPE_PRIMARY);
	if (IS_ERR(ipu_crtc->plane[0])) {
		ret = PTR_ERR(ipu_crtc->plane[0]);
		goto err_put_resources;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
			pdata->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
						IPU_DP_FLOW_SYNC_FG,
						drm_crtc_mask(&ipu_crtc->base),
						DRM_PLANE_TYPE_OVERLAY);
		if (IS_ERR(ipu_crtc->plane[1])) {
			ipu_crtc->plane[1] = NULL;
		} else {
			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
			if (ret) {
				dev_err(ipu_crtc->dev, "getting plane 1 "
					"resources failed with %d.\n", ret);
				goto err_put_plane0_res;
			}
		}
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane1_res;
	}
	/* Only enable IRQ when we actually need it to trigger work. */
	disable_irq(ipu_crtc->irq);

	return 0;

err_put_plane1_res:
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
err_put_plane0_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);
	if (ipu_crtc->plane[1])
		ipu_plane_put_resources(ipu_crtc->plane[1]);
	ipu_plane_put_resources(ipu_crtc->plane[0]);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
f326f799	14	*/
17b5001b	15	#include <linux/component.h>
f326f799 SH	16	#include <linux/module.h>
	17	#include <linux/export.h>
	18	#include <linux/device.h>
	19	#include <linux/platform_device.h>
	20	#include <drm/drmP.h>
ae2531ab	21	#include <drm/drm_atomic.h>
255c35f8	22	#include <drm/drm_atomic_helper.h>
f326f799 SH	23	#include <drm/drm_crtc_helper.h>
	24	#include <linux/fb.h>
	25	#include <linux/clk.h>
b8d181e4	26	#include <linux/errno.h>
f326f799 SH	27	#include <drm/drm_gem_cma_helper.h>
	28	#include <drm/drm_fb_cma_helper.h>
	29
39b9004d	30	#include <video/imx-ipu-v3.h>
f326f799	31	#include "imx-drm.h"
b8d181e4	32	#include "ipuv3-plane.h"
f326f799 SH	33
	34	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	35
f326f799	36	struct ipu_crtc {
f326f799 SH	37	struct device *dev;
	38	struct drm_crtc base;
	39	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	40
	41	/* plane[0] is the full plane, plane[1] is the partial plane */
	42	struct ipu_plane *plane[2];
	43
f326f799	44	struct ipu_dc *dc;
f326f799	45	struct ipu_di *di;
f326f799	46	int irq;
f326f799 SH	47	};
	48
	49	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	50
f6e396e5	51	static void ipu_crtc_enable(struct drm_crtc *crtc)
f326f799	52	{
f6e396e5	53	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b PZ	54	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
1e6d486b PZ	55
1e6d486b	56	ipu_dc_enable(ipu);
c115edb8 PZ	57	ipu_dc_enable_channel(ipu_crtc->dc);
c115edb8 PZ	58	ipu_di_enable(ipu_crtc->di);
f326f799 SH	59	}
f326f799 SH	60
f6e396e5	61	static void ipu_crtc_disable(struct drm_crtc *crtc)
f326f799	62	{
f6e396e5	63	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
1e6d486b	64	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799	65
f326f799	66	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799	67	ipu_di_disable(ipu_crtc->di);
1e6d486b	68	ipu_dc_disable(ipu);
33f14235	69
5f2f9115 LY	70	spin_lock_irq(&crtc->dev->event_lock);
	71	if (crtc->state->event) {
	72	drm_crtc_send_vblank_event(crtc, crtc->state->event);
	73	crtc->state->event = NULL;
	74	}
	75	spin_unlock_irq(&crtc->dev->event_lock);
f326f799 SH	76	}
f326f799 SH	77
f326f799	78	static const struct drm_crtc_funcs ipu_crtc_funcs = {
5f2f9115	79	.set_config = drm_atomic_helper_set_config,
f326f799	80	.destroy = drm_crtc_cleanup,
5f2f9115	81	.page_flip = drm_atomic_helper_page_flip,
255c35f8 LY	82	.reset = drm_atomic_helper_crtc_reset,
	83	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	84	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
f326f799 SH	85	};
f326f799 SH	86
f326f799 SH	87	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	88	{
	89	struct ipu_crtc *ipu_crtc = dev_id;
	90
	91	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	92
f326f799 SH	93	return IRQ_HANDLED;
	94	}
	95
	96	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	97	const struct drm_display_mode *mode,
	98	struct drm_display_mode *adjusted_mode)
	99	{
0c460a55 SL	100	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	101	struct videomode vm;
	102	int ret;
	103
	104	drm_display_mode_to_videomode(adjusted_mode, &vm);
	105
	106	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
	107	if (ret)
	108	return false;
	109
33f14235 LY	110	if ((vm.vsync_len == 0) \|\| (vm.hsync_len == 0))
	111	return false;
	112
0c460a55 SL	113	drm_display_mode_from_videomode(&vm, adjusted_mode);
0c460a55 SL	114
f326f799 SH	115	return true;
	116	}
	117
33f14235 LY	118	static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
	119	struct drm_crtc_state *state)
	120	{
5f2f9115 LY	121	u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
	122
	123	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
	124	return -EINVAL;
	125
33f14235 LY	126	return 0;
	127	}
	128
5f2f9115 LY	129	static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
	130	struct drm_crtc_state *old_crtc_state)
	131	{
	132	spin_lock_irq(&crtc->dev->event_lock);
	133	if (crtc->state->event) {
	134	WARN_ON(drm_crtc_vblank_get(crtc));
	135	drm_crtc_arm_vblank_event(crtc, crtc->state->event);
	136	crtc->state->event = NULL;
	137	}
	138	spin_unlock_irq(&crtc->dev->event_lock);
	139	}
	140
33f14235 LY	141	static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	142	{
	143	struct drm_device *dev = crtc->dev;
	144	struct drm_encoder *encoder;
032003c5	145	struct imx_drm_encoder *imx_encoder = NULL;
33f14235 LY	146	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	147	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	148	struct ipu_di_signal_cfg sig_cfg = {};
	149	unsigned long encoder_types = 0;
	150
	151	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	152	mode->hdisplay);
	153	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	154	mode->vdisplay);
	155
032003c5 LY	156	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
032003c5 LY	157	if (encoder->crtc == crtc) {
33f14235	158	encoder_types \|= BIT(encoder->encoder_type);
032003c5 LY	159	imx_encoder = enc_to_imx_enc(encoder);
	160	}
	161	}
33f14235 LY	162
	163	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
	164	__func__, encoder_types);
	165
	166	/*
	167	* If we have DAC or LDB, then we need the IPU DI clock to be
	168	* the same as the LDB DI clock. For TVDAC, derive the IPU DI
	169	* clock from 27 MHz TVE_DI clock, but allow to divide it.
	170	*/
	171	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) \|
	172	BIT(DRM_MODE_ENCODER_LVDS)))
	173	sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC \| IPU_DI_CLKMODE_EXT;
	174	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
	175	sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
	176	else
	177	sig_cfg.clkflags = 0;
	178
032003c5	179	sig_cfg.enable_pol = !(imx_encoder->bus_flags & DRM_BUS_FLAG_DE_LOW);
33f14235	180	/* Default to driving pixel data on negative clock edges */
032003c5	181	sig_cfg.clk_pol = !!(imx_encoder->bus_flags &
33f14235	182	DRM_BUS_FLAG_PIXDATA_POSEDGE);
032003c5	183	sig_cfg.bus_format = imx_encoder->bus_format;
33f14235	184	sig_cfg.v_to_h_sync = 0;
032003c5 LY	185	sig_cfg.hsync_pin = imx_encoder->di_hsync_pin;
032003c5 LY	186	sig_cfg.vsync_pin = imx_encoder->di_vsync_pin;
33f14235 LY	187
	188	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
	189
	190	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
	191	mode->flags & DRM_MODE_FLAG_INTERLACE,
032003c5	192	imx_encoder->bus_format, mode->hdisplay);
33f14235	193	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
f326f799 SH	194	}
f326f799 SH	195
7ae847dd	196	static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
f326f799	197	.mode_fixup = ipu_crtc_mode_fixup,
33f14235	198	.mode_set_nofb = ipu_crtc_mode_set_nofb,
33f14235	199	.atomic_check = ipu_crtc_atomic_check,
5f2f9115	200	.atomic_begin = ipu_crtc_atomic_begin,
f6e396e5 LY	201	.disable = ipu_crtc_disable,
f6e396e5 LY	202	.enable = ipu_crtc_enable,
f326f799 SH	203	};
	204
	205	static int ipu_enable_vblank(struct drm_crtc *crtc)
	206	{
411b0336 LS	207	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	208
	209	enable_irq(ipu_crtc->irq);
	210
f326f799 SH	211	return 0;
	212	}
	213
	214	static void ipu_disable_vblank(struct drm_crtc *crtc)
	215	{
411b0336 LS	216	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	217
	218	disable_irq_nosync(ipu_crtc->irq);
f326f799 SH	219	}
f326f799 SH	220
f326f799 SH	221	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	222	.enable_vblank = ipu_enable_vblank,
	223	.disable_vblank = ipu_disable_vblank,
f326f799 SH	224	.crtc_funcs = &ipu_crtc_funcs,
	225	.crtc_helper_funcs = &ipu_helper_funcs,
	226	};
	227
	228	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	229	{
b8d181e4 PZ	230	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	231	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	232	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	233	ipu_di_put(ipu_crtc->di);
	234	}
	235
	236	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	237	struct ipu_client_platformdata *pdata)
	238	{
	239	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	240	int ret;
	241
f326f799 SH	242	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	243	if (IS_ERR(ipu_crtc->dc)) {
	244	ret = PTR_ERR(ipu_crtc->dc);
	245	goto err_out;
	246	}
	247
f326f799 SH	248	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	249	if (IS_ERR(ipu_crtc->di)) {
	250	ret = PTR_ERR(ipu_crtc->di);
	251	goto err_out;
	252	}
	253
f326f799 SH	254	return 0;
	255	err_out:
	256	ipu_put_resources(ipu_crtc);
	257
	258	return ret;
	259	}
	260
	261	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	262	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	263	{
47b1be5c	264	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	265	int dp = -EINVAL;
f326f799 SH	266	int ret;
	267
	268	ret = ipu_get_resources(ipu_crtc, pdata);
	269	if (ret) {
	270	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	271	ret);
	272	return ret;
	273	}
	274
43895599 PZ	275	if (pdata->dp >= 0)
	276	dp = IPU_DP_FLOW_SYNC_BG;
	277	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
	278	DRM_PLANE_TYPE_PRIMARY);
a7ed3c2b LY	279	if (IS_ERR(ipu_crtc->plane[0])) {
	280	ret = PTR_ERR(ipu_crtc->plane[0]);
	281	goto err_put_resources;
	282	}
43895599	283
655b43cc	284	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
43895599	285	&ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
310944d1	286	pdata->of_node);
f326f799 SH	287	if (ret) {
	288	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	289	goto err_put_resources;
	290	}
	291
b8d181e4 PZ	292	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	293	if (ret) {
	294	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	295	ret);
	296	goto err_remove_crtc;
	297	}
	298
	299	/* If this crtc is using the DP, add an overlay plane */
	300	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
43895599 PZ	301	ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
	302	IPU_DP_FLOW_SYNC_FG,
	303	drm_crtc_mask(&ipu_crtc->base),
	304	DRM_PLANE_TYPE_OVERLAY);
33f14235	305	if (IS_ERR(ipu_crtc->plane[1])) {
b8d181e4	306	ipu_crtc->plane[1] = NULL;
33f14235 LY	307	} else {
	308	ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
	309	if (ret) {
	310	dev_err(ipu_crtc->dev, "getting plane 1 "
	311	"resources failed with %d.\n", ret);
	312	goto err_put_plane0_res;
	313	}
	314	}
b8d181e4 PZ	315	}
	316
	317	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	318	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	319	"imx_drm", ipu_crtc);
	320	if (ret < 0) {
	321	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
33f14235	322	goto err_put_plane1_res;
47b1be5c	323	}
411b0336 LS	324	/* Only enable IRQ when we actually need it to trigger work. */
411b0336 LS	325	disable_irq(ipu_crtc->irq);
47b1be5c	326
f326f799 SH	327	return 0;
f326f799 SH	328
33f14235 LY	329	err_put_plane1_res:
	330	if (ipu_crtc->plane[1])
	331	ipu_plane_put_resources(ipu_crtc->plane[1]);
	332	err_put_plane0_res:
b8d181e4 PZ	333	ipu_plane_put_resources(ipu_crtc->plane[0]);
	334	err_remove_crtc:
	335	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	336	err_put_resources:
	337	ipu_put_resources(ipu_crtc);
	338
	339	return ret;
	340	}
	341
17b5001b	342	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	343	{
17b5001b	344	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	345	struct drm_device *drm = data;
f326f799 SH	346	struct ipu_crtc *ipu_crtc;
	347	int ret;
	348
17b5001b	349	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	350	if (!ipu_crtc)
	351	return -ENOMEM;
	352
17b5001b	353	ipu_crtc->dev = dev;
f326f799	354
32266b45	355	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	356	if (ret)
9a8f3f44 LW	357	return ret;
f326f799	358
17b5001b	359	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	360
	361	return 0;
	362	}
	363
17b5001b RK	364	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	365	void *data)
f326f799	366	{
17b5001b	367	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	368
	369	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	370
	371	ipu_put_resources(ipu_crtc);
33f14235 LY	372	if (ipu_crtc->plane[1])
	373	ipu_plane_put_resources(ipu_crtc->plane[1]);
	374	ipu_plane_put_resources(ipu_crtc->plane[0]);
17b5001b RK	375	}
	376
	377	static const struct component_ops ipu_crtc_ops = {
	378	.bind = ipu_drm_bind,
	379	.unbind = ipu_drm_unbind,
	380	};
f326f799	381
17b5001b RK	382	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	383	{
655b43cc	384	struct device *dev = &pdev->dev;
17b5001b RK	385	int ret;
17b5001b RK	386
655b43cc	387	if (!dev->platform_data)
17b5001b RK	388	return -EINVAL;
17b5001b RK	389
655b43cc	390	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	391	if (ret)
	392	return ret;
	393
655b43cc	394	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	395	}
	396
	397	static int ipu_drm_remove(struct platform_device *pdev)
	398	{
	399	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	400	return 0;
	401	}
	402
	403	static struct platform_driver ipu_drm_driver = {
	404	.driver = {
	405	.name = "imx-ipuv3-crtc",
	406	},
	407	.probe = ipu_drm_probe,
99c28f10	408	.remove = ipu_drm_remove,
f326f799 SH	409	};
	410	module_platform_driver(ipu_drm_driver);
	411
	412	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	413	MODULE_DESCRIPTION(DRIVER_DESC);
	414	MODULE_LICENSE("GPL");
ce9c1cef	415	MODULE_ALIAS("platform:imx-ipuv3-crtc");