[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "video/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_ARGB1555,
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_ABGR1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_RGBA5551,
	DRM_FORMAT_BGRA5551,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
}

static inline int calc_bandwidth(int width, int height, unsigned int vref)
{
	return width * height * vref;
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct drm_gem_cma_object *cma_obj;
	unsigned long eba;
	int active;

	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	if (!cma_obj) {
		DRM_DEBUG_KMS("entry is null.\n");
		return -EFAULT;
	}

	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
		&cma_obj->paddr, x, y);

	eba = cma_obj->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;

	if (ipu_plane->enabled) {
		active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
		ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	} else {
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	}

	/* cache offsets for subsequent pageflips */
	ipu_plane->x = x;
	ipu_plane->y = y;

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h, bool interlaced)
{
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	/* clip to crtc bounds */
	if (crtc_x < 0) {
		if (-crtc_x > crtc_w)
			return -EINVAL;
		src_x += -crtc_x;
		src_w -= -crtc_x;
		crtc_w -= -crtc_x;
		crtc_x = 0;
	}
	if (crtc_y < 0) {
		if (-crtc_y > crtc_h)
			return -EINVAL;
		src_y += -crtc_y;
		src_h -= -crtc_y;
		crtc_h -= -crtc_y;
		crtc_y = 0;
	}
	if (crtc_x + crtc_w > mode->hdisplay) {
		if (crtc_x > mode->hdisplay)
			return -EINVAL;
		crtc_w = mode->hdisplay - crtc_x;
		src_w = crtc_w;
	}
	if (crtc_y + crtc_h > mode->vdisplay) {
		if (crtc_y > mode->vdisplay)
			return -EINVAL;
		crtc_h = mode->vdisplay - crtc_y;
		src_h = crtc_h;
	}
	/* full plane minimum width is 13 pixels */
	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	/*
	 * since we cannot touch active IDMAC channels, we do not support
	 * resizing the enabled plane or changing its format
	 */
	if (ipu_plane->enabled) {
		if (src_w != ipu_plane->w || src_h != ipu_plane->h ||
		    fb->pixel_format != ipu_plane->base.fb->pixel_format)
			return -EINVAL;

		return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	}

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		/* Enable local alpha on partial plane */
		switch (fb->pixel_format) {
		case DRM_FORMAT_ARGB1555:
		case DRM_FORMAT_ABGR1555:
		case DRM_FORMAT_RGBA5551:
		case DRM_FORMAT_BGRA5551:
		case DRM_FORMAT_ARGB8888:
		case DRM_FORMAT_ABGR8888:
			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
			break;
		default:
			break;
		}
	}

	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	if (ret) {
		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
			calc_bandwidth(crtc_w, crtc_h,
				       calc_vref(mode)), 64);
	if (ret) {
		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
		return ret;
	}

	ipu_cpmem_zero(ipu_plane->ipu_ch);
	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;
	if (interlaced)
		ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);

	ipu_plane->w = src_w;
	ipu_plane->h = src_h;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	if (ipu_plane->dp)
		ipu_dp_enable(ipu_plane->ipu);
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
	if (ipu_plane->dp)
		ipu_dp_disable(ipu_plane->ipu);
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
			false);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);
	plane->crtc = crtc;

	if (!ipu_plane->enabled)
		ipu_plane_enable(ipu_plane);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	if (ipu_plane->enabled)
		ipu_plane_disable(ipu_plane);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 bool priv)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
			     &ipu_plane_funcs, ipu_plane_formats,
			     ARRAY_SIZE(ipu_plane_formats),
			     priv);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
39b9004d	20	#include "video/imx-ipu-v3.h"
b8d181e4 PZ	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
c639a1cf	26	DRM_FORMAT_ARGB1555,
b8d181e4	27	DRM_FORMAT_XRGB1555,
c639a1cf	28	DRM_FORMAT_ABGR1555,
b8d181e4	29	DRM_FORMAT_XBGR1555,
c639a1cf PZ	30	DRM_FORMAT_RGBA5551,
c639a1cf PZ	31	DRM_FORMAT_BGRA5551,
b8d181e4 PZ	32	DRM_FORMAT_ARGB8888,
	33	DRM_FORMAT_XRGB8888,
	34	DRM_FORMAT_ABGR8888,
	35	DRM_FORMAT_XBGR8888,
	36	DRM_FORMAT_YUYV,
	37	DRM_FORMAT_YVYU,
	38	DRM_FORMAT_YUV420,
	39	DRM_FORMAT_YVU420,
	40	};
	41
	42	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	43	{
	44	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	45	IPU_IRQ_EOF);
	46	}
	47
	48	static int calc_vref(struct drm_display_mode *mode)
	49	{
	50	unsigned long htotal, vtotal;
	51
	52	htotal = mode->htotal;
	53	vtotal = mode->vtotal;
	54
	55	if (!htotal \|\| !vtotal)
	56	return 60;
	57
	58	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
	59	}
	60
	61	static inline int calc_bandwidth(int width, int height, unsigned int vref)
	62	{
	63	return width * height * vref;
	64	}
	65
	66	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	67	int x, int y)
	68	{
b8d181e4	69	struct drm_gem_cma_object *cma_obj;
ee2e072e	70	unsigned long eba;
356f9524	71	int active;
b8d181e4 PZ	72
	73	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	74	if (!cma_obj) {
38821e64	75	DRM_DEBUG_KMS("entry is null.\n");
b8d181e4 PZ	76	return -EFAULT;
	77	}
	78
18589738 FE	79	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
18589738 FE	80	&cma_obj->paddr, x, y);
b8d181e4	81
bc2b067a LS	82	eba = cma_obj->paddr + fb->offsets[0] +
bc2b067a LS	83	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
356f9524 PZ	84
	85	if (ipu_plane->enabled) {
	86	active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
	87	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
	88	ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	89	} else {
	90	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
	91	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	92	}
b8d181e4	93
32f71106 LS	94	/* cache offsets for subsequent pageflips */
	95	ipu_plane->x = x;
	96	ipu_plane->y = y;
	97
b8d181e4 PZ	98	return 0;
	99	}
	100
	101	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	102	struct drm_display_mode *mode,
	103	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	104	unsigned int crtc_w, unsigned int crtc_h,
	105	uint32_t src_x, uint32_t src_y,
dd7fa6d8	106	uint32_t src_w, uint32_t src_h, bool interlaced)
b8d181e4	107	{
b8d181e4 PZ	108	struct device *dev = ipu_plane->base.dev->dev;
	109	int ret;
	110
	111	/* no scaling */
	112	if (src_w != crtc_w \|\| src_h != crtc_h)
	113	return -EINVAL;
	114
	115	/* clip to crtc bounds */
	116	if (crtc_x < 0) {
	117	if (-crtc_x > crtc_w)
	118	return -EINVAL;
	119	src_x += -crtc_x;
	120	src_w -= -crtc_x;
	121	crtc_w -= -crtc_x;
	122	crtc_x = 0;
	123	}
	124	if (crtc_y < 0) {
	125	if (-crtc_y > crtc_h)
	126	return -EINVAL;
	127	src_y += -crtc_y;
	128	src_h -= -crtc_y;
	129	crtc_h -= -crtc_y;
	130	crtc_y = 0;
	131	}
	132	if (crtc_x + crtc_w > mode->hdisplay) {
	133	if (crtc_x > mode->hdisplay)
	134	return -EINVAL;
	135	crtc_w = mode->hdisplay - crtc_x;
	136	src_w = crtc_w;
	137	}
	138	if (crtc_y + crtc_h > mode->vdisplay) {
	139	if (crtc_y > mode->vdisplay)
	140	return -EINVAL;
	141	crtc_h = mode->vdisplay - crtc_y;
	142	src_h = crtc_h;
	143	}
	144	/* full plane minimum width is 13 pixels */
	145	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
	146	return -EINVAL;
	147	if (crtc_h < 2)
	148	return -EINVAL;
	149
9a666030 PZ	150	/*
	151	* since we cannot touch active IDMAC channels, we do not support
	152	* resizing the enabled plane or changing its format
	153	*/
	154	if (ipu_plane->enabled) {
	155	if (src_w != ipu_plane->w \|\| src_h != ipu_plane->h \|\|
	156	fb->pixel_format != ipu_plane->base.fb->pixel_format)
	157	return -EINVAL;
	158
	159	return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	160	}
	161
b8d181e4 PZ	162	switch (ipu_plane->dp_flow) {
	163	case IPU_DP_FLOW_SYNC_BG:
	164	ret = ipu_dp_setup_channel(ipu_plane->dp,
	165	IPUV3_COLORSPACE_RGB,
	166	IPUV3_COLORSPACE_RGB);
	167	if (ret) {
	168	dev_err(dev,
	169	"initializing display processor failed with %d\n",
	170	ret);
	171	return ret;
	172	}
e6245fc7	173	ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
b8d181e4 PZ	174	break;
	175	case IPU_DP_FLOW_SYNC_FG:
	176	ipu_dp_setup_channel(ipu_plane->dp,
	177	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
	178	IPUV3_COLORSPACE_UNKNOWN);
	179	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
e6245fc7 PZ	180	/* Enable local alpha on partial plane */
e6245fc7 PZ	181	switch (fb->pixel_format) {
c639a1cf PZ	182	case DRM_FORMAT_ARGB1555:
	183	case DRM_FORMAT_ABGR1555:
	184	case DRM_FORMAT_RGBA5551:
	185	case DRM_FORMAT_BGRA5551:
e6245fc7 PZ	186	case DRM_FORMAT_ARGB8888:
	187	case DRM_FORMAT_ABGR8888:
	188	ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
	189	break;
	190	default:
	191	break;
	192	}
b8d181e4 PZ	193	}
	194
	195	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	196	if (ret) {
	197	dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
	198	return ret;
	199	}
	200
	201	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
	202	calc_bandwidth(crtc_w, crtc_h,
	203	calc_vref(mode)), 64);
	204	if (ret) {
	205	dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
	206	return ret;
	207	}
	208
2eb671c4 SL	209	ipu_cpmem_zero(ipu_plane->ipu_ch);
	210	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	211	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
b8d181e4 PZ	212	if (ret < 0) {
	213	dev_err(dev, "unsupported pixel format 0x%08x\n",
	214	fb->pixel_format);
	215	return ret;
	216	}
	217	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
356f9524	218	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
7cd9bebe	219	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4 PZ	220
	221	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	222	if (ret < 0)
	223	return ret;
dd7fa6d8 PZ	224	if (interlaced)
dd7fa6d8 PZ	225	ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4	226
9a666030 PZ	227	ipu_plane->w = src_w;
	228	ipu_plane->h = src_h;
	229
b8d181e4 PZ	230	return 0;
	231	}
	232
	233	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
	234	{
	235	if (!IS_ERR_OR_NULL(ipu_plane->dp))
	236	ipu_dp_put(ipu_plane->dp);
	237	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
	238	ipu_dmfc_put(ipu_plane->dmfc);
	239	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
	240	ipu_idmac_put(ipu_plane->ipu_ch);
	241	}
	242
	243	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
	244	{
	245	int ret;
	246
	247	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	248	if (IS_ERR(ipu_plane->ipu_ch)) {
	249	ret = PTR_ERR(ipu_plane->ipu_ch);
	250	DRM_ERROR("failed to get idmac channel: %d\n", ret);
	251	return ret;
	252	}
	253
	254	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	255	if (IS_ERR(ipu_plane->dmfc)) {
	256	ret = PTR_ERR(ipu_plane->dmfc);
	257	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
	258	goto err_out;
	259	}
	260
	261	if (ipu_plane->dp_flow >= 0) {
	262	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
	263	if (IS_ERR(ipu_plane->dp)) {
	264	ret = PTR_ERR(ipu_plane->dp);
	265	DRM_ERROR("failed to get dp flow: %d\n", ret);
	266	goto err_out;
	267	}
	268	}
	269
	270	return 0;
	271	err_out:
	272	ipu_plane_put_resources(ipu_plane);
	273
	274	return ret;
	275	}
	276
	277	void ipu_plane_enable(struct ipu_plane *ipu_plane)
	278	{
285bbb01 PZ	279	if (ipu_plane->dp)
285bbb01 PZ	280	ipu_dp_enable(ipu_plane->ipu);
b8d181e4 PZ	281	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	282	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	283	if (ipu_plane->dp)
	284	ipu_dp_enable_channel(ipu_plane->dp);
	285
	286	ipu_plane->enabled = true;
	287	}
	288
	289	void ipu_plane_disable(struct ipu_plane *ipu_plane)
	290	{
	291	ipu_plane->enabled = false;
	292
	293	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
	294
	295	if (ipu_plane->dp)
	296	ipu_dp_disable_channel(ipu_plane->dp);
	297	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	298	ipu_dmfc_disable_channel(ipu_plane->dmfc);
285bbb01 PZ	299	if (ipu_plane->dp)
285bbb01 PZ	300	ipu_dp_disable(ipu_plane->ipu);
b8d181e4 PZ	301	}
b8d181e4 PZ	302
b8d181e4 PZ	303	/*
	304	* drm_plane API
	305	*/
	306
	307	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	308	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	309	unsigned int crtc_w, unsigned int crtc_h,
	310	uint32_t src_x, uint32_t src_y,
	311	uint32_t src_w, uint32_t src_h)
	312	{
	313	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	314	int ret = 0;
	315
	316	DRM_DEBUG_KMS("plane - %p\n", plane);
	317
	318	if (!ipu_plane->enabled)
	319	ret = ipu_plane_get_resources(ipu_plane);
	320	if (ret < 0)
	321	return ret;
	322
	323	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
	324	crtc_x, crtc_y, crtc_w, crtc_h,
dd7fa6d8 PZ	325	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
dd7fa6d8 PZ	326	false);
b8d181e4 PZ	327	if (ret < 0) {
	328	ipu_plane_put_resources(ipu_plane);
	329	return ret;
	330	}
	331
	332	if (crtc != plane->crtc)
	333	dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
	334	plane->crtc, crtc);
	335	plane->crtc = crtc;
	336
b46355f0 SG	337	if (!ipu_plane->enabled)
b46355f0 SG	338	ipu_plane_enable(ipu_plane);
b8d181e4 PZ	339
	340	return 0;
	341	}
	342
	343	static int ipu_disable_plane(struct drm_plane *plane)
	344	{
	345	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	346
	347	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	348
b46355f0 SG	349	if (ipu_plane->enabled)
b46355f0 SG	350	ipu_plane_disable(ipu_plane);
b8d181e4 PZ	351
	352	ipu_plane_put_resources(ipu_plane);
	353
	354	return 0;
	355	}
	356
	357	static void ipu_plane_destroy(struct drm_plane *plane)
	358	{
	359	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	360
	361	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	362
	363	ipu_disable_plane(plane);
	364	drm_plane_cleanup(plane);
	365	kfree(ipu_plane);
	366	}
	367
	368	static struct drm_plane_funcs ipu_plane_funcs = {
	369	.update_plane = ipu_update_plane,
	370	.disable_plane = ipu_disable_plane,
	371	.destroy = ipu_plane_destroy,
	372	};
	373
	374	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
	375	int dma, int dp, unsigned int possible_crtcs,
	376	bool priv)
	377	{
	378	struct ipu_plane *ipu_plane;
	379	int ret;
	380
	381	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
	382	dma, dp, possible_crtcs);
	383
	384	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	385	if (!ipu_plane) {
	386	DRM_ERROR("failed to allocate plane\n");
	387	return ERR_PTR(-ENOMEM);
	388	}
	389
	390	ipu_plane->ipu = ipu;
	391	ipu_plane->dma = dma;
	392	ipu_plane->dp_flow = dp;
	393
	394	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
	395	&ipu_plane_funcs, ipu_plane_formats,
	396	ARRAY_SIZE(ipu_plane_formats),
	397	priv);
	398	if (ret) {
	399	DRM_ERROR("failed to initialize plane\n");
	400	kfree(ipu_plane);
	401	return ERR_PTR(ret);
	402	}
	403
	404	return ipu_plane;
	405	}