[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "video/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_ARGB1555,
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_ABGR1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_RGBA5551,
	DRM_FORMAT_BGRA5551,
	DRM_FORMAT_ARGB4444,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_RGBX8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
	DRM_FORMAT_RGB565,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
}

static inline int calc_bandwidth(int width, int height, unsigned int vref)
{
	return width * height * vref;
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct drm_gem_cma_object *cma_obj[3];
	unsigned long eba, ubo, vbo;
	int active, i;

	for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
		cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
		if (!cma_obj[i]) {
			DRM_DEBUG_KMS("plane %d entry is null.\n", i);
			return -EFAULT;
		}
	}

	eba = cma_obj[0]->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;

	if (eba & 0x7) {
		DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
		return -EINVAL;
	}

	if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) {
		DRM_DEBUG_KMS("pitches out of range.\n");
		return -EINVAL;
	}

	if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
		DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
		return -EINVAL;
	}

	ipu_plane->stride[0] = fb->pitches[0];

	switch (fb->pixel_format) {
	case DRM_FORMAT_YUV420:
	case DRM_FORMAT_YVU420:
		/*
		 * Multiplanar formats have to meet the following restrictions:
		 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
		 * - EBA, UBO and VBO are a multiple of 8
		 * - UBO and VBO are unsigned and not larger than 0xfffff8
		 * - Only EBA may be changed while scanout is active
		 * - The strides of U and V planes must be identical.
		 */
		ubo = cma_obj[1]->paddr + fb->offsets[1] +
		      fb->pitches[1] * y / 2 + x / 2 - eba;
		vbo = cma_obj[2]->paddr + fb->offsets[2] +
		      fb->pitches[2] * y / 2 + x / 2 - eba;

		if ((ubo & 0x7) || (vbo & 0x7)) {
			DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
			return -EINVAL;
		}

		if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) {
			DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
			return -EINVAL;
		}

		if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) ||
					   (ipu_plane->v_offset != vbo))) {
			DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
			return -EINVAL;
		}

		if (fb->pitches[1] != fb->pitches[2]) {
			DRM_DEBUG_KMS("U/V pitches must be identical.\n");
			return -EINVAL;
		}

		if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) {
			DRM_DEBUG_KMS("U/V pitches out of range.\n");
			return -EINVAL;
		}

		if (ipu_plane->enabled &&
		    (ipu_plane->stride[1] != fb->pitches[1])) {
			DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
			return -EINVAL;
		}

		ipu_plane->u_offset = ubo;
		ipu_plane->v_offset = vbo;
		ipu_plane->stride[1] = fb->pitches[1];

		dev_dbg(ipu_plane->base.dev->dev,
			"phys = %pad %pad %pad, x = %d, y = %d",
			&cma_obj[0]->paddr, &cma_obj[1]->paddr,
			&cma_obj[2]->paddr, x, y);
		break;
	default:
		dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
			&cma_obj[0]->paddr, x, y);
		break;
	}

	if (ipu_plane->enabled) {
		active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
		ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	} else {
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	}

	/* cache offsets for subsequent pageflips */
	ipu_plane->x = x;
	ipu_plane->y = y;

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h, bool interlaced)
{
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	/* clip to crtc bounds */
	if (crtc_x < 0) {
		if (-crtc_x > crtc_w)
			return -EINVAL;
		src_x += -crtc_x;
		src_w -= -crtc_x;
		crtc_w -= -crtc_x;
		crtc_x = 0;
	}
	if (crtc_y < 0) {
		if (-crtc_y > crtc_h)
			return -EINVAL;
		src_y += -crtc_y;
		src_h -= -crtc_y;
		crtc_h -= -crtc_y;
		crtc_y = 0;
	}
	if (crtc_x + crtc_w > mode->hdisplay) {
		if (crtc_x > mode->hdisplay)
			return -EINVAL;
		crtc_w = mode->hdisplay - crtc_x;
		src_w = crtc_w;
	}
	if (crtc_y + crtc_h > mode->vdisplay) {
		if (crtc_y > mode->vdisplay)
			return -EINVAL;
		crtc_h = mode->vdisplay - crtc_y;
		src_h = crtc_h;
	}
	/* full plane minimum width is 13 pixels */
	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	/*
	 * since we cannot touch active IDMAC channels, we do not support
	 * resizing the enabled plane or changing its format
	 */
	if (ipu_plane->enabled) {
		if (src_w != ipu_plane->w || src_h != ipu_plane->h ||
		    fb->pixel_format != ipu_plane->base.fb->pixel_format)
			return -EINVAL;

		return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	}

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		/* Enable local alpha on partial plane */
		switch (fb->pixel_format) {
		case DRM_FORMAT_ARGB1555:
		case DRM_FORMAT_ABGR1555:
		case DRM_FORMAT_RGBA5551:
		case DRM_FORMAT_BGRA5551:
		case DRM_FORMAT_ARGB4444:
		case DRM_FORMAT_ARGB8888:
		case DRM_FORMAT_ABGR8888:
		case DRM_FORMAT_RGBA8888:
		case DRM_FORMAT_BGRA8888:
			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
			break;
		default:
			break;
		}
	}

	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	if (ret) {
		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
			calc_bandwidth(crtc_w, crtc_h,
				       calc_vref(mode)), 64);
	if (ret) {
		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
		return ret;
	}

	ipu_cpmem_zero(ipu_plane->ipu_ch);
	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;
	if (interlaced)
		ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);

	ipu_plane->w = src_w;
	ipu_plane->h = src_h;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	if (ipu_plane->dp)
		ipu_dp_enable(ipu_plane->ipu);
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
	if (ipu_plane->dp)
		ipu_dp_disable(ipu_plane->ipu);
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
			false);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);
	plane->crtc = crtc;

	if (!ipu_plane->enabled)
		ipu_plane_enable(ipu_plane);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	if (ipu_plane->enabled)
		ipu_plane_disable(ipu_plane);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 enum drm_plane_type type)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
				       &ipu_plane_funcs, ipu_plane_formats,
				       ARRAY_SIZE(ipu_plane_formats), type,
				       NULL);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
39b9004d	20	#include "video/imx-ipu-v3.h"
b8d181e4 PZ	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
c639a1cf	26	DRM_FORMAT_ARGB1555,
b8d181e4	27	DRM_FORMAT_XRGB1555,
c639a1cf	28	DRM_FORMAT_ABGR1555,
b8d181e4	29	DRM_FORMAT_XBGR1555,
c639a1cf PZ	30	DRM_FORMAT_RGBA5551,
c639a1cf PZ	31	DRM_FORMAT_BGRA5551,
cb166a30	32	DRM_FORMAT_ARGB4444,
b8d181e4 PZ	33	DRM_FORMAT_ARGB8888,
	34	DRM_FORMAT_XRGB8888,
	35	DRM_FORMAT_ABGR8888,
	36	DRM_FORMAT_XBGR8888,
59d6b718 PZ	37	DRM_FORMAT_RGBA8888,
	38	DRM_FORMAT_RGBX8888,
	39	DRM_FORMAT_BGRA8888,
	40	DRM_FORMAT_BGRA8888,
b8d181e4 PZ	41	DRM_FORMAT_YUYV,
	42	DRM_FORMAT_YVYU,
	43	DRM_FORMAT_YUV420,
	44	DRM_FORMAT_YVU420,
33bee520	45	DRM_FORMAT_RGB565,
b8d181e4 PZ	46	};
	47
	48	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	49	{
	50	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	51	IPU_IRQ_EOF);
	52	}
	53
	54	static int calc_vref(struct drm_display_mode *mode)
	55	{
	56	unsigned long htotal, vtotal;
	57
	58	htotal = mode->htotal;
	59	vtotal = mode->vtotal;
	60
	61	if (!htotal \|\| !vtotal)
	62	return 60;
	63
	64	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
	65	}
	66
	67	static inline int calc_bandwidth(int width, int height, unsigned int vref)
	68	{
	69	return width * height * vref;
	70	}
	71
	72	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	73	int x, int y)
	74	{
67ca6b60 PZ	75	struct drm_gem_cma_object *cma_obj[3];
	76	unsigned long eba, ubo, vbo;
	77	int active, i;
	78
	79	for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
	80	cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
	81	if (!cma_obj[i]) {
	82	DRM_DEBUG_KMS("plane %d entry is null.\n", i);
	83	return -EFAULT;
	84	}
b8d181e4 PZ	85	}
b8d181e4 PZ	86
67ca6b60	87	eba = cma_obj[0]->paddr + fb->offsets[0] +
bc2b067a	88	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
356f9524	89
67ca6b60 PZ	90	if (eba & 0x7) {
	91	DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
	92	return -EINVAL;
	93	}
	94
	95	if (fb->pitches[0] < 1 \|\| fb->pitches[0] > 16384) {
	96	DRM_DEBUG_KMS("pitches out of range.\n");
	97	return -EINVAL;
	98	}
	99
	100	if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
	101	DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
	102	return -EINVAL;
	103	}
	104
	105	ipu_plane->stride[0] = fb->pitches[0];
	106
	107	switch (fb->pixel_format) {
	108	case DRM_FORMAT_YUV420:
	109	case DRM_FORMAT_YVU420:
	110	/*
	111	* Multiplanar formats have to meet the following restrictions:
	112	* - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
	113	* - EBA, UBO and VBO are a multiple of 8
	114	* - UBO and VBO are unsigned and not larger than 0xfffff8
	115	* - Only EBA may be changed while scanout is active
	116	* - The strides of U and V planes must be identical.
	117	*/
	118	ubo = cma_obj[1]->paddr + fb->offsets[1] +
	119	fb->pitches[1] * y / 2 + x / 2 - eba;
	120	vbo = cma_obj[2]->paddr + fb->offsets[2] +
	121	fb->pitches[2] * y / 2 + x / 2 - eba;
	122
	123	if ((ubo & 0x7) \|\| (vbo & 0x7)) {
	124	DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
	125	return -EINVAL;
	126	}
	127
	128	if ((ubo > 0xfffff8) \|\| (vbo > 0xfffff8)) {
	129	DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
	130	return -EINVAL;
	131	}
	132
	133	if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) \|\|
	134	(ipu_plane->v_offset != vbo))) {
	135	DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
	136	return -EINVAL;
	137	}
	138
	139	if (fb->pitches[1] != fb->pitches[2]) {
	140	DRM_DEBUG_KMS("U/V pitches must be identical.\n");
	141	return -EINVAL;
	142	}
	143
	144	if (fb->pitches[1] < 1 \|\| fb->pitches[1] > 16384) {
	145	DRM_DEBUG_KMS("U/V pitches out of range.\n");
	146	return -EINVAL;
	147	}
	148
	149	if (ipu_plane->enabled &&
	150	(ipu_plane->stride[1] != fb->pitches[1])) {
	151	DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
	152	return -EINVAL;
	153	}
154
155	ipu_plane->u_offset = ubo;
156	ipu_plane->v_offset = vbo;
157	ipu_plane->stride[1] = fb->pitches[1];
158
159	dev_dbg(ipu_plane->base.dev->dev,
160	"phys = %pad %pad %pad, x = %d, y = %d",
161	&cma_obj[0]->paddr, &cma_obj[1]->paddr,
162	&cma_obj[2]->paddr, x, y);
163	break;
164	default:
165	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
166	&cma_obj[0]->paddr, x, y);
167	break;
168	}
169
356f9524 PZ	170	if (ipu_plane->enabled) {
	171	active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
	172	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
	173	ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	174	} else {
	175	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
	176	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	177	}
b8d181e4	178
32f71106 LS	179	/* cache offsets for subsequent pageflips */
	180	ipu_plane->x = x;
	181	ipu_plane->y = y;
	182
b8d181e4 PZ	183	return 0;
	184	}
	185
	186	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	187	struct drm_display_mode *mode,
	188	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	189	unsigned int crtc_w, unsigned int crtc_h,
	190	uint32_t src_x, uint32_t src_y,
dd7fa6d8	191	uint32_t src_w, uint32_t src_h, bool interlaced)
b8d181e4	192	{
b8d181e4 PZ	193	struct device *dev = ipu_plane->base.dev->dev;
	194	int ret;
	195
	196	/* no scaling */
	197	if (src_w != crtc_w \|\| src_h != crtc_h)
	198	return -EINVAL;
	199
	200	/* clip to crtc bounds */
	201	if (crtc_x < 0) {
	202	if (-crtc_x > crtc_w)
	203	return -EINVAL;
	204	src_x += -crtc_x;
	205	src_w -= -crtc_x;
	206	crtc_w -= -crtc_x;
	207	crtc_x = 0;
	208	}
	209	if (crtc_y < 0) {
	210	if (-crtc_y > crtc_h)
	211	return -EINVAL;
	212	src_y += -crtc_y;
	213	src_h -= -crtc_y;
	214	crtc_h -= -crtc_y;
	215	crtc_y = 0;
	216	}
	217	if (crtc_x + crtc_w > mode->hdisplay) {
	218	if (crtc_x > mode->hdisplay)
	219	return -EINVAL;
	220	crtc_w = mode->hdisplay - crtc_x;
	221	src_w = crtc_w;
	222	}
	223	if (crtc_y + crtc_h > mode->vdisplay) {
	224	if (crtc_y > mode->vdisplay)
	225	return -EINVAL;
	226	crtc_h = mode->vdisplay - crtc_y;
	227	src_h = crtc_h;
	228	}
	229	/* full plane minimum width is 13 pixels */
	230	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
	231	return -EINVAL;
	232	if (crtc_h < 2)
	233	return -EINVAL;
	234
9a666030 PZ	235	/*
	236	* since we cannot touch active IDMAC channels, we do not support
	237	* resizing the enabled plane or changing its format
	238	*/
	239	if (ipu_plane->enabled) {
	240	if (src_w != ipu_plane->w \|\| src_h != ipu_plane->h \|\|
	241	fb->pixel_format != ipu_plane->base.fb->pixel_format)
	242	return -EINVAL;
	243
	244	return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	245	}
	246
b8d181e4 PZ	247	switch (ipu_plane->dp_flow) {
	248	case IPU_DP_FLOW_SYNC_BG:
	249	ret = ipu_dp_setup_channel(ipu_plane->dp,
	250	IPUV3_COLORSPACE_RGB,
	251	IPUV3_COLORSPACE_RGB);
	252	if (ret) {
	253	dev_err(dev,
	254	"initializing display processor failed with %d\n",
	255	ret);
	256	return ret;
	257	}
e6245fc7	258	ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
b8d181e4 PZ	259	break;
	260	case IPU_DP_FLOW_SYNC_FG:
	261	ipu_dp_setup_channel(ipu_plane->dp,
	262	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
	263	IPUV3_COLORSPACE_UNKNOWN);
	264	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
e6245fc7 PZ	265	/* Enable local alpha on partial plane */
e6245fc7 PZ	266	switch (fb->pixel_format) {
c639a1cf PZ	267	case DRM_FORMAT_ARGB1555:
	268	case DRM_FORMAT_ABGR1555:
	269	case DRM_FORMAT_RGBA5551:
	270	case DRM_FORMAT_BGRA5551:
cb166a30	271	case DRM_FORMAT_ARGB4444:
e6245fc7 PZ	272	case DRM_FORMAT_ARGB8888:
e6245fc7 PZ	273	case DRM_FORMAT_ABGR8888:
59d6b718 PZ	274	case DRM_FORMAT_RGBA8888:
59d6b718 PZ	275	case DRM_FORMAT_BGRA8888:
e6245fc7 PZ	276	ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
	277	break;
	278	default:
	279	break;
	280	}
b8d181e4 PZ	281	}
	282
	283	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	284	if (ret) {
	285	dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
	286	return ret;
	287	}
	288
	289	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
	290	calc_bandwidth(crtc_w, crtc_h,
	291	calc_vref(mode)), 64);
	292	if (ret) {
	293	dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
	294	return ret;
	295	}
	296
2eb671c4 SL	297	ipu_cpmem_zero(ipu_plane->ipu_ch);
	298	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	299	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
b8d181e4 PZ	300	if (ret < 0) {
	301	dev_err(dev, "unsupported pixel format 0x%08x\n",
	302	fb->pixel_format);
	303	return ret;
	304	}
	305	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
356f9524	306	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
7cd9bebe	307	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4 PZ	308
	309	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	310	if (ret < 0)
	311	return ret;
dd7fa6d8 PZ	312	if (interlaced)
dd7fa6d8 PZ	313	ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4	314
9a666030 PZ	315	ipu_plane->w = src_w;
	316	ipu_plane->h = src_h;
	317
b8d181e4 PZ	318	return 0;
	319	}
	320
	321	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
	322	{
	323	if (!IS_ERR_OR_NULL(ipu_plane->dp))
	324	ipu_dp_put(ipu_plane->dp);
	325	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
	326	ipu_dmfc_put(ipu_plane->dmfc);
	327	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
	328	ipu_idmac_put(ipu_plane->ipu_ch);
	329	}
	330
	331	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
	332	{
	333	int ret;
	334
	335	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	336	if (IS_ERR(ipu_plane->ipu_ch)) {
	337	ret = PTR_ERR(ipu_plane->ipu_ch);
	338	DRM_ERROR("failed to get idmac channel: %d\n", ret);
	339	return ret;
	340	}
	341
	342	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	343	if (IS_ERR(ipu_plane->dmfc)) {
	344	ret = PTR_ERR(ipu_plane->dmfc);
	345	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
	346	goto err_out;
	347	}
	348
	349	if (ipu_plane->dp_flow >= 0) {
	350	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
	351	if (IS_ERR(ipu_plane->dp)) {
	352	ret = PTR_ERR(ipu_plane->dp);
	353	DRM_ERROR("failed to get dp flow: %d\n", ret);
	354	goto err_out;
	355	}
	356	}
	357
	358	return 0;
	359	err_out:
	360	ipu_plane_put_resources(ipu_plane);
	361
	362	return ret;
	363	}
	364
	365	void ipu_plane_enable(struct ipu_plane *ipu_plane)
	366	{
285bbb01 PZ	367	if (ipu_plane->dp)
285bbb01 PZ	368	ipu_dp_enable(ipu_plane->ipu);
b8d181e4 PZ	369	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	370	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	371	if (ipu_plane->dp)
	372	ipu_dp_enable_channel(ipu_plane->dp);
	373
	374	ipu_plane->enabled = true;
	375	}
	376
	377	void ipu_plane_disable(struct ipu_plane *ipu_plane)
	378	{
	379	ipu_plane->enabled = false;
	380
	381	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
	382
	383	if (ipu_plane->dp)
	384	ipu_dp_disable_channel(ipu_plane->dp);
	385	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	386	ipu_dmfc_disable_channel(ipu_plane->dmfc);
285bbb01 PZ	387	if (ipu_plane->dp)
285bbb01 PZ	388	ipu_dp_disable(ipu_plane->ipu);
b8d181e4 PZ	389	}
b8d181e4 PZ	390
b8d181e4 PZ	391	/*
	392	* drm_plane API
	393	*/
	394
	395	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	396	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	397	unsigned int crtc_w, unsigned int crtc_h,
	398	uint32_t src_x, uint32_t src_y,
	399	uint32_t src_w, uint32_t src_h)
	400	{
	401	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	402	int ret = 0;
	403
	404	DRM_DEBUG_KMS("plane - %p\n", plane);
	405
	406	if (!ipu_plane->enabled)
	407	ret = ipu_plane_get_resources(ipu_plane);
	408	if (ret < 0)
	409	return ret;
	410
	411	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
	412	crtc_x, crtc_y, crtc_w, crtc_h,
dd7fa6d8 PZ	413	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
dd7fa6d8 PZ	414	false);
b8d181e4 PZ	415	if (ret < 0) {
	416	ipu_plane_put_resources(ipu_plane);
	417	return ret;
	418	}
	419
	420	if (crtc != plane->crtc)
beec8ec0	421	dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
b8d181e4 PZ	422	plane->crtc, crtc);
	423	plane->crtc = crtc;
	424
b46355f0 SG	425	if (!ipu_plane->enabled)
b46355f0 SG	426	ipu_plane_enable(ipu_plane);
b8d181e4 PZ	427
	428	return 0;
	429	}
	430
	431	static int ipu_disable_plane(struct drm_plane *plane)
	432	{
	433	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	434
	435	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	436
b46355f0 SG	437	if (ipu_plane->enabled)
b46355f0 SG	438	ipu_plane_disable(ipu_plane);
b8d181e4 PZ	439
	440	ipu_plane_put_resources(ipu_plane);
	441
	442	return 0;
	443	}
	444
	445	static void ipu_plane_destroy(struct drm_plane *plane)
	446	{
	447	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	448
	449	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	450
	451	ipu_disable_plane(plane);
	452	drm_plane_cleanup(plane);
	453	kfree(ipu_plane);
	454	}
	455
	456	static struct drm_plane_funcs ipu_plane_funcs = {
	457	.update_plane = ipu_update_plane,
	458	.disable_plane = ipu_disable_plane,
	459	.destroy = ipu_plane_destroy,
	460	};
	461
	462	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
	463	int dma, int dp, unsigned int possible_crtcs,
43895599	464	enum drm_plane_type type)
b8d181e4 PZ	465	{
	466	struct ipu_plane *ipu_plane;
	467	int ret;
	468
	469	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
	470	dma, dp, possible_crtcs);
	471
	472	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	473	if (!ipu_plane) {
	474	DRM_ERROR("failed to allocate plane\n");
	475	return ERR_PTR(-ENOMEM);
	476	}
	477
	478	ipu_plane->ipu = ipu;
	479	ipu_plane->dma = dma;
	480	ipu_plane->dp_flow = dp;
	481
43895599 PZ	482	ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
43895599 PZ	483	&ipu_plane_funcs, ipu_plane_formats,
b0b3b795 VS	484	ARRAY_SIZE(ipu_plane_formats), type,
b0b3b795 VS	485	NULL);
b8d181e4 PZ	486	if (ret) {
	487	DRM_ERROR("failed to initialize plane\n");
	488	kfree(ipu_plane);
	489	return ERR_PTR(ret);
	490	}
	491
	492	return ipu_plane;
	493	}