[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "video/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_ARGB1555,
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_ABGR1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_RGBA5551,
	DRM_FORMAT_BGRA5551,
	DRM_FORMAT_ARGB4444,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_RGBX8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
	DRM_FORMAT_RGB565,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct drm_gem_cma_object *cma_obj[3];
	unsigned long eba, ubo, vbo;
	int active, i;

	for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
		cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
		if (!cma_obj[i]) {
			DRM_DEBUG_KMS("plane %d entry is null.\n", i);
			return -EFAULT;
		}
	}

	eba = cma_obj[0]->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;

	if (eba & 0x7) {
		DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
		return -EINVAL;
	}

	if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) {
		DRM_DEBUG_KMS("pitches out of range.\n");
		return -EINVAL;
	}

	if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
		DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
		return -EINVAL;
	}

	ipu_plane->stride[0] = fb->pitches[0];

	switch (fb->pixel_format) {
	case DRM_FORMAT_YUV420:
	case DRM_FORMAT_YVU420:
		/*
		 * Multiplanar formats have to meet the following restrictions:
		 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
		 * - EBA, UBO and VBO are a multiple of 8
		 * - UBO and VBO are unsigned and not larger than 0xfffff8
		 * - Only EBA may be changed while scanout is active
		 * - The strides of U and V planes must be identical.
		 */
		ubo = cma_obj[1]->paddr + fb->offsets[1] +
		      fb->pitches[1] * y / 2 + x / 2 - eba;
		vbo = cma_obj[2]->paddr + fb->offsets[2] +
		      fb->pitches[2] * y / 2 + x / 2 - eba;

		if ((ubo & 0x7) || (vbo & 0x7)) {
			DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
			return -EINVAL;
		}

		if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) {
			DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
			return -EINVAL;
		}

		if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) ||
					   (ipu_plane->v_offset != vbo))) {
			DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
			return -EINVAL;
		}

		if (fb->pitches[1] != fb->pitches[2]) {
			DRM_DEBUG_KMS("U/V pitches must be identical.\n");
			return -EINVAL;
		}

		if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) {
			DRM_DEBUG_KMS("U/V pitches out of range.\n");
			return -EINVAL;
		}

		if (ipu_plane->enabled &&
		    (ipu_plane->stride[1] != fb->pitches[1])) {
			DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
			return -EINVAL;
		}

		ipu_plane->u_offset = ubo;
		ipu_plane->v_offset = vbo;
		ipu_plane->stride[1] = fb->pitches[1];

		dev_dbg(ipu_plane->base.dev->dev,
			"phys = %pad %pad %pad, x = %d, y = %d",
			&cma_obj[0]->paddr, &cma_obj[1]->paddr,
			&cma_obj[2]->paddr, x, y);
		break;
	default:
		dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
			&cma_obj[0]->paddr, x, y);
		break;
	}

	if (ipu_plane->enabled) {
		active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
		ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	} else {
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	}

	/* cache offsets for subsequent pageflips */
	ipu_plane->x = x;
	ipu_plane->y = y;

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h, bool interlaced)
{
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	if (ipu_plane->base.type == DRM_PLANE_TYPE_PRIMARY) {
		/* full plane doesn't support partial off screen */
		if (crtc_x || crtc_y || crtc_w != mode->hdisplay ||
			crtc_h != mode->vdisplay)
			return -EINVAL;

		/* full plane minimum width is 13 pixels */
		if (crtc_w < 13)
			return -EINVAL;
	} else if (ipu_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
		/* clip to crtc bounds */
		if (crtc_x < 0) {
			if (-crtc_x > crtc_w)
				return -EINVAL;
			src_x += -crtc_x;
			src_w -= -crtc_x;
			crtc_w -= -crtc_x;
			crtc_x = 0;
		}
		if (crtc_y < 0) {
			if (-crtc_y > crtc_h)
				return -EINVAL;
			src_y += -crtc_y;
			src_h -= -crtc_y;
			crtc_h -= -crtc_y;
			crtc_y = 0;
		}
		if (crtc_x + crtc_w > mode->hdisplay) {
			if (crtc_x > mode->hdisplay)
				return -EINVAL;
			crtc_w = mode->hdisplay - crtc_x;
			src_w = crtc_w;
		}
		if (crtc_y + crtc_h > mode->vdisplay) {
			if (crtc_y > mode->vdisplay)
				return -EINVAL;
			crtc_h = mode->vdisplay - crtc_y;
			src_h = crtc_h;
		}
	} else
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	/*
	 * since we cannot touch active IDMAC channels, we do not support
	 * resizing the enabled plane or changing its format
	 */
	if (ipu_plane->enabled) {
		if (src_w != ipu_plane->w || src_h != ipu_plane->h ||
		    fb->pixel_format != ipu_plane->base.fb->pixel_format)
			return -EINVAL;

		return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	}

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		/* Enable local alpha on partial plane */
		switch (fb->pixel_format) {
		case DRM_FORMAT_ARGB1555:
		case DRM_FORMAT_ABGR1555:
		case DRM_FORMAT_RGBA5551:
		case DRM_FORMAT_BGRA5551:
		case DRM_FORMAT_ARGB4444:
		case DRM_FORMAT_ARGB8888:
		case DRM_FORMAT_ABGR8888:
		case DRM_FORMAT_RGBA8888:
		case DRM_FORMAT_BGRA8888:
			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
			break;
		default:
			break;
		}
	}

	ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w);

	ipu_cpmem_zero(ipu_plane->ipu_ch);
	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;
	if (interlaced)
		ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);

	if (fb->pixel_format == DRM_FORMAT_YUV420) {
		ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
					      ipu_plane->stride[1],
					      ipu_plane->u_offset,
					      ipu_plane->v_offset);
	} else if (fb->pixel_format == DRM_FORMAT_YVU420) {
		ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
					      ipu_plane->stride[1],
					      ipu_plane->v_offset,
					      ipu_plane->u_offset);
	}

	ipu_plane->w = src_w;
	ipu_plane->h = src_h;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	if (ipu_plane->dp)
		ipu_dp_enable(ipu_plane->ipu);
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
	if (ipu_plane->dp)
		ipu_dp_disable(ipu_plane->ipu);
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
			false);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);

	if (!ipu_plane->enabled)
		ipu_plane_enable(ipu_plane);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	if (ipu_plane->enabled)
		ipu_plane_disable(ipu_plane);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static const struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 enum drm_plane_type type)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
				       &ipu_plane_funcs, ipu_plane_formats,
				       ARRAY_SIZE(ipu_plane_formats), type,
				       NULL);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
39b9004d	20	#include "video/imx-ipu-v3.h"
b8d181e4 PZ	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
c639a1cf	26	DRM_FORMAT_ARGB1555,
b8d181e4	27	DRM_FORMAT_XRGB1555,
c639a1cf	28	DRM_FORMAT_ABGR1555,
b8d181e4	29	DRM_FORMAT_XBGR1555,
c639a1cf PZ	30	DRM_FORMAT_RGBA5551,
c639a1cf PZ	31	DRM_FORMAT_BGRA5551,
cb166a30	32	DRM_FORMAT_ARGB4444,
b8d181e4 PZ	33	DRM_FORMAT_ARGB8888,
	34	DRM_FORMAT_XRGB8888,
	35	DRM_FORMAT_ABGR8888,
	36	DRM_FORMAT_XBGR8888,
59d6b718 PZ	37	DRM_FORMAT_RGBA8888,
	38	DRM_FORMAT_RGBX8888,
	39	DRM_FORMAT_BGRA8888,
	40	DRM_FORMAT_BGRA8888,
7932131f PZ	41	DRM_FORMAT_UYVY,
7932131f PZ	42	DRM_FORMAT_VYUY,
b8d181e4 PZ	43	DRM_FORMAT_YUYV,
	44	DRM_FORMAT_YVYU,
	45	DRM_FORMAT_YUV420,
	46	DRM_FORMAT_YVU420,
33bee520	47	DRM_FORMAT_RGB565,
b8d181e4 PZ	48	};
	49
	50	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	51	{
	52	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	53	IPU_IRQ_EOF);
	54	}
	55
b8d181e4 PZ	56	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	57	int x, int y)
	58	{
67ca6b60 PZ	59	struct drm_gem_cma_object *cma_obj[3];
	60	unsigned long eba, ubo, vbo;
	61	int active, i;
	62
	63	for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
	64	cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
	65	if (!cma_obj[i]) {
	66	DRM_DEBUG_KMS("plane %d entry is null.\n", i);
	67	return -EFAULT;
	68	}
b8d181e4 PZ	69	}
b8d181e4 PZ	70
67ca6b60	71	eba = cma_obj[0]->paddr + fb->offsets[0] +
bc2b067a	72	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
356f9524	73
67ca6b60 PZ	74	if (eba & 0x7) {
	75	DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
	76	return -EINVAL;
	77	}
	78
	79	if (fb->pitches[0] < 1 \|\| fb->pitches[0] > 16384) {
	80	DRM_DEBUG_KMS("pitches out of range.\n");
	81	return -EINVAL;
	82	}
	83
	84	if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
	85	DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
	86	return -EINVAL;
	87	}
	88
	89	ipu_plane->stride[0] = fb->pitches[0];
	90
	91	switch (fb->pixel_format) {
	92	case DRM_FORMAT_YUV420:
	93	case DRM_FORMAT_YVU420:
	94	/*
	95	* Multiplanar formats have to meet the following restrictions:
	96	* - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
	97	* - EBA, UBO and VBO are a multiple of 8
	98	* - UBO and VBO are unsigned and not larger than 0xfffff8
	99	* - Only EBA may be changed while scanout is active
	100	* - The strides of U and V planes must be identical.
	101	*/
	102	ubo = cma_obj[1]->paddr + fb->offsets[1] +
	103	fb->pitches[1] * y / 2 + x / 2 - eba;
	104	vbo = cma_obj[2]->paddr + fb->offsets[2] +
	105	fb->pitches[2] * y / 2 + x / 2 - eba;
	106
	107	if ((ubo & 0x7) \|\| (vbo & 0x7)) {
	108	DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
	109	return -EINVAL;
	110	}
	111
	112	if ((ubo > 0xfffff8) \|\| (vbo > 0xfffff8)) {
	113	DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
	114	return -EINVAL;
	115	}
	116
	117	if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) \|\|
	118	(ipu_plane->v_offset != vbo))) {
	119	DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
	120	return -EINVAL;
	121	}
	122
	123	if (fb->pitches[1] != fb->pitches[2]) {
	124	DRM_DEBUG_KMS("U/V pitches must be identical.\n");
	125	return -EINVAL;
	126	}
	127
	128	if (fb->pitches[1] < 1 \|\| fb->pitches[1] > 16384) {
	129	DRM_DEBUG_KMS("U/V pitches out of range.\n");
	130	return -EINVAL;
	131	}
	132
	133	if (ipu_plane->enabled &&
	134	(ipu_plane->stride[1] != fb->pitches[1])) {
	135	DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
	136	return -EINVAL;
	137	}
138
139	ipu_plane->u_offset = ubo;
140	ipu_plane->v_offset = vbo;
141	ipu_plane->stride[1] = fb->pitches[1];
142
143	dev_dbg(ipu_plane->base.dev->dev,
144	"phys = %pad %pad %pad, x = %d, y = %d",
145	&cma_obj[0]->paddr, &cma_obj[1]->paddr,
146	&cma_obj[2]->paddr, x, y);
147	break;
148	default:
149	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
150	&cma_obj[0]->paddr, x, y);
151	break;
152	}
153
356f9524 PZ	154	if (ipu_plane->enabled) {
	155	active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
	156	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
	157	ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	158	} else {
	159	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
	160	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	161	}
b8d181e4	162
32f71106 LS	163	/* cache offsets for subsequent pageflips */
	164	ipu_plane->x = x;
	165	ipu_plane->y = y;
	166
b8d181e4 PZ	167	return 0;
	168	}
	169
	170	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	171	struct drm_display_mode *mode,
	172	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	173	unsigned int crtc_w, unsigned int crtc_h,
	174	uint32_t src_x, uint32_t src_y,
dd7fa6d8	175	uint32_t src_w, uint32_t src_h, bool interlaced)
b8d181e4	176	{
b8d181e4 PZ	177	struct device *dev = ipu_plane->base.dev->dev;
	178	int ret;
	179
	180	/* no scaling */
	181	if (src_w != crtc_w \|\| src_h != crtc_h)
	182	return -EINVAL;
	183
08a89018 LY	184	if (ipu_plane->base.type == DRM_PLANE_TYPE_PRIMARY) {
	185	/* full plane doesn't support partial off screen */
	186	if (crtc_x \|\| crtc_y \|\| crtc_w != mode->hdisplay \|\|
	187	crtc_h != mode->vdisplay)
b8d181e4	188	return -EINVAL;
08a89018 LY	189
	190	/* full plane minimum width is 13 pixels */
	191	if (crtc_w < 13)
b8d181e4	192	return -EINVAL;
08a89018 LY	193	} else if (ipu_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
	194	/* clip to crtc bounds */
	195	if (crtc_x < 0) {
	196	if (-crtc_x > crtc_w)
	197	return -EINVAL;
	198	src_x += -crtc_x;
	199	src_w -= -crtc_x;
	200	crtc_w -= -crtc_x;
	201	crtc_x = 0;
	202	}
	203	if (crtc_y < 0) {
	204	if (-crtc_y > crtc_h)
	205	return -EINVAL;
	206	src_y += -crtc_y;
	207	src_h -= -crtc_y;
	208	crtc_h -= -crtc_y;
	209	crtc_y = 0;
	210	}
	211	if (crtc_x + crtc_w > mode->hdisplay) {
	212	if (crtc_x > mode->hdisplay)
	213	return -EINVAL;
	214	crtc_w = mode->hdisplay - crtc_x;
	215	src_w = crtc_w;
	216	}
	217	if (crtc_y + crtc_h > mode->vdisplay) {
	218	if (crtc_y > mode->vdisplay)
	219	return -EINVAL;
	220	crtc_h = mode->vdisplay - crtc_y;
	221	src_h = crtc_h;
	222	}
	223	} else
b8d181e4 PZ	224	return -EINVAL;
	225	if (crtc_h < 2)
	226	return -EINVAL;
	227
9a666030 PZ	228	/*
	229	* since we cannot touch active IDMAC channels, we do not support
	230	* resizing the enabled plane or changing its format
	231	*/
	232	if (ipu_plane->enabled) {
	233	if (src_w != ipu_plane->w \|\| src_h != ipu_plane->h \|\|
	234	fb->pixel_format != ipu_plane->base.fb->pixel_format)
	235	return -EINVAL;
	236
	237	return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	238	}
	239
b8d181e4 PZ	240	switch (ipu_plane->dp_flow) {
	241	case IPU_DP_FLOW_SYNC_BG:
	242	ret = ipu_dp_setup_channel(ipu_plane->dp,
	243	IPUV3_COLORSPACE_RGB,
	244	IPUV3_COLORSPACE_RGB);
	245	if (ret) {
	246	dev_err(dev,
	247	"initializing display processor failed with %d\n",
	248	ret);
	249	return ret;
	250	}
e6245fc7	251	ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
b8d181e4 PZ	252	break;
	253	case IPU_DP_FLOW_SYNC_FG:
	254	ipu_dp_setup_channel(ipu_plane->dp,
	255	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
	256	IPUV3_COLORSPACE_UNKNOWN);
	257	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
e6245fc7 PZ	258	/* Enable local alpha on partial plane */
e6245fc7 PZ	259	switch (fb->pixel_format) {
c639a1cf PZ	260	case DRM_FORMAT_ARGB1555:
	261	case DRM_FORMAT_ABGR1555:
	262	case DRM_FORMAT_RGBA5551:
	263	case DRM_FORMAT_BGRA5551:
cb166a30	264	case DRM_FORMAT_ARGB4444:
e6245fc7 PZ	265	case DRM_FORMAT_ARGB8888:
e6245fc7 PZ	266	case DRM_FORMAT_ABGR8888:
59d6b718 PZ	267	case DRM_FORMAT_RGBA8888:
59d6b718 PZ	268	case DRM_FORMAT_BGRA8888:
e6245fc7 PZ	269	ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
	270	break;
	271	default:
	272	break;
	273	}
b8d181e4 PZ	274	}
b8d181e4 PZ	275
6bcaf0c5 LY	276	ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w);
6bcaf0c5 LY	277
2eb671c4 SL	278	ipu_cpmem_zero(ipu_plane->ipu_ch);
	279	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	280	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
b8d181e4 PZ	281	if (ret < 0) {
	282	dev_err(dev, "unsupported pixel format 0x%08x\n",
	283	fb->pixel_format);
	284	return ret;
	285	}
	286	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
356f9524	287	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
7cd9bebe	288	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4 PZ	289
	290	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	291	if (ret < 0)
	292	return ret;
dd7fa6d8 PZ	293	if (interlaced)
dd7fa6d8 PZ	294	ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4	295
6ac217ee PZ	296	if (fb->pixel_format == DRM_FORMAT_YUV420) {
	297	ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
	298	ipu_plane->stride[1],
	299	ipu_plane->u_offset,
	300	ipu_plane->v_offset);
	301	} else if (fb->pixel_format == DRM_FORMAT_YVU420) {
	302	ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
	303	ipu_plane->stride[1],
	304	ipu_plane->v_offset,
	305	ipu_plane->u_offset);
	306	}
	307
9a666030 PZ	308	ipu_plane->w = src_w;
	309	ipu_plane->h = src_h;
	310
b8d181e4 PZ	311	return 0;
	312	}
	313
	314	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
	315	{
	316	if (!IS_ERR_OR_NULL(ipu_plane->dp))
	317	ipu_dp_put(ipu_plane->dp);
	318	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
	319	ipu_dmfc_put(ipu_plane->dmfc);
	320	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
	321	ipu_idmac_put(ipu_plane->ipu_ch);
	322	}
	323
	324	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
	325	{
	326	int ret;
	327
	328	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	329	if (IS_ERR(ipu_plane->ipu_ch)) {
	330	ret = PTR_ERR(ipu_plane->ipu_ch);
	331	DRM_ERROR("failed to get idmac channel: %d\n", ret);
	332	return ret;
	333	}
	334
	335	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	336	if (IS_ERR(ipu_plane->dmfc)) {
	337	ret = PTR_ERR(ipu_plane->dmfc);
	338	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
	339	goto err_out;
	340	}
	341
	342	if (ipu_plane->dp_flow >= 0) {
	343	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
	344	if (IS_ERR(ipu_plane->dp)) {
	345	ret = PTR_ERR(ipu_plane->dp);
	346	DRM_ERROR("failed to get dp flow: %d\n", ret);
	347	goto err_out;
	348	}
	349	}
	350
	351	return 0;
	352	err_out:
	353	ipu_plane_put_resources(ipu_plane);
	354
	355	return ret;
	356	}
	357
	358	void ipu_plane_enable(struct ipu_plane *ipu_plane)
	359	{
285bbb01 PZ	360	if (ipu_plane->dp)
285bbb01 PZ	361	ipu_dp_enable(ipu_plane->ipu);
b8d181e4 PZ	362	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	363	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	364	if (ipu_plane->dp)
	365	ipu_dp_enable_channel(ipu_plane->dp);
	366
	367	ipu_plane->enabled = true;
	368	}
	369
	370	void ipu_plane_disable(struct ipu_plane *ipu_plane)
	371	{
	372	ipu_plane->enabled = false;
	373
	374	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
	375
	376	if (ipu_plane->dp)
	377	ipu_dp_disable_channel(ipu_plane->dp);
	378	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	379	ipu_dmfc_disable_channel(ipu_plane->dmfc);
285bbb01 PZ	380	if (ipu_plane->dp)
285bbb01 PZ	381	ipu_dp_disable(ipu_plane->ipu);
b8d181e4 PZ	382	}
b8d181e4 PZ	383
b8d181e4 PZ	384	/*
	385	* drm_plane API
	386	*/
	387
	388	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	389	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	390	unsigned int crtc_w, unsigned int crtc_h,
	391	uint32_t src_x, uint32_t src_y,
	392	uint32_t src_w, uint32_t src_h)
	393	{
	394	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	395	int ret = 0;
	396
	397	DRM_DEBUG_KMS("plane - %p\n", plane);
	398
	399	if (!ipu_plane->enabled)
	400	ret = ipu_plane_get_resources(ipu_plane);
	401	if (ret < 0)
	402	return ret;
	403
	404	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
	405	crtc_x, crtc_y, crtc_w, crtc_h,
dd7fa6d8 PZ	406	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
dd7fa6d8 PZ	407	false);
b8d181e4 PZ	408	if (ret < 0) {
	409	ipu_plane_put_resources(ipu_plane);
	410	return ret;
	411	}
	412
	413	if (crtc != plane->crtc)
beec8ec0	414	dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
b8d181e4	415	plane->crtc, crtc);
b8d181e4	416
b46355f0 SG	417	if (!ipu_plane->enabled)
b46355f0 SG	418	ipu_plane_enable(ipu_plane);
b8d181e4 PZ	419
	420	return 0;
	421	}
	422
	423	static int ipu_disable_plane(struct drm_plane *plane)
	424	{
	425	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	426
	427	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	428
b46355f0 SG	429	if (ipu_plane->enabled)
b46355f0 SG	430	ipu_plane_disable(ipu_plane);
b8d181e4 PZ	431
	432	ipu_plane_put_resources(ipu_plane);
	433
	434	return 0;
	435	}
	436
	437	static void ipu_plane_destroy(struct drm_plane *plane)
	438	{
	439	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	440
	441	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	442
	443	ipu_disable_plane(plane);
	444	drm_plane_cleanup(plane);
	445	kfree(ipu_plane);
	446	}
	447
8b3ce873	448	static const struct drm_plane_funcs ipu_plane_funcs = {
b8d181e4 PZ	449	.update_plane = ipu_update_plane,
	450	.disable_plane = ipu_disable_plane,
	451	.destroy = ipu_plane_destroy,
	452	};
	453
	454	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
	455	int dma, int dp, unsigned int possible_crtcs,
43895599	456	enum drm_plane_type type)
b8d181e4 PZ	457	{
	458	struct ipu_plane *ipu_plane;
	459	int ret;
	460
	461	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
	462	dma, dp, possible_crtcs);
	463
	464	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	465	if (!ipu_plane) {
	466	DRM_ERROR("failed to allocate plane\n");
	467	return ERR_PTR(-ENOMEM);
	468	}
	469
	470	ipu_plane->ipu = ipu;
	471	ipu_plane->dma = dma;
	472	ipu_plane->dp_flow = dp;
	473
43895599 PZ	474	ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
43895599 PZ	475	&ipu_plane_funcs, ipu_plane_formats,
b0b3b795 VS	476	ARRAY_SIZE(ipu_plane_formats), type,
b0b3b795 VS	477	NULL);
b8d181e4 PZ	478	if (ret) {
	479	DRM_ERROR("failed to initialize plane\n");
	480	kfree(ipu_plane);
	481	return ERR_PTR(ret);
	482	}
	483
	484	return ipu_plane;
	485	}