projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9e629c17 JQ |
1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. | |
| 3 | * Author: Jie Qiu <jie.qiu@mediatek.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | */ | |
| 14 | #ifndef __MTK_DPI_REGS_H | |
| 15 | #define __MTK_DPI_REGS_H | |
| 16 | ||
| 17 | #define DPI_EN 0x00 | |
| 18 | #define EN BIT(0) | |
| 19 | ||
| 20 | #define DPI_RET 0x04 | |
| 21 | #define RST BIT(0) | |
| 22 | ||
| 23 | #define DPI_INTEN 0x08 | |
| 24 | #define INT_VSYNC_EN BIT(0) | |
| 25 | #define INT_VDE_EN BIT(1) | |
| 26 | #define INT_UNDERFLOW_EN BIT(2) | |
| 27 | ||
| 28 | #define DPI_INTSTA 0x0C | |
| 29 | #define INT_VSYNC_STA BIT(0) | |
| 30 | #define INT_VDE_STA BIT(1) | |
| 31 | #define INT_UNDERFLOW_STA BIT(2) | |
| 32 | ||
| 33 | #define DPI_CON 0x10 | |
| 34 | #define BG_ENABLE BIT(0) | |
| 35 | #define IN_RB_SWAP BIT(1) | |
| 36 | #define INTL_EN BIT(2) | |
| 37 | #define TDFP_EN BIT(3) | |
| 38 | #define CLPF_EN BIT(4) | |
| 39 | #define YUV422_EN BIT(5) | |
| 40 | #define CSC_ENABLE BIT(6) | |
| 41 | #define R601_SEL BIT(7) | |
| 42 | #define EMBSYNC_EN BIT(8) | |
| 43 | #define VS_LODD_EN BIT(16) | |
| 44 | #define VS_LEVEN_EN BIT(17) | |
| 45 | #define VS_RODD_EN BIT(18) | |
| 46 | #define VS_REVEN BIT(19) | |
| 47 | #define FAKE_DE_LODD BIT(20) | |
| 48 | #define FAKE_DE_LEVEN BIT(21) | |
| 49 | #define FAKE_DE_RODD BIT(22) | |
| 50 | #define FAKE_DE_REVEN BIT(23) | |
| 51 | ||
| 52 | #define DPI_OUTPUT_SETTING 0x14 | |
| 53 | #define CH_SWAP 0 | |
| 54 | #define CH_SWAP_MASK (0x7 << 0) | |
| 55 | #define SWAP_RGB 0x00 | |
| 56 | #define SWAP_GBR 0x01 | |
| 57 | #define SWAP_BRG 0x02 | |
| 58 | #define SWAP_RBG 0x03 | |
| 59 | #define SWAP_GRB 0x04 | |
| 60 | #define SWAP_BGR 0x05 | |
| 61 | #define BIT_SWAP BIT(3) | |
| 62 | #define B_MASK BIT(4) | |
| 63 | #define G_MASK BIT(5) | |
| 64 | #define R_MASK BIT(6) | |
| 65 | #define DE_MASK BIT(8) | |
| 66 | #define HS_MASK BIT(9) | |
| 67 | #define VS_MASK BIT(10) | |
| 68 | #define DE_POL BIT(12) | |
| 69 | #define HSYNC_POL BIT(13) | |
| 70 | #define VSYNC_POL BIT(14) | |
| 71 | #define CK_POL BIT(15) | |
| 72 | #define OEN_OFF BIT(16) | |
| 73 | #define EDGE_SEL BIT(17) | |
| 74 | #define OUT_BIT 18 | |
| 75 | #define OUT_BIT_MASK (0x3 << 18) | |
| 76 | #define OUT_BIT_8 0x00 | |
| 77 | #define OUT_BIT_10 0x01 | |
| 78 | #define OUT_BIT_12 0x02 | |
| 79 | #define OUT_BIT_16 0x03 | |
| 80 | #define YC_MAP 20 | |
| 81 | #define YC_MAP_MASK (0x7 << 20) | |
| 82 | #define YC_MAP_RGB 0x00 | |
| 83 | #define YC_MAP_CYCY 0x04 | |
| 84 | #define YC_MAP_YCYC 0x05 | |
| 85 | #define YC_MAP_CY 0x06 | |
| 86 | #define YC_MAP_YC 0x07 | |
| 87 | ||
| 88 | #define DPI_SIZE 0x18 | |
| 89 | #define HSIZE 0 | |
| 90 | #define HSIZE_MASK (0x1FFF << 0) | |
| 91 | #define VSIZE 16 | |
| 92 | #define VSIZE_MASK (0x1FFF << 16) | |
| 93 | ||
| 94 | #define DPI_DDR_SETTING 0x1C | |
| 95 | #define DDR_EN BIT(0) | |
| 96 | #define DDDR_SEL BIT(1) | |
| 97 | #define DDR_4PHASE BIT(2) | |
| 98 | #define DDR_WIDTH (0x3 << 4) | |
| 99 | #define DDR_PAD_MODE (0x1 << 8) | |
| 100 | ||
| 101 | #define DPI_TGEN_HWIDTH 0x20 | |
| 102 | #define HPW 0 | |
| 103 | #define HPW_MASK (0xFFF << 0) | |
| 104 | ||
| 105 | #define DPI_TGEN_HPORCH 0x24 | |
| 106 | #define HBP 0 | |
| 107 | #define HBP_MASK (0xFFF << 0) | |
| 108 | #define HFP 16 | |
| 109 | #define HFP_MASK (0xFFF << 16) | |
| 110 | ||
| 111 | #define DPI_TGEN_VWIDTH 0x28 | |
| 112 | #define DPI_TGEN_VPORCH 0x2C | |
| 113 | ||
| 114 | #define VSYNC_WIDTH_SHIFT 0 | |
| 115 | #define VSYNC_WIDTH_MASK (0xFFF << 0) | |
| 116 | #define VSYNC_HALF_LINE_SHIFT 16 | |
| 117 | #define VSYNC_HALF_LINE_MASK BIT(16) | |
| 118 | #define VSYNC_BACK_PORCH_SHIFT 0 | |
| 119 | #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) | |
| 120 | #define VSYNC_FRONT_PORCH_SHIFT 16 | |
| 121 | #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) | |
| 122 | ||
| 123 | #define DPI_BG_HCNTL 0x30 | |
| 124 | #define BG_RIGHT (0x1FFF << 0) | |
| 125 | #define BG_LEFT (0x1FFF << 16) | |
| 126 | ||
| 127 | #define DPI_BG_VCNTL 0x34 | |
| 128 | #define BG_BOT (0x1FFF << 0) | |
| 129 | #define BG_TOP (0x1FFF << 16) | |
| 130 | ||
| 131 | #define DPI_BG_COLOR 0x38 | |
| 132 | #define BG_B (0xF << 0) | |
| 133 | #define BG_G (0xF << 8) | |
| 134 | #define BG_R (0xF << 16) | |
| 135 | ||
| 136 | #define DPI_FIFO_CTL 0x3C | |
| 137 | #define FIFO_VALID_SET (0x1F << 0) | |
| 138 | #define FIFO_RST_SEL (0x1 << 8) | |
| 139 | ||
| 140 | #define DPI_STATUS 0x40 | |
| 141 | #define VCOUNTER (0x1FFF << 0) | |
| 142 | #define DPI_BUSY BIT(16) | |
| 143 | #define OUTEN BIT(17) | |
| 144 | #define FIELD BIT(20) | |
| 145 | #define TDLR BIT(21) | |
| 146 | ||
| 147 | #define DPI_TMODE 0x44 | |
| 148 | #define DPI_OEN_ON BIT(0) | |
| 149 | ||
| 150 | #define DPI_CHECKSUM 0x48 | |
| 151 | #define DPI_CHECKSUM_MASK (0xFFFFFF << 0) | |
| 152 | #define DPI_CHECKSUM_READY BIT(30) | |
| 153 | #define DPI_CHECKSUM_EN BIT(31) | |
| 154 | ||
| 155 | #define DPI_DUMMY 0x50 | |
| 156 | #define DPI_DUMMY_MASK (0xFFFFFFFF << 0) | |
| 157 | ||
| 158 | #define DPI_TGEN_VWIDTH_LEVEN 0x68 | |
| 159 | #define DPI_TGEN_VPORCH_LEVEN 0x6C | |
| 160 | #define DPI_TGEN_VWIDTH_RODD 0x70 | |
| 161 | #define DPI_TGEN_VPORCH_RODD 0x74 | |
| 162 | #define DPI_TGEN_VWIDTH_REVEN 0x78 | |
| 163 | #define DPI_TGEN_VPORCH_REVEN 0x7C | |
| 164 | ||
| 165 | #define DPI_ESAV_VTIMING_LODD 0x80 | |
| 166 | #define ESAV_VOFST_LODD (0xFFF << 0) | |
| 167 | #define ESAV_VWID_LODD (0xFFF << 16) | |
| 168 | ||
| 169 | #define DPI_ESAV_VTIMING_LEVEN 0x84 | |
| 170 | #define ESAV_VOFST_LEVEN (0xFFF << 0) | |
| 171 | #define ESAV_VWID_LEVEN (0xFFF << 16) | |
| 172 | ||
| 173 | #define DPI_ESAV_VTIMING_RODD 0x88 | |
| 174 | #define ESAV_VOFST_RODD (0xFFF << 0) | |
| 175 | #define ESAV_VWID_RODD (0xFFF << 16) | |
| 176 | ||
| 177 | #define DPI_ESAV_VTIMING_REVEN 0x8C | |
| 178 | #define ESAV_VOFST_REVEN (0xFFF << 0) | |
| 179 | #define ESAV_VWID_REVEN (0xFFF << 16) | |
| 180 | ||
| 181 | #define DPI_ESAV_FTIMING 0x90 | |
| 182 | #define ESAV_FOFST_ODD (0xFFF << 0) | |
| 183 | #define ESAV_FOFST_EVEN (0xFFF << 16) | |
| 184 | ||
| 185 | #define DPI_CLPF_SETTING 0x94 | |
| 186 | #define CLPF_TYPE (0x3 << 0) | |
| 187 | #define ROUND_EN BIT(4) | |
| 188 | ||
| 189 | #define DPI_Y_LIMIT 0x98 | |
| 190 | #define Y_LIMINT_BOT 0 | |
| 191 | #define Y_LIMINT_BOT_MASK (0xFFF << 0) | |
| 192 | #define Y_LIMINT_TOP 16 | |
| 193 | #define Y_LIMINT_TOP_MASK (0xFFF << 16) | |
| 194 | ||
| 195 | #define DPI_C_LIMIT 0x9C | |
| 196 | #define C_LIMIT_BOT 0 | |
| 197 | #define C_LIMIT_BOT_MASK (0xFFF << 0) | |
| 198 | #define C_LIMIT_TOP 16 | |
| 199 | #define C_LIMIT_TOP_MASK (0xFFF << 16) | |
| 200 | ||
| 201 | #define DPI_YUV422_SETTING 0xA0 | |
| 202 | #define UV_SWAP BIT(0) | |
| 203 | #define CR_DELSEL BIT(4) | |
| 204 | #define CB_DELSEL BIT(5) | |
| 205 | #define Y_DELSEL BIT(6) | |
| 206 | #define DE_DELSEL BIT(7) | |
| 207 | ||
| 208 | #define DPI_EMBSYNC_SETTING 0xA4 | |
| 209 | #define EMBSYNC_R_CR_EN BIT(0) | |
| 210 | #define EMPSYNC_G_Y_EN BIT(1) | |
| 211 | #define EMPSYNC_B_CB_EN BIT(2) | |
| 212 | #define ESAV_F_INV BIT(4) | |
| 213 | #define ESAV_V_INV BIT(5) | |
| 214 | #define ESAV_H_INV BIT(6) | |
| 215 | #define ESAV_CODE_MAN BIT(8) | |
| 216 | #define VS_OUT_SEL (0x7 << 12) | |
| 217 | ||
| 218 | #define DPI_ESAV_CODE_SET0 0xA8 | |
| 219 | #define ESAV_CODE0 (0xFFF << 0) | |
| 220 | #define ESAV_CODE1 (0xFFF << 16) | |
| 221 | ||
| 222 | #define DPI_ESAV_CODE_SET1 0xAC | |
| 223 | #define ESAV_CODE2 (0xFFF << 0) | |
| 224 | #define ESAV_CODE3_MSB BIT(16) | |
| 225 | ||
| 226 | #define DPI_H_FRE_CON 0xE0 | |
| 227 | #define H_FRE_2N BIT(25) | |
| 228 | #endif /* __MTK_DPI_REGS_H */ |