Commit | Line | Data |
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119f5173 CH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <asm/barrier.h> | |
15 | #include <drm/drmP.h> | |
16 | #include <drm/drm_atomic_helper.h> | |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_plane_helper.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/pm_runtime.h> | |
21 | #include <soc/mediatek/smi.h> | |
22 | ||
23 | #include "mtk_drm_drv.h" | |
24 | #include "mtk_drm_crtc.h" | |
25 | #include "mtk_drm_ddp.h" | |
26 | #include "mtk_drm_ddp_comp.h" | |
27 | #include "mtk_drm_gem.h" | |
28 | #include "mtk_drm_plane.h" | |
29 | ||
30 | /** | |
31 | * struct mtk_drm_crtc - MediaTek specific crtc structure. | |
32 | * @base: crtc object. | |
33 | * @enabled: records whether crtc_enable succeeded | |
34 | * @planes: array of 4 mtk_drm_plane structures, one for each overlay plane | |
35 | * @pending_planes: whether any plane has pending changes to be applied | |
36 | * @config_regs: memory mapped mmsys configuration register space | |
37 | * @mutex: handle to one of the ten disp_mutex streams | |
38 | * @ddp_comp_nr: number of components in ddp_comp | |
39 | * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc | |
40 | */ | |
41 | struct mtk_drm_crtc { | |
42 | struct drm_crtc base; | |
43 | bool enabled; | |
44 | ||
45 | bool pending_needs_vblank; | |
46 | struct drm_pending_vblank_event *event; | |
47 | ||
48 | struct mtk_drm_plane planes[OVL_LAYER_NR]; | |
49 | bool pending_planes; | |
50 | ||
51 | void __iomem *config_regs; | |
52 | struct mtk_disp_mutex *mutex; | |
53 | unsigned int ddp_comp_nr; | |
54 | struct mtk_ddp_comp **ddp_comp; | |
55 | }; | |
56 | ||
57 | struct mtk_crtc_state { | |
58 | struct drm_crtc_state base; | |
59 | ||
60 | bool pending_config; | |
61 | unsigned int pending_width; | |
62 | unsigned int pending_height; | |
63 | unsigned int pending_vrefresh; | |
64 | }; | |
65 | ||
66 | static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) | |
67 | { | |
68 | return container_of(c, struct mtk_drm_crtc, base); | |
69 | } | |
70 | ||
71 | static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) | |
72 | { | |
73 | return container_of(s, struct mtk_crtc_state, base); | |
74 | } | |
75 | ||
76 | static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) | |
77 | { | |
78 | struct drm_crtc *crtc = &mtk_crtc->base; | |
79 | unsigned long flags; | |
80 | ||
81 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
82 | drm_crtc_send_vblank_event(crtc, mtk_crtc->event); | |
83 | drm_crtc_vblank_put(crtc); | |
84 | mtk_crtc->event = NULL; | |
85 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
86 | } | |
87 | ||
88 | static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) | |
89 | { | |
90 | drm_crtc_handle_vblank(&mtk_crtc->base); | |
91 | if (mtk_crtc->pending_needs_vblank) { | |
92 | mtk_drm_crtc_finish_page_flip(mtk_crtc); | |
93 | mtk_crtc->pending_needs_vblank = false; | |
94 | } | |
95 | } | |
96 | ||
97 | static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) | |
98 | { | |
99 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
100 | int i; | |
101 | ||
102 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) | |
103 | clk_unprepare(mtk_crtc->ddp_comp[i]->clk); | |
104 | ||
105 | mtk_disp_mutex_put(mtk_crtc->mutex); | |
106 | ||
107 | drm_crtc_cleanup(crtc); | |
108 | } | |
109 | ||
110 | static void mtk_drm_crtc_reset(struct drm_crtc *crtc) | |
111 | { | |
112 | struct mtk_crtc_state *state; | |
113 | ||
114 | if (crtc->state) { | |
115 | if (crtc->state->mode_blob) | |
116 | drm_property_unreference_blob(crtc->state->mode_blob); | |
117 | ||
118 | state = to_mtk_crtc_state(crtc->state); | |
119 | memset(state, 0, sizeof(*state)); | |
120 | } else { | |
121 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
122 | if (!state) | |
123 | return; | |
124 | crtc->state = &state->base; | |
125 | } | |
126 | ||
127 | state->base.crtc = crtc; | |
128 | } | |
129 | ||
130 | static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) | |
131 | { | |
132 | struct mtk_crtc_state *state; | |
133 | ||
134 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
135 | if (!state) | |
136 | return NULL; | |
137 | ||
138 | __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); | |
139 | ||
140 | WARN_ON(state->base.crtc != crtc); | |
141 | state->base.crtc = crtc; | |
142 | ||
143 | return &state->base; | |
144 | } | |
145 | ||
146 | static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, | |
147 | struct drm_crtc_state *state) | |
148 | { | |
ec2dc6a0 | 149 | __drm_atomic_helper_crtc_destroy_state(state); |
119f5173 CH |
150 | kfree(to_mtk_crtc_state(state)); |
151 | } | |
152 | ||
153 | static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, | |
154 | const struct drm_display_mode *mode, | |
155 | struct drm_display_mode *adjusted_mode) | |
156 | { | |
157 | /* Nothing to do here, but this callback is mandatory. */ | |
158 | return true; | |
159 | } | |
160 | ||
161 | static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
162 | { | |
163 | struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); | |
164 | ||
165 | state->pending_width = crtc->mode.hdisplay; | |
166 | state->pending_height = crtc->mode.vdisplay; | |
167 | state->pending_vrefresh = crtc->mode.vrefresh; | |
168 | wmb(); /* Make sure the above parameters are set before update */ | |
169 | state->pending_config = true; | |
170 | } | |
171 | ||
172 | int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe) | |
173 | { | |
174 | struct mtk_drm_private *priv = drm->dev_private; | |
175 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]); | |
176 | struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; | |
177 | ||
178 | mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base); | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
183 | void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe) | |
184 | { | |
185 | struct mtk_drm_private *priv = drm->dev_private; | |
186 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]); | |
187 | struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; | |
188 | ||
189 | mtk_ddp_comp_disable_vblank(ovl); | |
190 | } | |
191 | ||
192 | static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) | |
193 | { | |
194 | int ret; | |
195 | int i; | |
196 | ||
197 | DRM_DEBUG_DRIVER("%s\n", __func__); | |
198 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { | |
199 | ret = clk_enable(mtk_crtc->ddp_comp[i]->clk); | |
200 | if (ret) { | |
201 | DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); | |
202 | goto err; | |
203 | } | |
204 | } | |
205 | ||
206 | return 0; | |
207 | err: | |
208 | while (--i >= 0) | |
209 | clk_disable(mtk_crtc->ddp_comp[i]->clk); | |
210 | return ret; | |
211 | } | |
212 | ||
213 | static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) | |
214 | { | |
215 | int i; | |
216 | ||
217 | DRM_DEBUG_DRIVER("%s\n", __func__); | |
218 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) | |
219 | clk_disable(mtk_crtc->ddp_comp[i]->clk); | |
220 | } | |
221 | ||
222 | static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) | |
223 | { | |
224 | struct drm_crtc *crtc = &mtk_crtc->base; | |
225 | unsigned int width, height, vrefresh; | |
226 | int ret; | |
227 | int i; | |
228 | ||
229 | DRM_DEBUG_DRIVER("%s\n", __func__); | |
230 | if (WARN_ON(!crtc->state)) | |
231 | return -EINVAL; | |
232 | ||
233 | width = crtc->state->adjusted_mode.hdisplay; | |
234 | height = crtc->state->adjusted_mode.vdisplay; | |
235 | vrefresh = crtc->state->adjusted_mode.vrefresh; | |
236 | ||
237 | ret = pm_runtime_get_sync(crtc->dev->dev); | |
238 | if (ret < 0) { | |
239 | DRM_ERROR("Failed to enable power domain: %d\n", ret); | |
240 | return ret; | |
241 | } | |
242 | ||
243 | ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); | |
244 | if (ret < 0) { | |
245 | DRM_ERROR("Failed to enable mutex clock: %d\n", ret); | |
246 | goto err_pm_runtime_put; | |
247 | } | |
248 | ||
249 | ret = mtk_crtc_ddp_clk_enable(mtk_crtc); | |
250 | if (ret < 0) { | |
251 | DRM_ERROR("Failed to enable component clocks: %d\n", ret); | |
252 | goto err_mutex_unprepare; | |
253 | } | |
254 | ||
255 | DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); | |
256 | for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { | |
257 | mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, | |
258 | mtk_crtc->ddp_comp[i]->id, | |
259 | mtk_crtc->ddp_comp[i + 1]->id); | |
260 | mtk_disp_mutex_add_comp(mtk_crtc->mutex, | |
261 | mtk_crtc->ddp_comp[i]->id); | |
262 | } | |
263 | mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); | |
264 | mtk_disp_mutex_enable(mtk_crtc->mutex); | |
265 | ||
266 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { | |
267 | struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; | |
268 | ||
269 | mtk_ddp_comp_config(comp, width, height, vrefresh); | |
270 | mtk_ddp_comp_start(comp); | |
271 | } | |
272 | ||
273 | /* Initially configure all planes */ | |
274 | for (i = 0; i < OVL_LAYER_NR; i++) { | |
275 | struct drm_plane *plane = &mtk_crtc->planes[i].base; | |
276 | struct mtk_plane_state *plane_state; | |
277 | ||
278 | plane_state = to_mtk_plane_state(plane->state); | |
279 | mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i, | |
280 | plane_state); | |
281 | } | |
282 | ||
283 | return 0; | |
284 | ||
285 | err_mutex_unprepare: | |
286 | mtk_disp_mutex_unprepare(mtk_crtc->mutex); | |
287 | err_pm_runtime_put: | |
288 | pm_runtime_put(crtc->dev->dev); | |
289 | return ret; | |
290 | } | |
291 | ||
292 | static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) | |
293 | { | |
294 | struct drm_device *drm = mtk_crtc->base.dev; | |
295 | int i; | |
296 | ||
297 | DRM_DEBUG_DRIVER("%s\n", __func__); | |
298 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) | |
299 | mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); | |
300 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) | |
301 | mtk_disp_mutex_remove_comp(mtk_crtc->mutex, | |
302 | mtk_crtc->ddp_comp[i]->id); | |
303 | mtk_disp_mutex_disable(mtk_crtc->mutex); | |
304 | for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { | |
305 | mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, | |
306 | mtk_crtc->ddp_comp[i]->id, | |
307 | mtk_crtc->ddp_comp[i + 1]->id); | |
308 | mtk_disp_mutex_remove_comp(mtk_crtc->mutex, | |
309 | mtk_crtc->ddp_comp[i]->id); | |
310 | } | |
311 | mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); | |
312 | mtk_crtc_ddp_clk_disable(mtk_crtc); | |
313 | mtk_disp_mutex_unprepare(mtk_crtc->mutex); | |
314 | ||
315 | pm_runtime_put(drm->dev); | |
316 | } | |
317 | ||
318 | static void mtk_drm_crtc_enable(struct drm_crtc *crtc) | |
319 | { | |
320 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
321 | struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; | |
322 | int ret; | |
323 | ||
324 | DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); | |
325 | ||
326 | ret = mtk_smi_larb_get(ovl->larb_dev); | |
327 | if (ret) { | |
328 | DRM_ERROR("Failed to get larb: %d\n", ret); | |
329 | return; | |
330 | } | |
331 | ||
332 | ret = mtk_crtc_ddp_hw_init(mtk_crtc); | |
333 | if (ret) { | |
334 | mtk_smi_larb_put(ovl->larb_dev); | |
335 | return; | |
336 | } | |
337 | ||
338 | drm_crtc_vblank_on(crtc); | |
339 | mtk_crtc->enabled = true; | |
340 | } | |
341 | ||
342 | static void mtk_drm_crtc_disable(struct drm_crtc *crtc) | |
343 | { | |
344 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
345 | struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; | |
346 | int i; | |
347 | ||
348 | DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); | |
349 | if (!mtk_crtc->enabled) | |
350 | return; | |
351 | ||
352 | /* Set all pending plane state to disabled */ | |
353 | for (i = 0; i < OVL_LAYER_NR; i++) { | |
354 | struct drm_plane *plane = &mtk_crtc->planes[i].base; | |
355 | struct mtk_plane_state *plane_state; | |
356 | ||
357 | plane_state = to_mtk_plane_state(plane->state); | |
358 | plane_state->pending.enable = false; | |
359 | plane_state->pending.config = true; | |
360 | } | |
361 | mtk_crtc->pending_planes = true; | |
362 | ||
363 | /* Wait for planes to be disabled */ | |
364 | drm_crtc_wait_one_vblank(crtc); | |
365 | ||
366 | drm_crtc_vblank_off(crtc); | |
367 | mtk_crtc_ddp_hw_fini(mtk_crtc); | |
368 | mtk_smi_larb_put(ovl->larb_dev); | |
369 | ||
370 | mtk_crtc->enabled = false; | |
371 | } | |
372 | ||
373 | static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, | |
374 | struct drm_crtc_state *old_crtc_state) | |
375 | { | |
376 | struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); | |
377 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
378 | ||
379 | if (mtk_crtc->event && state->base.event) | |
380 | DRM_ERROR("new event while there is still a pending event\n"); | |
381 | ||
382 | if (state->base.event) { | |
383 | state->base.event->pipe = drm_crtc_index(crtc); | |
384 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
385 | mtk_crtc->event = state->base.event; | |
386 | state->base.event = NULL; | |
387 | } | |
388 | } | |
389 | ||
390 | static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, | |
391 | struct drm_crtc_state *old_crtc_state) | |
392 | { | |
393 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
394 | unsigned int pending_planes = 0; | |
395 | int i; | |
396 | ||
397 | if (mtk_crtc->event) | |
398 | mtk_crtc->pending_needs_vblank = true; | |
399 | for (i = 0; i < OVL_LAYER_NR; i++) { | |
400 | struct drm_plane *plane = &mtk_crtc->planes[i].base; | |
401 | struct mtk_plane_state *plane_state; | |
402 | ||
403 | plane_state = to_mtk_plane_state(plane->state); | |
404 | if (plane_state->pending.dirty) { | |
405 | plane_state->pending.config = true; | |
406 | plane_state->pending.dirty = false; | |
407 | pending_planes |= BIT(i); | |
408 | } | |
409 | } | |
410 | if (pending_planes) | |
411 | mtk_crtc->pending_planes = true; | |
412 | } | |
413 | ||
414 | static const struct drm_crtc_funcs mtk_crtc_funcs = { | |
415 | .set_config = drm_atomic_helper_set_config, | |
416 | .page_flip = drm_atomic_helper_page_flip, | |
417 | .destroy = mtk_drm_crtc_destroy, | |
418 | .reset = mtk_drm_crtc_reset, | |
419 | .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, | |
420 | .atomic_destroy_state = mtk_drm_crtc_destroy_state, | |
421 | }; | |
422 | ||
423 | static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { | |
424 | .mode_fixup = mtk_drm_crtc_mode_fixup, | |
425 | .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, | |
426 | .enable = mtk_drm_crtc_enable, | |
427 | .disable = mtk_drm_crtc_disable, | |
428 | .atomic_begin = mtk_drm_crtc_atomic_begin, | |
429 | .atomic_flush = mtk_drm_crtc_atomic_flush, | |
430 | }; | |
431 | ||
432 | static int mtk_drm_crtc_init(struct drm_device *drm, | |
433 | struct mtk_drm_crtc *mtk_crtc, | |
434 | struct drm_plane *primary, | |
435 | struct drm_plane *cursor, unsigned int pipe) | |
436 | { | |
437 | int ret; | |
438 | ||
439 | ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, | |
440 | &mtk_crtc_funcs, NULL); | |
441 | if (ret) | |
442 | goto err_cleanup_crtc; | |
443 | ||
444 | drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); | |
445 | ||
446 | return 0; | |
447 | ||
448 | err_cleanup_crtc: | |
449 | drm_crtc_cleanup(&mtk_crtc->base); | |
450 | return ret; | |
451 | } | |
452 | ||
453 | void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl) | |
454 | { | |
455 | struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); | |
456 | struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); | |
457 | unsigned int i; | |
458 | ||
459 | /* | |
460 | * TODO: instead of updating the registers here, we should prepare | |
461 | * working registers in atomic_commit and let the hardware command | |
462 | * queue update module registers on vblank. | |
463 | */ | |
464 | if (state->pending_config) { | |
465 | mtk_ddp_comp_config(ovl, state->pending_width, | |
466 | state->pending_height, | |
467 | state->pending_vrefresh); | |
468 | ||
469 | state->pending_config = false; | |
470 | } | |
471 | ||
472 | if (mtk_crtc->pending_planes) { | |
473 | for (i = 0; i < OVL_LAYER_NR; i++) { | |
474 | struct drm_plane *plane = &mtk_crtc->planes[i].base; | |
475 | struct mtk_plane_state *plane_state; | |
476 | ||
477 | plane_state = to_mtk_plane_state(plane->state); | |
478 | ||
479 | if (plane_state->pending.config) { | |
480 | mtk_ddp_comp_layer_config(ovl, i, plane_state); | |
481 | plane_state->pending.config = false; | |
482 | } | |
483 | } | |
484 | mtk_crtc->pending_planes = false; | |
485 | } | |
486 | ||
487 | mtk_drm_finish_page_flip(mtk_crtc); | |
488 | } | |
489 | ||
490 | int mtk_drm_crtc_create(struct drm_device *drm_dev, | |
491 | const enum mtk_ddp_comp_id *path, unsigned int path_len) | |
492 | { | |
493 | struct mtk_drm_private *priv = drm_dev->dev_private; | |
494 | struct device *dev = drm_dev->dev; | |
495 | struct mtk_drm_crtc *mtk_crtc; | |
496 | enum drm_plane_type type; | |
497 | unsigned int zpos; | |
498 | int pipe = priv->num_pipes; | |
499 | int ret; | |
500 | int i; | |
501 | ||
502 | for (i = 0; i < path_len; i++) { | |
503 | enum mtk_ddp_comp_id comp_id = path[i]; | |
504 | struct device_node *node; | |
505 | ||
506 | node = priv->comp_node[comp_id]; | |
507 | if (!node) { | |
508 | dev_info(dev, | |
509 | "Not creating crtc %d because component %d is disabled or missing\n", | |
510 | pipe, comp_id); | |
511 | return 0; | |
512 | } | |
513 | } | |
514 | ||
515 | mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); | |
516 | if (!mtk_crtc) | |
517 | return -ENOMEM; | |
518 | ||
519 | mtk_crtc->config_regs = priv->config_regs; | |
520 | mtk_crtc->ddp_comp_nr = path_len; | |
521 | mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, | |
522 | sizeof(*mtk_crtc->ddp_comp), | |
523 | GFP_KERNEL); | |
524 | ||
525 | mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); | |
526 | if (IS_ERR(mtk_crtc->mutex)) { | |
527 | ret = PTR_ERR(mtk_crtc->mutex); | |
528 | dev_err(dev, "Failed to get mutex: %d\n", ret); | |
529 | return ret; | |
530 | } | |
531 | ||
532 | for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { | |
533 | enum mtk_ddp_comp_id comp_id = path[i]; | |
534 | struct mtk_ddp_comp *comp; | |
535 | struct device_node *node; | |
536 | ||
537 | node = priv->comp_node[comp_id]; | |
538 | comp = priv->ddp_comp[comp_id]; | |
539 | if (!comp) { | |
540 | dev_err(dev, "Component %s not initialized\n", | |
541 | node->full_name); | |
542 | ret = -ENODEV; | |
543 | goto unprepare; | |
544 | } | |
545 | ||
546 | ret = clk_prepare(comp->clk); | |
547 | if (ret) { | |
548 | dev_err(dev, | |
549 | "Failed to prepare clock for component %s: %d\n", | |
550 | node->full_name, ret); | |
551 | goto unprepare; | |
552 | } | |
553 | ||
554 | mtk_crtc->ddp_comp[i] = comp; | |
555 | } | |
556 | ||
557 | for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) { | |
558 | type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : | |
559 | (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : | |
560 | DRM_PLANE_TYPE_OVERLAY; | |
561 | ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], | |
562 | BIT(pipe), type, zpos); | |
563 | if (ret) | |
564 | goto unprepare; | |
565 | } | |
566 | ||
567 | ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0].base, | |
568 | &mtk_crtc->planes[1].base, pipe); | |
569 | if (ret < 0) | |
570 | goto unprepare; | |
571 | ||
572 | priv->crtc[pipe] = &mtk_crtc->base; | |
573 | priv->num_pipes++; | |
574 | ||
575 | return 0; | |
576 | ||
577 | unprepare: | |
578 | while (--i >= 0) | |
579 | clk_unprepare(mtk_crtc->ddp_comp[i]->clk); | |
580 | ||
581 | return ret; | |
582 | } |