[deliverable/linux.git] / drivers / gpu / drm / mediatek / mtk_drm_ddp_comp.c

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Authors:
 *	YT Shen <yt.shen@mediatek.com>
 *	CK Hu <ck.hu@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include "mtk_drm_drv.h"
#include "mtk_drm_plane.h"
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_crtc.h"

#define DISP_OD_EN				0x0000
#define DISP_OD_INTEN				0x0008
#define DISP_OD_INTSTA				0x000c
#define DISP_OD_CFG				0x0020
#define DISP_OD_SIZE				0x0030

#define DISP_REG_UFO_START			0x0000

#define DISP_COLOR_CFG_MAIN			0x0400
#define DISP_COLOR_START			0x0c00
#define DISP_COLOR_WIDTH			0x0c50
#define DISP_COLOR_HEIGHT			0x0c54

#define DISP_AAL_EN				0x0000
#define DISP_AAL_SIZE				0x0030

#define DISP_GAMMA_EN				0x0000
#define DISP_GAMMA_CFG				0x0020
#define DISP_GAMMA_SIZE				0x0030
#define DISP_GAMMA_LUT				0x0700

#define LUT_10BIT_MASK				0x03ff

#define	OD_RELAY_MODE		BIT(0)

#define	UFO_BYPASS		BIT(2)

#define	COLOR_BYPASS_ALL	BIT(7)
#define	COLOR_SEQ_SEL		BIT(13)

#define AAL_EN			BIT(0)

#define GAMMA_EN		BIT(0)
#define GAMMA_LUT_EN		BIT(1)

static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
			     unsigned int h, unsigned int vrefresh)
{
	writel(w, comp->regs + DISP_COLOR_WIDTH);
	writel(h, comp->regs + DISP_COLOR_HEIGHT);
}

static void mtk_color_start(struct mtk_ddp_comp *comp)
{
	writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
	       comp->regs + DISP_COLOR_CFG_MAIN);
	writel(0x1, comp->regs + DISP_COLOR_START);
}

static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
			  unsigned int h, unsigned int vrefresh)
{
	writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
}

static void mtk_od_start(struct mtk_ddp_comp *comp)
{
	writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG);
	writel(1, comp->regs + DISP_OD_EN);
}

static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
{
	writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
}

static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
			   unsigned int h, unsigned int vrefresh)
{
	writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
}

static void mtk_aal_start(struct mtk_ddp_comp *comp)
{
	writel(AAL_EN, comp->regs + DISP_AAL_EN);
}

static void mtk_aal_stop(struct mtk_ddp_comp *comp)
{
	writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
}

static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
			     unsigned int h, unsigned int vrefresh)
{
	writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
}

static void mtk_gamma_start(struct mtk_ddp_comp *comp)
{
	writel(GAMMA_EN, comp->regs  + DISP_GAMMA_EN);
}

static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
{
	writel_relaxed(0x0, comp->regs  + DISP_GAMMA_EN);
}

static void mtk_gamma_set(struct mtk_ddp_comp *comp,
			  struct drm_crtc_state *state)
{
	unsigned int i, reg;
	struct drm_color_lut *lut;
	void __iomem *lut_base;
	u32 word;

	if (state->gamma_lut) {
		reg = readl(comp->regs + DISP_GAMMA_CFG);
		reg = reg | GAMMA_LUT_EN;
		writel(reg, comp->regs + DISP_GAMMA_CFG);
		lut_base = comp->regs + DISP_GAMMA_LUT;
		lut = (struct drm_color_lut *)state->gamma_lut->data;
		for (i = 0; i < MTK_LUT_SIZE; i++) {
			word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
				(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
				((lut[i].blue >> 6) & LUT_10BIT_MASK);
			writel(word, (lut_base + i * 4));
		}
	}
}

static const struct mtk_ddp_comp_funcs ddp_aal = {
	.gamma_set = mtk_gamma_set,
	.config = mtk_aal_config,
	.start = mtk_aal_start,
	.stop = mtk_aal_stop,
};

static const struct mtk_ddp_comp_funcs ddp_gamma = {
	.gamma_set = mtk_gamma_set,
	.config = mtk_gamma_config,
	.start = mtk_gamma_start,
	.stop = mtk_gamma_stop,
};

static const struct mtk_ddp_comp_funcs ddp_color = {
	.config = mtk_color_config,
	.start = mtk_color_start,
};

static const struct mtk_ddp_comp_funcs ddp_od = {
	.config = mtk_od_config,
	.start = mtk_od_start,
};

static const struct mtk_ddp_comp_funcs ddp_ufoe = {
	.start = mtk_ufoe_start,
};

static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
	[MTK_DISP_OVL] = "ovl",
	[MTK_DISP_RDMA] = "rdma",
	[MTK_DISP_WDMA] = "wdma",
	[MTK_DISP_COLOR] = "color",
	[MTK_DISP_AAL] = "aal",
	[MTK_DISP_GAMMA] = "gamma",
	[MTK_DISP_UFOE] = "ufoe",
	[MTK_DSI] = "dsi",
	[MTK_DPI] = "dpi",
	[MTK_DISP_PWM] = "pwm",
	[MTK_DISP_MUTEX] = "mutex",
	[MTK_DISP_OD] = "od",
};

struct mtk_ddp_comp_match {
	enum mtk_ddp_comp_type type;
	int alias_id;
	const struct mtk_ddp_comp_funcs *funcs;
};

static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
	[DDP_COMPONENT_AAL]	= { MTK_DISP_AAL,	0, &ddp_aal },
	[DDP_COMPONENT_COLOR0]	= { MTK_DISP_COLOR,	0, &ddp_color },
	[DDP_COMPONENT_COLOR1]	= { MTK_DISP_COLOR,	1, &ddp_color },
	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, NULL },
	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, NULL },
	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, NULL },
	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
	[DDP_COMPONENT_OD]	= { MTK_DISP_OD,	0, &ddp_od },
	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, NULL },
	[DDP_COMPONENT_OVL1]	= { MTK_DISP_OVL,	1, NULL },
	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, NULL },
	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, NULL },
	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, NULL },
	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
};

int mtk_ddp_comp_get_id(struct device_node *node,
			enum mtk_ddp_comp_type comp_type)
{
	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
	int i;

	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
		if (comp_type == mtk_ddp_matches[i].type &&
		    (id < 0 || id == mtk_ddp_matches[i].alias_id))
			return i;
	}

	return -EINVAL;
}

int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
		      struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
		      const struct mtk_ddp_comp_funcs *funcs)
{
	enum mtk_ddp_comp_type type;
	struct device_node *larb_node;
	struct platform_device *larb_pdev;

	if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
		return -EINVAL;

	comp->id = comp_id;
	comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;

	if (comp_id == DDP_COMPONENT_DPI0 ||
	    comp_id == DDP_COMPONENT_DSI0 ||
	    comp_id == DDP_COMPONENT_PWM0) {
		comp->regs = NULL;
		comp->clk = NULL;
		comp->irq = 0;
		return 0;
	}

	comp->regs = of_iomap(node, 0);
	comp->irq = of_irq_get(node, 0);
	comp->clk = of_clk_get(node, 0);
	if (IS_ERR(comp->clk))
		comp->clk = NULL;

	type = mtk_ddp_matches[comp_id].type;

	/* Only DMA capable components need the LARB property */
	comp->larb_dev = NULL;
	if (type != MTK_DISP_OVL &&
	    type != MTK_DISP_RDMA &&
	    type != MTK_DISP_WDMA)
		return 0;

	larb_node = of_parse_phandle(node, "mediatek,larb", 0);
	if (!larb_node) {
		dev_err(dev,
			"Missing mediadek,larb phandle in %s node\n",
			node->full_name);
		return -EINVAL;
	}

	larb_pdev = of_find_device_by_node(larb_node);
	if (!larb_pdev) {
		dev_warn(dev, "Waiting for larb device %s\n",
			 larb_node->full_name);
		of_node_put(larb_node);
		return -EPROBE_DEFER;
	}
	of_node_put(larb_node);

	comp->larb_dev = &larb_pdev->dev;

	return 0;
}

int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
{
	struct mtk_drm_private *private = drm->dev_private;

	if (private->ddp_comp[comp->id])
		return -EBUSY;

	private->ddp_comp[comp->id] = comp;
	return 0;
}

void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
{
	struct mtk_drm_private *private = drm->dev_private;

	private->ddp_comp[comp->id] = NULL;
}
Commit	Line	Data
119f5173 CH	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Authors:
	4	* YT Shen <yt.shen@mediatek.com>
	5	* CK Hu <ck.hu@mediatek.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/platform_device.h>
	23	#include <drm/drmP.h>
	24	#include "mtk_drm_drv.h"
	25	#include "mtk_drm_plane.h"
	26	#include "mtk_drm_ddp_comp.h"
2f3f4dda	27	#include "mtk_drm_crtc.h"
119f5173 CH	28
	29	#define DISP_OD_EN 0x0000
	30	#define DISP_OD_INTEN 0x0008
	31	#define DISP_OD_INTSTA 0x000c
	32	#define DISP_OD_CFG 0x0020
	33	#define DISP_OD_SIZE 0x0030
	34
	35	#define DISP_REG_UFO_START 0x0000
	36
	37	#define DISP_COLOR_CFG_MAIN 0x0400
	38	#define DISP_COLOR_START 0x0c00
	39	#define DISP_COLOR_WIDTH 0x0c50
	40	#define DISP_COLOR_HEIGHT 0x0c54
	41
0664d139 BH	42	#define DISP_AAL_EN 0x0000
	43	#define DISP_AAL_SIZE 0x0030
	44
e0a5d337	45	#define DISP_GAMMA_EN 0x0000
2f3f4dda	46	#define DISP_GAMMA_CFG 0x0020
e0a5d337	47	#define DISP_GAMMA_SIZE 0x0030
2f3f4dda BH	48	#define DISP_GAMMA_LUT 0x0700
	49
	50	#define LUT_10BIT_MASK 0x03ff
e0a5d337	51
119f5173 CH	52	#define OD_RELAY_MODE BIT(0)
	53
	54	#define UFO_BYPASS BIT(2)
	55
	56	#define COLOR_BYPASS_ALL BIT(7)
	57	#define COLOR_SEQ_SEL BIT(13)
	58
0664d139 BH	59	#define AAL_EN BIT(0)
0664d139 BH	60
e0a5d337	61	#define GAMMA_EN BIT(0)
2f3f4dda	62	#define GAMMA_LUT_EN BIT(1)
e0a5d337	63
119f5173 CH	64	static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
	65	unsigned int h, unsigned int vrefresh)
	66	{
	67	writel(w, comp->regs + DISP_COLOR_WIDTH);
	68	writel(h, comp->regs + DISP_COLOR_HEIGHT);
	69	}
	70
	71	static void mtk_color_start(struct mtk_ddp_comp *comp)
	72	{
	73	writel(COLOR_BYPASS_ALL \| COLOR_SEQ_SEL,
	74	comp->regs + DISP_COLOR_CFG_MAIN);
	75	writel(0x1, comp->regs + DISP_COLOR_START);
	76	}
	77
	78	static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
	79	unsigned int h, unsigned int vrefresh)
	80	{
	81	writel(w << 16 \| h, comp->regs + DISP_OD_SIZE);
	82	}
	83
	84	static void mtk_od_start(struct mtk_ddp_comp *comp)
	85	{
	86	writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG);
	87	writel(1, comp->regs + DISP_OD_EN);
	88	}
	89
	90	static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
	91	{
	92	writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
	93	}
	94
0664d139 BH	95	static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
	96	unsigned int h, unsigned int vrefresh)
	97	{
	98	writel(h << 16 \| w, comp->regs + DISP_AAL_SIZE);
	99	}
	100
	101	static void mtk_aal_start(struct mtk_ddp_comp *comp)
	102	{
	103	writel(AAL_EN, comp->regs + DISP_AAL_EN);
	104	}
	105
	106	static void mtk_aal_stop(struct mtk_ddp_comp *comp)
	107	{
	108	writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
	109	}
	110
e0a5d337 BH	111	static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
	112	unsigned int h, unsigned int vrefresh)
	113	{
	114	writel(h << 16 \| w, comp->regs + DISP_GAMMA_SIZE);
	115	}
	116
	117	static void mtk_gamma_start(struct mtk_ddp_comp *comp)
	118	{
	119	writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
	120	}
	121
	122	static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
	123	{
	124	writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
	125	}
	126
2f3f4dda BH	127	static void mtk_gamma_set(struct mtk_ddp_comp *comp,
	128	struct drm_crtc_state *state)
	129	{
	130	unsigned int i, reg;
	131	struct drm_color_lut *lut;
	132	void __iomem *lut_base;
	133	u32 word;
	134
	135	if (state->gamma_lut) {
	136	reg = readl(comp->regs + DISP_GAMMA_CFG);
	137	reg = reg \| GAMMA_LUT_EN;
	138	writel(reg, comp->regs + DISP_GAMMA_CFG);
	139	lut_base = comp->regs + DISP_GAMMA_LUT;
	140	lut = (struct drm_color_lut *)state->gamma_lut->data;
	141	for (i = 0; i < MTK_LUT_SIZE; i++) {
	142	word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
	143	(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
	144	((lut[i].blue >> 6) & LUT_10BIT_MASK);
	145	writel(word, (lut_base + i * 4));
	146	}
	147	}
	148	}
	149
0664d139	150	static const struct mtk_ddp_comp_funcs ddp_aal = {
2f3f4dda	151	.gamma_set = mtk_gamma_set,
0664d139 BH	152	.config = mtk_aal_config,
	153	.start = mtk_aal_start,
	154	.stop = mtk_aal_stop,
	155	};
	156
e0a5d337	157	static const struct mtk_ddp_comp_funcs ddp_gamma = {
2f3f4dda	158	.gamma_set = mtk_gamma_set,
e0a5d337 BH	159	.config = mtk_gamma_config,
	160	.start = mtk_gamma_start,
	161	.stop = mtk_gamma_stop,
	162	};
	163
119f5173 CH	164	static const struct mtk_ddp_comp_funcs ddp_color = {
	165	.config = mtk_color_config,
	166	.start = mtk_color_start,
	167	};
	168
	169	static const struct mtk_ddp_comp_funcs ddp_od = {
	170	.config = mtk_od_config,
	171	.start = mtk_od_start,
	172	};
	173
	174	static const struct mtk_ddp_comp_funcs ddp_ufoe = {
	175	.start = mtk_ufoe_start,
	176	};
	177
	178	static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
	179	[MTK_DISP_OVL] = "ovl",
	180	[MTK_DISP_RDMA] = "rdma",
	181	[MTK_DISP_WDMA] = "wdma",
	182	[MTK_DISP_COLOR] = "color",
	183	[MTK_DISP_AAL] = "aal",
	184	[MTK_DISP_GAMMA] = "gamma",
	185	[MTK_DISP_UFOE] = "ufoe",
	186	[MTK_DSI] = "dsi",
	187	[MTK_DPI] = "dpi",
	188	[MTK_DISP_PWM] = "pwm",
	189	[MTK_DISP_MUTEX] = "mutex",
	190	[MTK_DISP_OD] = "od",
	191	};
	192
	193	struct mtk_ddp_comp_match {
	194	enum mtk_ddp_comp_type type;
	195	int alias_id;
	196	const struct mtk_ddp_comp_funcs *funcs;
	197	};
	198
	199	static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
0664d139	200	[DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
119f5173 CH	201	[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
	202	[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
	203	[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
	204	[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
	205	[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
e0a5d337	206	[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
119f5173 CH	207	[DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
	208	[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
	209	[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
	210	[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
	211	[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
	212	[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
	213	[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
	214	[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
	215	[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
	216	[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
	217	};
	218
	219	int mtk_ddp_comp_get_id(struct device_node *node,
	220	enum mtk_ddp_comp_type comp_type)
	221	{
	222	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
	223	int i;
	224
	225	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
	226	if (comp_type == mtk_ddp_matches[i].type &&
	227	(id < 0 \|\| id == mtk_ddp_matches[i].alias_id))
	228	return i;
	229	}
	230
	231	return -EINVAL;
	232	}
	233
	234	int mtk_ddp_comp_init(struct device dev, struct device_node node,
	235	struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
	236	const struct mtk_ddp_comp_funcs *funcs)
	237	{
	238	enum mtk_ddp_comp_type type;
	239	struct device_node *larb_node;
	240	struct platform_device *larb_pdev;
	241
	242	if (comp_id < 0 \|\| comp_id >= DDP_COMPONENT_ID_MAX)
	243	return -EINVAL;
	244
	245	comp->id = comp_id;
	246	comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
	247
	248	if (comp_id == DDP_COMPONENT_DPI0 \|\|
	249	comp_id == DDP_COMPONENT_DSI0 \|\|
	250	comp_id == DDP_COMPONENT_PWM0) {
	251	comp->regs = NULL;
	252	comp->clk = NULL;
	253	comp->irq = 0;
	254	return 0;
	255	}
	256
	257	comp->regs = of_iomap(node, 0);
	258	comp->irq = of_irq_get(node, 0);
	259	comp->clk = of_clk_get(node, 0);
	260	if (IS_ERR(comp->clk))
	261	comp->clk = NULL;
	262
	263	type = mtk_ddp_matches[comp_id].type;
	264
	265	/* Only DMA capable components need the LARB property */
	266	comp->larb_dev = NULL;
	267	if (type != MTK_DISP_OVL &&
	268	type != MTK_DISP_RDMA &&
	269	type != MTK_DISP_WDMA)
	270	return 0;
271
272	larb_node = of_parse_phandle(node, "mediatek,larb", 0);
273	if (!larb_node) {
274	dev_err(dev,
275	"Missing mediadek,larb phandle in %s node\n",
276	node->full_name);
277	return -EINVAL;
278	}
279
280	larb_pdev = of_find_device_by_node(larb_node);
281	if (!larb_pdev) {
282	dev_warn(dev, "Waiting for larb device %s\n",
283	larb_node->full_name);
284	of_node_put(larb_node);
285	return -EPROBE_DEFER;
286	}
287	of_node_put(larb_node);
288
289	comp->larb_dev = &larb_pdev->dev;
290
291	return 0;
292	}
293
294	int mtk_ddp_comp_register(struct drm_device drm, struct mtk_ddp_comp comp)
295	{
296	struct mtk_drm_private *private = drm->dev_private;
297
298	if (private->ddp_comp[comp->id])
299	return -EBUSY;
300
301	private->ddp_comp[comp->id] = comp;
302	return 0;
303	}
304
305	void mtk_ddp_comp_unregister(struct drm_device drm, struct mtk_ddp_comp comp)
306	{
307	struct mtk_drm_private *private = drm->dev_private;
308
309	private->ddp_comp[comp->id] = NULL;
310	}