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119f5173 CH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Authors: | |
4 | * YT Shen <yt.shen@mediatek.com> | |
5 | * CK Hu <ck.hu@mediatek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <drm/drmP.h> | |
24 | #include "mtk_drm_drv.h" | |
25 | #include "mtk_drm_plane.h" | |
26 | #include "mtk_drm_ddp_comp.h" | |
27 | ||
28 | #define DISP_OD_EN 0x0000 | |
29 | #define DISP_OD_INTEN 0x0008 | |
30 | #define DISP_OD_INTSTA 0x000c | |
31 | #define DISP_OD_CFG 0x0020 | |
32 | #define DISP_OD_SIZE 0x0030 | |
33 | ||
34 | #define DISP_REG_UFO_START 0x0000 | |
35 | ||
36 | #define DISP_COLOR_CFG_MAIN 0x0400 | |
37 | #define DISP_COLOR_START 0x0c00 | |
38 | #define DISP_COLOR_WIDTH 0x0c50 | |
39 | #define DISP_COLOR_HEIGHT 0x0c54 | |
40 | ||
0664d139 BH |
41 | #define DISP_AAL_EN 0x0000 |
42 | #define DISP_AAL_SIZE 0x0030 | |
43 | ||
e0a5d337 BH |
44 | #define DISP_GAMMA_EN 0x0000 |
45 | #define DISP_GAMMA_SIZE 0x0030 | |
46 | ||
119f5173 CH |
47 | #define OD_RELAY_MODE BIT(0) |
48 | ||
49 | #define UFO_BYPASS BIT(2) | |
50 | ||
51 | #define COLOR_BYPASS_ALL BIT(7) | |
52 | #define COLOR_SEQ_SEL BIT(13) | |
53 | ||
0664d139 BH |
54 | #define AAL_EN BIT(0) |
55 | ||
e0a5d337 BH |
56 | #define GAMMA_EN BIT(0) |
57 | ||
119f5173 CH |
58 | static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, |
59 | unsigned int h, unsigned int vrefresh) | |
60 | { | |
61 | writel(w, comp->regs + DISP_COLOR_WIDTH); | |
62 | writel(h, comp->regs + DISP_COLOR_HEIGHT); | |
63 | } | |
64 | ||
65 | static void mtk_color_start(struct mtk_ddp_comp *comp) | |
66 | { | |
67 | writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL, | |
68 | comp->regs + DISP_COLOR_CFG_MAIN); | |
69 | writel(0x1, comp->regs + DISP_COLOR_START); | |
70 | } | |
71 | ||
72 | static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, | |
73 | unsigned int h, unsigned int vrefresh) | |
74 | { | |
75 | writel(w << 16 | h, comp->regs + DISP_OD_SIZE); | |
76 | } | |
77 | ||
78 | static void mtk_od_start(struct mtk_ddp_comp *comp) | |
79 | { | |
80 | writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG); | |
81 | writel(1, comp->regs + DISP_OD_EN); | |
82 | } | |
83 | ||
84 | static void mtk_ufoe_start(struct mtk_ddp_comp *comp) | |
85 | { | |
86 | writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); | |
87 | } | |
88 | ||
0664d139 BH |
89 | static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, |
90 | unsigned int h, unsigned int vrefresh) | |
91 | { | |
92 | writel(h << 16 | w, comp->regs + DISP_AAL_SIZE); | |
93 | } | |
94 | ||
95 | static void mtk_aal_start(struct mtk_ddp_comp *comp) | |
96 | { | |
97 | writel(AAL_EN, comp->regs + DISP_AAL_EN); | |
98 | } | |
99 | ||
100 | static void mtk_aal_stop(struct mtk_ddp_comp *comp) | |
101 | { | |
102 | writel_relaxed(0x0, comp->regs + DISP_AAL_EN); | |
103 | } | |
104 | ||
e0a5d337 BH |
105 | static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, |
106 | unsigned int h, unsigned int vrefresh) | |
107 | { | |
108 | writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE); | |
109 | } | |
110 | ||
111 | static void mtk_gamma_start(struct mtk_ddp_comp *comp) | |
112 | { | |
113 | writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); | |
114 | } | |
115 | ||
116 | static void mtk_gamma_stop(struct mtk_ddp_comp *comp) | |
117 | { | |
118 | writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); | |
119 | } | |
120 | ||
0664d139 BH |
121 | static const struct mtk_ddp_comp_funcs ddp_aal = { |
122 | .config = mtk_aal_config, | |
123 | .start = mtk_aal_start, | |
124 | .stop = mtk_aal_stop, | |
125 | }; | |
126 | ||
e0a5d337 BH |
127 | static const struct mtk_ddp_comp_funcs ddp_gamma = { |
128 | .config = mtk_gamma_config, | |
129 | .start = mtk_gamma_start, | |
130 | .stop = mtk_gamma_stop, | |
131 | }; | |
132 | ||
119f5173 CH |
133 | static const struct mtk_ddp_comp_funcs ddp_color = { |
134 | .config = mtk_color_config, | |
135 | .start = mtk_color_start, | |
136 | }; | |
137 | ||
138 | static const struct mtk_ddp_comp_funcs ddp_od = { | |
139 | .config = mtk_od_config, | |
140 | .start = mtk_od_start, | |
141 | }; | |
142 | ||
143 | static const struct mtk_ddp_comp_funcs ddp_ufoe = { | |
144 | .start = mtk_ufoe_start, | |
145 | }; | |
146 | ||
147 | static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { | |
148 | [MTK_DISP_OVL] = "ovl", | |
149 | [MTK_DISP_RDMA] = "rdma", | |
150 | [MTK_DISP_WDMA] = "wdma", | |
151 | [MTK_DISP_COLOR] = "color", | |
152 | [MTK_DISP_AAL] = "aal", | |
153 | [MTK_DISP_GAMMA] = "gamma", | |
154 | [MTK_DISP_UFOE] = "ufoe", | |
155 | [MTK_DSI] = "dsi", | |
156 | [MTK_DPI] = "dpi", | |
157 | [MTK_DISP_PWM] = "pwm", | |
158 | [MTK_DISP_MUTEX] = "mutex", | |
159 | [MTK_DISP_OD] = "od", | |
160 | }; | |
161 | ||
162 | struct mtk_ddp_comp_match { | |
163 | enum mtk_ddp_comp_type type; | |
164 | int alias_id; | |
165 | const struct mtk_ddp_comp_funcs *funcs; | |
166 | }; | |
167 | ||
168 | static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { | |
0664d139 | 169 | [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, |
119f5173 CH |
170 | [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, |
171 | [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, | |
172 | [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, | |
173 | [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, | |
174 | [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, | |
e0a5d337 | 175 | [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, |
119f5173 CH |
176 | [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, |
177 | [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, | |
178 | [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, | |
179 | [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, | |
180 | [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, | |
181 | [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, | |
182 | [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, | |
183 | [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, | |
184 | [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, | |
185 | [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, | |
186 | }; | |
187 | ||
188 | int mtk_ddp_comp_get_id(struct device_node *node, | |
189 | enum mtk_ddp_comp_type comp_type) | |
190 | { | |
191 | int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); | |
192 | int i; | |
193 | ||
194 | for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { | |
195 | if (comp_type == mtk_ddp_matches[i].type && | |
196 | (id < 0 || id == mtk_ddp_matches[i].alias_id)) | |
197 | return i; | |
198 | } | |
199 | ||
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | int mtk_ddp_comp_init(struct device *dev, struct device_node *node, | |
204 | struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, | |
205 | const struct mtk_ddp_comp_funcs *funcs) | |
206 | { | |
207 | enum mtk_ddp_comp_type type; | |
208 | struct device_node *larb_node; | |
209 | struct platform_device *larb_pdev; | |
210 | ||
211 | if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) | |
212 | return -EINVAL; | |
213 | ||
214 | comp->id = comp_id; | |
215 | comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; | |
216 | ||
217 | if (comp_id == DDP_COMPONENT_DPI0 || | |
218 | comp_id == DDP_COMPONENT_DSI0 || | |
219 | comp_id == DDP_COMPONENT_PWM0) { | |
220 | comp->regs = NULL; | |
221 | comp->clk = NULL; | |
222 | comp->irq = 0; | |
223 | return 0; | |
224 | } | |
225 | ||
226 | comp->regs = of_iomap(node, 0); | |
227 | comp->irq = of_irq_get(node, 0); | |
228 | comp->clk = of_clk_get(node, 0); | |
229 | if (IS_ERR(comp->clk)) | |
230 | comp->clk = NULL; | |
231 | ||
232 | type = mtk_ddp_matches[comp_id].type; | |
233 | ||
234 | /* Only DMA capable components need the LARB property */ | |
235 | comp->larb_dev = NULL; | |
236 | if (type != MTK_DISP_OVL && | |
237 | type != MTK_DISP_RDMA && | |
238 | type != MTK_DISP_WDMA) | |
239 | return 0; | |
240 | ||
241 | larb_node = of_parse_phandle(node, "mediatek,larb", 0); | |
242 | if (!larb_node) { | |
243 | dev_err(dev, | |
244 | "Missing mediadek,larb phandle in %s node\n", | |
245 | node->full_name); | |
246 | return -EINVAL; | |
247 | } | |
248 | ||
249 | larb_pdev = of_find_device_by_node(larb_node); | |
250 | if (!larb_pdev) { | |
251 | dev_warn(dev, "Waiting for larb device %s\n", | |
252 | larb_node->full_name); | |
253 | of_node_put(larb_node); | |
254 | return -EPROBE_DEFER; | |
255 | } | |
256 | of_node_put(larb_node); | |
257 | ||
258 | comp->larb_dev = &larb_pdev->dev; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) | |
264 | { | |
265 | struct mtk_drm_private *private = drm->dev_private; | |
266 | ||
267 | if (private->ddp_comp[comp->id]) | |
268 | return -EBUSY; | |
269 | ||
270 | private->ddp_comp[comp->id] = comp; | |
271 | return 0; | |
272 | } | |
273 | ||
274 | void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) | |
275 | { | |
276 | struct mtk_drm_private *private = drm->dev_private; | |
277 | ||
278 | private->ddp_comp[comp->id] = NULL; | |
279 | } |