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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / mediatek / mtk_dsi.c
CommitLineData
2e54c14e
CH		 1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19#include <linux/clk.h>
20#include <linux/component.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/of_graph.h>
24#include <linux/phy/phy.h>
25#include <linux/platform_device.h>
26#include <video/videomode.h>
27
28#include "mtk_drm_ddp_comp.h"
29
30#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
31#define DSI_HOST_FIFO_DEPTH 64
32
33#define DSI_START 0x00
34
35#define DSI_CON_CTRL 0x10
36#define DSI_RESET BIT(0)
37#define DSI_EN BIT(1)
38
39#define DSI_MODE_CTRL 0x14
40#define MODE (3)
41#define CMD_MODE 0
42#define SYNC_PULSE_MODE 1
43#define SYNC_EVENT_MODE 2
44#define BURST_MODE 3
45#define FRM_MODE BIT(16)
46#define MIX_MODE BIT(17)
47
48#define DSI_TXRX_CTRL 0x18
49#define VC_NUM (2 << 0)
50#define LANE_NUM (0xf << 2)
51#define DIS_EOT BIT(6)
52#define NULL_EN BIT(7)
53#define TE_FREERUN BIT(8)
54#define EXT_TE_EN BIT(9)
55#define EXT_TE_EDGE BIT(10)
56#define MAX_RTN_SIZE (0xf << 12)
57#define HSTX_CKLP_EN BIT(16)
58
59#define DSI_PSCTRL 0x1c
60#define DSI_PS_WC 0x3fff
61#define DSI_PS_SEL (3 << 16)
62#define PACKED_PS_16BIT_RGB565 (0 << 16)
63#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
64#define PACKED_PS_18BIT_RGB666 (2 << 16)
65#define PACKED_PS_24BIT_RGB888 (3 << 16)
66
67#define DSI_VSA_NL 0x20
68#define DSI_VBP_NL 0x24
69#define DSI_VFP_NL 0x28
70#define DSI_VACT_NL 0x2C
71#define DSI_HSA_WC 0x50
72#define DSI_HBP_WC 0x54
73#define DSI_HFP_WC 0x58
74
75#define DSI_HSTX_CKL_WC 0x64
76
77#define DSI_PHY_LCCON 0x104
78#define LC_HS_TX_EN BIT(0)
79#define LC_ULPM_EN BIT(1)
80#define LC_WAKEUP_EN BIT(2)
81
82#define DSI_PHY_LD0CON 0x108
83#define LD0_HS_TX_EN BIT(0)
84#define LD0_ULPM_EN BIT(1)
85#define LD0_WAKEUP_EN BIT(2)
86
87#define DSI_PHY_TIMECON0 0x110
88#define LPX (0xff << 0)
89#define HS_PRPR (0xff << 8)
90#define HS_ZERO (0xff << 16)
91#define HS_TRAIL (0xff << 24)
92
93#define DSI_PHY_TIMECON1 0x114
94#define TA_GO (0xff << 0)
95#define TA_SURE (0xff << 8)
96#define TA_GET (0xff << 16)
97#define DA_HS_EXIT (0xff << 24)
98
99#define DSI_PHY_TIMECON2 0x118
100#define CONT_DET (0xff << 0)
101#define CLK_ZERO (0xff << 16)
102#define CLK_TRAIL (0xff << 24)
103
104#define DSI_PHY_TIMECON3 0x11c
105#define CLK_HS_PRPR (0xff << 0)
106#define CLK_HS_POST (0xff << 8)
107#define CLK_HS_EXIT (0xff << 16)
108
109#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
110
111struct phy;
112
113struct mtk_dsi {
114 struct mtk_ddp_comp ddp_comp;
115 struct device *dev;
116 struct mipi_dsi_host host;
117 struct drm_encoder encoder;
118 struct drm_connector conn;
119 struct drm_panel *panel;
120 struct drm_bridge *bridge;
121 struct phy *phy;
122
123 void __iomem *regs;
124
125 struct clk *engine_clk;
126 struct clk *digital_clk;
127 struct clk *hs_clk;
128
129 u32 data_rate;
130
131 unsigned long mode_flags;
132 enum mipi_dsi_pixel_format format;
133 unsigned int lanes;
134 struct videomode vm;
135 int refcount;
136 bool enabled;
137};
138
139static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
140{
141 return container_of(e, struct mtk_dsi, encoder);
142}
143
144static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
145{
146 return container_of(c, struct mtk_dsi, conn);
147}
148
149static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
150{
151 return container_of(h, struct mtk_dsi, host);
152}
153
154static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
155{
156 u32 temp = readl(dsi->regs + offset);
157
158 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
159}
160
161static void dsi_phy_timconfig(struct mtk_dsi *dsi)
162{
163 u32 timcon0, timcon1, timcon2, timcon3;
164 unsigned int ui, cycle_time;
165 unsigned int lpx;
166
167 ui = 1000 / dsi->data_rate + 0x01;
168 cycle_time = 8000 / dsi->data_rate + 0x01;
169 lpx = 5;
170
171 timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
172 timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
173 (4 * lpx);
174 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
175 (NS_TO_CYCLE(0x150, cycle_time) << 16);
176 timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
177 NS_TO_CYCLE(0x40, cycle_time);
178
179 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
180 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
181 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
182 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
183}
184
185static void mtk_dsi_enable(struct mtk_dsi *dsi)
186{
187 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
188}
189
190static void mtk_dsi_disable(struct mtk_dsi *dsi)
191{
192 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
193}
194
195static void mtk_dsi_reset(struct mtk_dsi *dsi)
196{
197 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
198 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
199}
200
201static int mtk_dsi_poweron(struct mtk_dsi *dsi)
202{
203 struct device *dev = dsi->dev;
204 int ret;
205
206 if (++dsi->refcount != 1)
207 return 0;
208
209 /**
210 * data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
211 * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
212 * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
213 * we set mipi_ratio is 1.05.
214 */
215 dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
216
217 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000);
218 if (ret < 0) {
219 dev_err(dev, "Failed to set data rate: %d\n", ret);
220 goto err_refcount;
221 }
222
223 phy_power_on(dsi->phy);
224
225 ret = clk_prepare_enable(dsi->engine_clk);
226 if (ret < 0) {
227 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
228 goto err_phy_power_off;
229 }
230
231 ret = clk_prepare_enable(dsi->digital_clk);
232 if (ret < 0) {
233 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
234 goto err_disable_engine_clk;
235 }
236
237 mtk_dsi_enable(dsi);
238 mtk_dsi_reset(dsi);
239 dsi_phy_timconfig(dsi);
240
241 return 0;
242
243err_disable_engine_clk:
244 clk_disable_unprepare(dsi->engine_clk);
245err_phy_power_off:
246 phy_power_off(dsi->phy);
247err_refcount:
248 dsi->refcount--;
249 return ret;
250}
251
252static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
253{
254 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
255 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
256}
257
258static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
259{
260 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
261 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
262 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
263}
264
265static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
266{
267 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
268 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
269}
270
271static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
272{
273 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
274 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
275 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
276}
277
278static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
279{
280 u32 tmp_reg1;
281
282 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
283 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
284}
285
286static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
287{
288 if (enter && !dsi_clk_hs_state(dsi))
289 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
290 else if (!enter && dsi_clk_hs_state(dsi))
291 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
292}
293
294static void dsi_set_mode(struct mtk_dsi *dsi)
295{
296 u32 vid_mode = CMD_MODE;
297
298 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
299 vid_mode = SYNC_PULSE_MODE;
300
301 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
302 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
303 vid_mode = BURST_MODE;
304 }
305
306 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
307}
308
309static void dsi_ps_control_vact(struct mtk_dsi *dsi)
310{
311 struct videomode *vm = &dsi->vm;
312 u32 dsi_buf_bpp, ps_wc;
313 u32 ps_bpp_mode;
314
315 if (dsi->format == MIPI_DSI_FMT_RGB565)
316 dsi_buf_bpp = 2;
317 else
318 dsi_buf_bpp = 3;
319
320 ps_wc = vm->hactive * dsi_buf_bpp;
321 ps_bpp_mode = ps_wc;
322
323 switch (dsi->format) {
324 case MIPI_DSI_FMT_RGB888:
325 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
326 break;
327 case MIPI_DSI_FMT_RGB666:
328 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
329 break;
330 case MIPI_DSI_FMT_RGB666_PACKED:
331 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
332 break;
333 case MIPI_DSI_FMT_RGB565:
334 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
335 break;
336 }
337
338 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
339 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
340 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
341}
342
343static void dsi_rxtx_control(struct mtk_dsi *dsi)
344{
345 u32 tmp_reg;
346
347 switch (dsi->lanes) {
348 case 1:
349 tmp_reg = 1 << 2;
350 break;
351 case 2:
352 tmp_reg = 3 << 2;
353 break;
354 case 3:
355 tmp_reg = 7 << 2;
356 break;
357 case 4:
358 tmp_reg = 0xf << 2;
359 break;
360 default:
361 tmp_reg = 0xf << 2;
362 break;
363 }
364
365 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
366}
367
368static void dsi_ps_control(struct mtk_dsi *dsi)
369{
370 unsigned int dsi_tmp_buf_bpp;
371 u32 tmp_reg;
372
373 switch (dsi->format) {
374 case MIPI_DSI_FMT_RGB888:
375 tmp_reg = PACKED_PS_24BIT_RGB888;
376 dsi_tmp_buf_bpp = 3;
377 break;
378 case MIPI_DSI_FMT_RGB666:
379 tmp_reg = LOOSELY_PS_18BIT_RGB666;
380 dsi_tmp_buf_bpp = 3;
381 break;
382 case MIPI_DSI_FMT_RGB666_PACKED:
383 tmp_reg = PACKED_PS_18BIT_RGB666;
384 dsi_tmp_buf_bpp = 3;
385 break;
386 case MIPI_DSI_FMT_RGB565:
387 tmp_reg = PACKED_PS_16BIT_RGB565;
388 dsi_tmp_buf_bpp = 2;
389 break;
390 default:
391 tmp_reg = PACKED_PS_24BIT_RGB888;
392 dsi_tmp_buf_bpp = 3;
393 break;
394 }
395
396 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
397 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
398}
399
400static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
401{
402 unsigned int horizontal_sync_active_byte;
403 unsigned int horizontal_backporch_byte;
404 unsigned int horizontal_frontporch_byte;
405 unsigned int dsi_tmp_buf_bpp;
406
407 struct videomode *vm = &dsi->vm;
408
409 if (dsi->format == MIPI_DSI_FMT_RGB565)
410 dsi_tmp_buf_bpp = 2;
411 else
412 dsi_tmp_buf_bpp = 3;
413
414 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
415 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
416 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
417 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
418
419 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
420
421 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
422 horizontal_backporch_byte =
423 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
424 else
425 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
426 dsi_tmp_buf_bpp - 10);
427
428 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
429
430 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
431 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
432 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
433
434 dsi_ps_control(dsi);
435}
436
437static void mtk_dsi_start(struct mtk_dsi *dsi)
438{
439 writel(0, dsi->regs + DSI_START);
440 writel(1, dsi->regs + DSI_START);
441}
442
443static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
444{
445 if (WARN_ON(dsi->refcount == 0))
446 return;
447
448 if (--dsi->refcount != 0)
449 return;
450
451 dsi_lane0_ulp_mode_enter(dsi);
452 dsi_clk_ulp_mode_enter(dsi);
453
454 mtk_dsi_disable(dsi);
455
456 clk_disable_unprepare(dsi->engine_clk);
457 clk_disable_unprepare(dsi->digital_clk);
458
459 phy_power_off(dsi->phy);
460}
461
462static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
463{
464 int ret;
465
466 if (dsi->enabled)
467 return;
468
469 if (dsi->panel) {
470 if (drm_panel_prepare(dsi->panel)) {
471 DRM_ERROR("failed to setup the panel\n");
472 return;
473 }
474 }
475
476 ret = mtk_dsi_poweron(dsi);
477 if (ret < 0) {
478 DRM_ERROR("failed to power on dsi\n");
479 return;
480 }
481
482 dsi_rxtx_control(dsi);
483
484 dsi_clk_ulp_mode_leave(dsi);
485 dsi_lane0_ulp_mode_leave(dsi);
486 dsi_clk_hs_mode(dsi, 0);
487 dsi_set_mode(dsi);
488
489 dsi_ps_control_vact(dsi);
490 dsi_config_vdo_timing(dsi);
491
492 dsi_set_mode(dsi);
493 dsi_clk_hs_mode(dsi, 1);
494
495 mtk_dsi_start(dsi);
496
497 dsi->enabled = true;
498}
499
500static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
501{
502 if (!dsi->enabled)
503 return;
504
505 if (dsi->panel) {
506 if (drm_panel_disable(dsi->panel)) {
507 DRM_ERROR("failed to disable the panel\n");
508 return;
509 }
510 }
511
512 mtk_dsi_poweroff(dsi);
513
514 dsi->enabled = false;
515}
516
517static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
518{
519 drm_encoder_cleanup(encoder);
520}
521
522static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
523 .destroy = mtk_dsi_encoder_destroy,
524};
525
526static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
527 const struct drm_display_mode *mode,
528 struct drm_display_mode *adjusted_mode)
529{
530 return true;
531}
532
533static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
534 struct drm_display_mode *mode,
535 struct drm_display_mode *adjusted)
536{
537 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
538
539 dsi->vm.pixelclock = adjusted->clock;
540 dsi->vm.hactive = adjusted->hdisplay;
541 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
542 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
543 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
544
545 dsi->vm.vactive = adjusted->vdisplay;
546 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
547 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
548 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
549}
550
551static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
552{
553 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
554
555 mtk_output_dsi_disable(dsi);
556}
557
558static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
559{
560 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
561
562 mtk_output_dsi_enable(dsi);
563}
564
565static enum drm_connector_status mtk_dsi_connector_detect(
566 struct drm_connector *connector, bool force)
567{
568 return connector_status_connected;
569}
570
571static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
572{
573 struct mtk_dsi *dsi = connector_to_dsi(connector);
574
575 return drm_panel_get_modes(dsi->panel);
576}
577
2e54c14e
CH		 578static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
579 .mode_fixup = mtk_dsi_encoder_mode_fixup,
580 .mode_set = mtk_dsi_encoder_mode_set,
581 .disable = mtk_dsi_encoder_disable,
582 .enable = mtk_dsi_encoder_enable,
583};
584
585static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
586 .dpms = drm_atomic_helper_connector_dpms,
587 .detect = mtk_dsi_connector_detect,
588 .fill_modes = drm_helper_probe_single_connector_modes,
589 .destroy = drm_connector_cleanup,
590 .reset = drm_atomic_helper_connector_reset,
591 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
592 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
593};
594
595static const struct drm_connector_helper_funcs
596 mtk_dsi_connector_helper_funcs = {
597 .get_modes = mtk_dsi_connector_get_modes,
2e54c14e
CH		 598};
599
600static int mtk_drm_attach_bridge(struct drm_bridge *bridge,
601 struct drm_encoder *encoder)
602{
603 int ret;
604
605 if (!bridge)
606 return -ENOENT;
607
608 encoder->bridge = bridge;
609 bridge->encoder = encoder;
610 ret = drm_bridge_attach(encoder->dev, bridge);
611 if (ret) {
612 DRM_ERROR("Failed to attach bridge to drm\n");
613 encoder->bridge = NULL;
614 bridge->encoder = NULL;
615 }
616
617 return ret;
618}
619
620static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
621{
622 int ret;
623
624 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
625 DRM_MODE_CONNECTOR_DSI);
626 if (ret) {
627 DRM_ERROR("Failed to connector init to drm\n");
628 return ret;
629 }
630
631 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
632
633 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
634 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
635
636 if (dsi->panel) {
637 ret = drm_panel_attach(dsi->panel, &dsi->conn);
638 if (ret) {
639 DRM_ERROR("Failed to attach panel to drm\n");
640 goto err_connector_cleanup;
641 }
642 }
643
644 return 0;
645
646err_connector_cleanup:
647 drm_connector_cleanup(&dsi->conn);
648 return ret;
649}
650
651static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
652{
653 int ret;
654
655 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
656 DRM_MODE_ENCODER_DSI, NULL);
657 if (ret) {
658 DRM_ERROR("Failed to encoder init to drm\n");
659 return ret;
660 }
661 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
662
663 /*
664 * Currently display data paths are statically assigned to a crtc each.
665 * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
666 */
667 dsi->encoder.possible_crtcs = 1;
668
669 /* If there's a bridge, attach to it and let it create the connector */
670 ret = mtk_drm_attach_bridge(dsi->bridge, &dsi->encoder);
671 if (ret) {
672 /* Otherwise create our own connector and attach to a panel */
673 ret = mtk_dsi_create_connector(drm, dsi);
674 if (ret)
675 goto err_encoder_cleanup;
676 }
677
678 return 0;
679
680err_encoder_cleanup:
681 drm_encoder_cleanup(&dsi->encoder);
682 return ret;
683}
684
685static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
686{
687 drm_encoder_cleanup(&dsi->encoder);
688 /* Skip connector cleanup if creation was delegated to the bridge */
2ea9f317 689 if (dsi->conn.dev)
2e54c14e 690 drm_connector_cleanup(&dsi->conn);
2e54c14e
CH		 691}
692
693static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
694{
695 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
696
697 mtk_dsi_poweron(dsi);
698}
699
700static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
701{
702 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
703
704 mtk_dsi_poweroff(dsi);
705}
706
707static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
708 .start = mtk_dsi_ddp_start,
709 .stop = mtk_dsi_ddp_stop,
710};
711
712static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
713 struct mipi_dsi_device *device)
714{
715 struct mtk_dsi *dsi = host_to_dsi(host);
716
717 dsi->lanes = device->lanes;
718 dsi->format = device->format;
719 dsi->mode_flags = device->mode_flags;
720
721 if (dsi->conn.dev)
722 drm_helper_hpd_irq_event(dsi->conn.dev);
723
724 return 0;
725}
726
727static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
728 struct mipi_dsi_device *device)
729{
730 struct mtk_dsi *dsi = host_to_dsi(host);
731
732 if (dsi->conn.dev)
733 drm_helper_hpd_irq_event(dsi->conn.dev);
734
735 return 0;
736}
737
738static const struct mipi_dsi_host_ops mtk_dsi_ops = {
739 .attach = mtk_dsi_host_attach,
740 .detach = mtk_dsi_host_detach,
741};
742
743static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
744{
745 int ret;
746 struct drm_device *drm = data;
747 struct mtk_dsi *dsi = dev_get_drvdata(dev);
748
749 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
750 if (ret < 0) {
751 dev_err(dev, "Failed to register component %s: %d\n",
752 dev->of_node->full_name, ret);
753 return ret;
754 }
755
756 ret = mipi_dsi_host_register(&dsi->host);
757 if (ret < 0) {
758 dev_err(dev, "failed to register DSI host: %d\n", ret);
759 goto err_ddp_comp_unregister;
760 }
761
762 ret = mtk_dsi_create_conn_enc(drm, dsi);
763 if (ret) {
764 DRM_ERROR("Encoder create failed with %d\n", ret);
765 goto err_unregister;
766 }
767
768 return 0;
769
770err_unregister:
771 mipi_dsi_host_unregister(&dsi->host);
772err_ddp_comp_unregister:
773 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
774 return ret;
775}
776
777static void mtk_dsi_unbind(struct device *dev, struct device *master,
778 void *data)
779{
780 struct drm_device *drm = data;
781 struct mtk_dsi *dsi = dev_get_drvdata(dev);
782
783 mtk_dsi_destroy_conn_enc(dsi);
784 mipi_dsi_host_unregister(&dsi->host);
785 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
786}
787
788static const struct component_ops mtk_dsi_component_ops = {
789 .bind = mtk_dsi_bind,
790 .unbind = mtk_dsi_unbind,
791};
792
793static int mtk_dsi_probe(struct platform_device *pdev)
794{
795 struct mtk_dsi *dsi;
796 struct device *dev = &pdev->dev;
797 struct device_node *remote_node, *endpoint;
798 struct resource *regs;
799 int comp_id;
800 int ret;
801
802 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
803 if (!dsi)
804 return -ENOMEM;
805
806 dsi->host.ops = &mtk_dsi_ops;
807 dsi->host.dev = dev;
808
809 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
810 if (endpoint) {
811 remote_node = of_graph_get_remote_port_parent(endpoint);
812 if (!remote_node) {
813 dev_err(dev, "No panel connected\n");
814 return -ENODEV;
815 }
816
817 dsi->bridge = of_drm_find_bridge(remote_node);
818 dsi->panel = of_drm_find_panel(remote_node);
819 of_node_put(remote_node);
820 if (!dsi->bridge && !dsi->panel) {
821 dev_info(dev, "Waiting for bridge or panel driver\n");
822 return -EPROBE_DEFER;
823 }
824 }
825
826 dsi->engine_clk = devm_clk_get(dev, "engine");
827 if (IS_ERR(dsi->engine_clk)) {
828 ret = PTR_ERR(dsi->engine_clk);
829 dev_err(dev, "Failed to get engine clock: %d\n", ret);
830 return ret;
831 }
832
833 dsi->digital_clk = devm_clk_get(dev, "digital");
834 if (IS_ERR(dsi->digital_clk)) {
835 ret = PTR_ERR(dsi->digital_clk);
836 dev_err(dev, "Failed to get digital clock: %d\n", ret);
837 return ret;
838 }
839
840 dsi->hs_clk = devm_clk_get(dev, "hs");
841 if (IS_ERR(dsi->hs_clk)) {
842 ret = PTR_ERR(dsi->hs_clk);
843 dev_err(dev, "Failed to get hs clock: %d\n", ret);
844 return ret;
845 }
846
847 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 dsi->regs = devm_ioremap_resource(dev, regs);
849 if (IS_ERR(dsi->regs)) {
850 ret = PTR_ERR(dsi->regs);
851 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
852 return ret;
853 }
854
855 dsi->phy = devm_phy_get(dev, "dphy");
856 if (IS_ERR(dsi->phy)) {
857 ret = PTR_ERR(dsi->phy);
858 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
859 return ret;
860 }
861
862 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
863 if (comp_id < 0) {
864 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
865 return comp_id;
866 }
867
868 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
869 &mtk_dsi_funcs);
870 if (ret) {
871 dev_err(dev, "Failed to initialize component: %d\n", ret);
872 return ret;
873 }
874
875 platform_set_drvdata(pdev, dsi);
876
877 return component_add(&pdev->dev, &mtk_dsi_component_ops);
878}
879
880static int mtk_dsi_remove(struct platform_device *pdev)
881{
882 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
883
884 mtk_output_dsi_disable(dsi);
885 component_del(&pdev->dev, &mtk_dsi_component_ops);
886
887 return 0;
888}
889
890static const struct of_device_id mtk_dsi_of_match[] = {
891 { .compatible = "mediatek,mt8173-dsi" },
892 { },
893};
894
895struct platform_driver mtk_dsi_driver = {
896 .probe = mtk_dsi_probe,
897 .remove = mtk_dsi_remove,
898 .driver = {
899 .name = "mtk-dsi",
900 .of_match_table = mtk_dsi_of_match,
901 },
902};
Linux kernel - Deliverables
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