projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8f83f268 JQ |
1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. | |
| 3 | * Author: Jie Qiu <jie.qiu@mediatek.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | */ | |
| 14 | #ifndef _MTK_HDMI_REGS_H | |
| 15 | #define _MTK_HDMI_REGS_H | |
| 16 | ||
| 17 | #define GRL_INT_MASK 0x18 | |
| 18 | #define GRL_IFM_PORT 0x188 | |
| 19 | #define GRL_CH_SWAP 0x198 | |
| 20 | #define LR_SWAP BIT(0) | |
| 21 | #define LFE_CC_SWAP BIT(1) | |
| 22 | #define LSRS_SWAP BIT(2) | |
| 23 | #define RLS_RRS_SWAP BIT(3) | |
| 24 | #define LR_STATUS_SWAP BIT(4) | |
| 25 | #define GRL_I2S_C_STA0 0x140 | |
| 26 | #define GRL_I2S_C_STA1 0x144 | |
| 27 | #define GRL_I2S_C_STA2 0x148 | |
| 28 | #define GRL_I2S_C_STA3 0x14C | |
| 29 | #define GRL_I2S_C_STA4 0x150 | |
| 30 | #define GRL_I2S_UV 0x154 | |
| 31 | #define I2S_UV_V BIT(0) | |
| 32 | #define I2S_UV_U BIT(1) | |
| 33 | #define I2S_UV_CH_EN_MASK 0x3c | |
| 34 | #define I2S_UV_CH_EN(x) BIT((x) + 2) | |
| 35 | #define I2S_UV_TMDS_DEBUG BIT(6) | |
| 36 | #define I2S_UV_NORMAL_INFO_INV BIT(7) | |
| 37 | #define GRL_ACP_ISRC_CTRL 0x158 | |
| 38 | #define VS_EN BIT(0) | |
| 39 | #define ACP_EN BIT(1) | |
| 40 | #define ISRC1_EN BIT(2) | |
| 41 | #define ISRC2_EN BIT(3) | |
| 42 | #define GAMUT_EN BIT(4) | |
| 43 | #define GRL_CTS_CTRL 0x160 | |
| 44 | #define CTS_CTRL_SOFT BIT(0) | |
| 45 | #define GRL_INT 0x14 | |
| 46 | #define INT_MDI BIT(0) | |
| 47 | #define INT_HDCP BIT(1) | |
| 48 | #define INT_FIFO_O BIT(2) | |
| 49 | #define INT_FIFO_U BIT(3) | |
| 50 | #define INT_IFM_ERR BIT(4) | |
| 51 | #define INT_INF_DONE BIT(5) | |
| 52 | #define INT_NCTS_DONE BIT(6) | |
| 53 | #define INT_CTRL_PKT_DONE BIT(7) | |
| 54 | #define GRL_INT_MASK 0x18 | |
| 55 | #define GRL_CTRL 0x1C | |
| 56 | #define CTRL_GEN_EN BIT(2) | |
| 57 | #define CTRL_SPD_EN BIT(3) | |
| 58 | #define CTRL_MPEG_EN BIT(4) | |
| 59 | #define CTRL_AUDIO_EN BIT(5) | |
| 60 | #define CTRL_AVI_EN BIT(6) | |
| 61 | #define CTRL_AVMUTE BIT(7) | |
| 62 | #define GRL_STATUS 0x20 | |
| 63 | #define STATUS_HTPLG BIT(0) | |
| 64 | #define STATUS_PORD BIT(1) | |
| 65 | #define GRL_DIVN 0x170 | |
| 66 | #define NCTS_WRI_ANYTIME BIT(6) | |
| 67 | #define GRL_AUDIO_CFG 0x17C | |
| 68 | #define AUDIO_ZERO BIT(0) | |
| 69 | #define HIGH_BIT_RATE BIT(1) | |
| 70 | #define SACD_DST BIT(2) | |
| 71 | #define DST_NORMAL_DOUBLE BIT(3) | |
| 72 | #define DSD_INV BIT(4) | |
| 73 | #define LR_INV BIT(5) | |
| 74 | #define LR_MIX BIT(6) | |
| 75 | #define DSD_SEL BIT(7) | |
| 76 | #define GRL_NCTS 0x184 | |
| 77 | #define GRL_CH_SW0 0x18C | |
| 78 | #define GRL_CH_SW1 0x190 | |
| 79 | #define GRL_CH_SW2 0x194 | |
| 80 | #define CH_SWITCH(from, to) ((from) << ((to) * 3)) | |
| 81 | #define GRL_INFOFRM_VER 0x19C | |
| 82 | #define GRL_INFOFRM_TYPE 0x1A0 | |
| 83 | #define GRL_INFOFRM_LNG 0x1A4 | |
| 84 | #define GRL_MIX_CTRL 0x1B4 | |
| 85 | #define MIX_CTRL_SRC_EN BIT(0) | |
| 86 | #define BYPASS_VOLUME BIT(1) | |
| 87 | #define MIX_CTRL_FLAT BIT(7) | |
| 88 | #define GRL_AOUT_CFG 0x1C4 | |
| 89 | #define AOUT_BNUM_SEL_MASK 0x03 | |
| 90 | #define AOUT_24BIT 0x00 | |
| 91 | #define AOUT_20BIT 0x02 | |
| 92 | #define AOUT_16BIT 0x03 | |
| 93 | #define AOUT_FIFO_ADAP_CTRL BIT(6) | |
| 94 | #define AOUT_BURST_PREAMBLE_EN BIT(7) | |
| 95 | #define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \ | |
| 96 | AOUT_FIFO_ADAP_CTRL) | |
| 97 | #define GRL_SHIFT_L1 0x1C0 | |
| 98 | #define GRL_SHIFT_R2 0x1B0 | |
| 99 | #define AUDIO_PACKET_OFF BIT(6) | |
| 100 | #define GRL_CFG0 0x24 | |
| 101 | #define CFG0_I2S_MODE_MASK 0x3 | |
| 102 | #define CFG0_I2S_MODE_RTJ 0x1 | |
| 103 | #define CFG0_I2S_MODE_LTJ 0x0 | |
| 104 | #define CFG0_I2S_MODE_I2S 0x2 | |
| 105 | #define CFG0_W_LENGTH_MASK 0x30 | |
| 106 | #define CFG0_W_LENGTH_24BIT 0x00 | |
| 107 | #define CFG0_W_LENGTH_16BIT 0x10 | |
| 108 | #define GRL_CFG1 0x28 | |
| 109 | #define CFG1_EDG_SEL BIT(0) | |
| 110 | #define CFG1_SPDIF BIT(1) | |
| 111 | #define CFG1_DVI BIT(2) | |
| 112 | #define CFG1_HDCP_DEBUG BIT(3) | |
| 113 | #define GRL_CFG2 0x2c | |
| 114 | #define CFG2_MHL_DE_SEL BIT(3) | |
| 115 | #define CFG2_MHL_FAKE_DE_SEL BIT(4) | |
| 116 | #define CFG2_MHL_DATA_REMAP BIT(5) | |
| 117 | #define CFG2_NOTICE_EN BIT(6) | |
| 118 | #define CFG2_ACLK_INV BIT(7) | |
| 119 | #define GRL_CFG3 0x30 | |
| 120 | #define CFG3_AES_KEY_INDEX_MASK 0x3f | |
| 121 | #define CFG3_CONTROL_PACKET_DELAY BIT(6) | |
| 122 | #define CFG3_KSV_LOAD_START BIT(7) | |
| 123 | #define GRL_CFG4 0x34 | |
| 124 | #define CFG4_AES_KEY_LOAD BIT(4) | |
| 125 | #define CFG4_AV_UNMUTE_EN BIT(5) | |
| 126 | #define CFG4_AV_UNMUTE_SET BIT(6) | |
| 127 | #define CFG4_MHL_MODE BIT(7) | |
| 128 | #define GRL_CFG5 0x38 | |
| 129 | #define CFG5_CD_RATIO_MASK 0x8F | |
| 130 | #define CFG5_FS128 (0x1 << 4) | |
| 131 | #define CFG5_FS256 (0x2 << 4) | |
| 132 | #define CFG5_FS384 (0x3 << 4) | |
| 133 | #define CFG5_FS512 (0x4 << 4) | |
| 134 | #define CFG5_FS768 (0x6 << 4) | |
| 135 | #define DUMMY_304 0x304 | |
| 136 | #define CHMO_SEL (0x3 << 2) | |
| 137 | #define CHM1_SEL (0x3 << 4) | |
| 138 | #define CHM2_SEL (0x3 << 6) | |
| 139 | #define AUDIO_I2S_NCTS_SEL BIT(1) | |
| 140 | #define AUDIO_I2S_NCTS_SEL_64 (1 << 1) | |
| 141 | #define AUDIO_I2S_NCTS_SEL_128 (0 << 1) | |
| 142 | #define NEW_GCP_CTRL BIT(0) | |
| 143 | #define NEW_GCP_CTRL_MERGE BIT(0) | |
| 144 | #define GRL_L_STATUS_0 0x200 | |
| 145 | #define GRL_L_STATUS_1 0x204 | |
| 146 | #define GRL_L_STATUS_2 0x208 | |
| 147 | #define GRL_L_STATUS_3 0x20c | |
| 148 | #define GRL_L_STATUS_4 0x210 | |
| 149 | #define GRL_L_STATUS_5 0x214 | |
| 150 | #define GRL_L_STATUS_6 0x218 | |
| 151 | #define GRL_L_STATUS_7 0x21c | |
| 152 | #define GRL_L_STATUS_8 0x220 | |
| 153 | #define GRL_L_STATUS_9 0x224 | |
| 154 | #define GRL_L_STATUS_10 0x228 | |
| 155 | #define GRL_L_STATUS_11 0x22c | |
| 156 | #define GRL_L_STATUS_12 0x230 | |
| 157 | #define GRL_L_STATUS_13 0x234 | |
| 158 | #define GRL_L_STATUS_14 0x238 | |
| 159 | #define GRL_L_STATUS_15 0x23c | |
| 160 | #define GRL_L_STATUS_16 0x240 | |
| 161 | #define GRL_L_STATUS_17 0x244 | |
| 162 | #define GRL_L_STATUS_18 0x248 | |
| 163 | #define GRL_L_STATUS_19 0x24c | |
| 164 | #define GRL_L_STATUS_20 0x250 | |
| 165 | #define GRL_L_STATUS_21 0x254 | |
| 166 | #define GRL_L_STATUS_22 0x258 | |
| 167 | #define GRL_L_STATUS_23 0x25c | |
| 168 | #define GRL_R_STATUS_0 0x260 | |
| 169 | #define GRL_R_STATUS_1 0x264 | |
| 170 | #define GRL_R_STATUS_2 0x268 | |
| 171 | #define GRL_R_STATUS_3 0x26c | |
| 172 | #define GRL_R_STATUS_4 0x270 | |
| 173 | #define GRL_R_STATUS_5 0x274 | |
| 174 | #define GRL_R_STATUS_6 0x278 | |
| 175 | #define GRL_R_STATUS_7 0x27c | |
| 176 | #define GRL_R_STATUS_8 0x280 | |
| 177 | #define GRL_R_STATUS_9 0x284 | |
| 178 | #define GRL_R_STATUS_10 0x288 | |
| 179 | #define GRL_R_STATUS_11 0x28c | |
| 180 | #define GRL_R_STATUS_12 0x290 | |
| 181 | #define GRL_R_STATUS_13 0x294 | |
| 182 | #define GRL_R_STATUS_14 0x298 | |
| 183 | #define GRL_R_STATUS_15 0x29c | |
| 184 | #define GRL_R_STATUS_16 0x2a0 | |
| 185 | #define GRL_R_STATUS_17 0x2a4 | |
| 186 | #define GRL_R_STATUS_18 0x2a8 | |
| 187 | #define GRL_R_STATUS_19 0x2ac | |
| 188 | #define GRL_R_STATUS_20 0x2b0 | |
| 189 | #define GRL_R_STATUS_21 0x2b4 | |
| 190 | #define GRL_R_STATUS_22 0x2b8 | |
| 191 | #define GRL_R_STATUS_23 0x2bc | |
| 192 | #define GRL_ABIST_CTRL0 0x2D4 | |
| 193 | #define GRL_ABIST_CTRL1 0x2D8 | |
| 194 | #define ABIST_EN BIT(7) | |
| 195 | #define ABIST_DATA_FMT (0x7 << 0) | |
| 196 | #define VIDEO_CFG_0 0x380 | |
| 197 | #define VIDEO_CFG_1 0x384 | |
| 198 | #define VIDEO_CFG_2 0x388 | |
| 199 | #define VIDEO_CFG_3 0x38c | |
| 200 | #define VIDEO_CFG_4 0x390 | |
| 201 | #define VIDEO_SOURCE_SEL BIT(7) | |
| 202 | #define NORMAL_PATH (1 << 7) | |
| 203 | #define GEN_RGB (0 << 7) | |
| 204 | ||
| 205 | #define HDMI_SYS_CFG1C 0x000 | |
| 206 | #define HDMI_ON BIT(0) | |
| 207 | #define HDMI_RST BIT(1) | |
| 208 | #define ANLG_ON BIT(2) | |
| 209 | #define CFG10_DVI BIT(3) | |
| 210 | #define HDMI_TST BIT(3) | |
| 211 | #define SYS_KEYMASK1 (0xff << 8) | |
| 212 | #define SYS_KEYMASK2 (0xff << 16) | |
| 213 | #define AUD_OUTSYNC_EN BIT(24) | |
| 214 | #define AUD_OUTSYNC_PRE_EN BIT(25) | |
| 215 | #define I2CM_ON BIT(26) | |
| 216 | #define E2PROM_TYPE_8BIT BIT(27) | |
| 217 | #define MCM_E2PROM_ON BIT(28) | |
| 218 | #define EXT_E2PROM_ON BIT(29) | |
| 219 | #define HTPLG_PIN_SEL_OFF BIT(30) | |
| 220 | #define AES_EFUSE_ENABLE BIT(31) | |
| 221 | #define HDMI_SYS_CFG20 0x004 | |
| 222 | #define DEEP_COLOR_MODE_MASK (3 << 1) | |
| 223 | #define COLOR_8BIT_MODE (0 << 1) | |
| 224 | #define COLOR_10BIT_MODE (1 << 1) | |
| 225 | #define COLOR_12BIT_MODE (2 << 1) | |
| 226 | #define COLOR_16BIT_MODE (3 << 1) | |
| 227 | #define DEEP_COLOR_EN BIT(0) | |
| 228 | #define HDMI_AUDIO_TEST_SEL BIT(8) | |
| 229 | #define HDMI2P0_EN BIT(11) | |
| 230 | #define HDMI_OUT_FIFO_EN BIT(16) | |
| 231 | #define HDMI_OUT_FIFO_CLK_INV BIT(17) | |
| 232 | #define MHL_MODE_ON BIT(28) | |
| 233 | #define MHL_PP_MODE BIT(29) | |
| 234 | #define MHL_SYNC_AUTO_EN BIT(30) | |
| 235 | #define HDMI_PCLK_FREE_RUN BIT(31) | |
| 236 | ||
| 56ba355d | 237 | #define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 |
| 8f83f268 | 238 | #endif |