Merge git://git.kvack.org/~bcrl/aio-fixes
[deliverable/linux.git] / drivers / gpu / drm / mga / mga_irq.c
CommitLineData
1da177e4 1/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
0a3e67a4
JB
2 */
3/*
1da177e4 4 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
b5e89ed5 5 *
1da177e4
LT
6 * The Weather Channel (TM) funded Tungsten Graphics to develop the
7 * initial release of the Radeon 8500 driver under the XFree86 license.
8 * This notice must be preserved.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the next
18 * paragraph) shall be included in all copies or substantial portions of the
19 * Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
27 * DEALINGS IN THE SOFTWARE.
28 *
29 * Authors:
30 * Keith Whitwell <keith@tungstengraphics.com>
31 * Eric Anholt <anholt@FreeBSD.org>
32 */
33
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/mga_drm.h>
1da177e4
LT
36#include "mga_drv.h"
37
0a3e67a4
JB
38u32 mga_get_vblank_counter(struct drm_device *dev, int crtc)
39{
40 const drm_mga_private_t *const dev_priv =
41 (drm_mga_private_t *) dev->dev_private;
42
43 if (crtc != 0)
44 return 0;
45
46 return atomic_read(&dev_priv->vbl_received);
47}
48
49
e9f0d76f 50irqreturn_t mga_driver_irq_handler(int irq, void *arg)
1da177e4 51{
eddca551 52 struct drm_device *dev = (struct drm_device *) arg;
b5e89ed5 53 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1da177e4 54 int status;
6795c985
DA
55 int handled = 0;
56
57 status = MGA_READ(MGA_STATUS);
1da177e4 58
1da177e4 59 /* VBLANK interrupt */
b5e89ed5
DA
60 if (status & MGA_VLINEPEN) {
61 MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
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JB
62 atomic_inc(&dev_priv->vbl_received);
63 drm_handle_vblank(dev, 0);
6795c985
DA
64 handled = 1;
65 }
66
67 /* SOFTRAP interrupt */
68 if (status & MGA_SOFTRAPEN) {
69 const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
b5e89ed5 70 const u32 prim_end = MGA_READ(MGA_PRIMEND);
6795c985 71
0a3e67a4 72
6795c985
DA
73 MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
74
75 /* In addition to clearing the interrupt-pending bit, we
76 * have to write to MGA_PRIMEND to re-start the DMA operation.
77 */
f2b2cb79 78 if ((prim_start & ~0x03) != (prim_end & ~0x03))
6795c985 79 MGA_WRITE(MGA_PRIMEND, prim_end);
6795c985
DA
80
81 atomic_inc(&dev_priv->last_fence_retired);
57ed0f7b 82 wake_up(&dev_priv->fence_queue);
6795c985
DA
83 handled = 1;
84 }
85
0a3e67a4 86 if (handled)
1da177e4 87 return IRQ_HANDLED;
1da177e4
LT
88 return IRQ_NONE;
89}
90
0a3e67a4 91int mga_enable_vblank(struct drm_device *dev, int crtc)
1da177e4 92{
0a3e67a4 93 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1da177e4 94
0a3e67a4
JB
95 if (crtc != 0) {
96 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
97 crtc);
98 return 0;
99 }
ac741ab7 100
0a3e67a4
JB
101 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
102 return 0;
103}
ac741ab7 104
0a3e67a4
JB
105
106void mga_disable_vblank(struct drm_device *dev, int crtc)
107{
108 if (crtc != 0) {
109 DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
110 crtc);
111 }
112
113 /* Do *NOT* disable the vertical refresh interrupt. MGA doesn't have
114 * a nice hardware counter that tracks the number of refreshes when
115 * the interrupt is disabled, and the kernel doesn't know the refresh
116 * rate to calculate an estimate.
117 */
118 /* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */
1da177e4
LT
119}
120
f2b2cb79 121int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence)
6795c985
DA
122{
123 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
124 unsigned int cur_fence;
125 int ret = 0;
126
127 /* Assume that the user has missed the current sequence number
128 * by about a day rather than she wants to wait for years
129 * using fences.
130 */
bfd8303a 131 DRM_WAIT_ON(ret, dev_priv->fence_queue, 3 * HZ,
6795c985
DA
132 (((cur_fence = atomic_read(&dev_priv->last_fence_retired))
133 - *sequence) <= (1 << 23)));
134
135 *sequence = cur_fence;
136
137 return ret;
138}
139
f2b2cb79 140void mga_driver_irq_preinstall(struct drm_device *dev)
6795c985
DA
141{
142 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1da177e4
LT
143
144 /* Disable *all* interrupts */
b5e89ed5 145 MGA_WRITE(MGA_IEN, 0);
1da177e4 146 /* Clear bits if they're already high */
b5e89ed5 147 MGA_WRITE(MGA_ICLEAR, ~0);
1da177e4
LT
148}
149
0a3e67a4 150int mga_driver_irq_postinstall(struct drm_device *dev)
6795c985
DA
151{
152 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
153
57ed0f7b 154 init_waitqueue_head(&dev_priv->fence_queue);
1da177e4 155
0a3e67a4
JB
156 /* Turn on soft trap interrupt. Vertical blank interrupts are enabled
157 * in mga_enable_vblank.
158 */
159 MGA_WRITE(MGA_IEN, MGA_SOFTRAPEN);
160 return 0;
1da177e4
LT
161}
162
f2b2cb79 163void mga_driver_irq_uninstall(struct drm_device *dev)
b5e89ed5
DA
164{
165 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1da177e4
LT
166 if (!dev_priv)
167 return;
168
169 /* Disable *all* interrupts */
6795c985 170 MGA_WRITE(MGA_IEN, 0);
b5e89ed5 171
4423843c 172 dev->irq_enabled = false;
1da177e4 173}
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