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414c4531 DA |
1 | /* |
2 | * Copyright 2010 Matt Turner. | |
3 | * Copyright 2012 Red Hat | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General | |
6 | * Public License version 2. See the file COPYING in the main | |
7 | * directory of this archive for more details. | |
8 | * | |
9 | * Authors: Matthew Garrett | |
10 | * Matt Turner | |
11 | * Dave Airlie | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | ||
760285e7 DH |
16 | #include <drm/drmP.h> |
17 | #include <drm/drm_crtc_helper.h> | |
3cb9ae4f | 18 | #include <drm/drm_plane_helper.h> |
414c4531 DA |
19 | |
20 | #include "mgag200_drv.h" | |
21 | ||
22 | #define MGAG200_LUT_SIZE 256 | |
23 | ||
24 | /* | |
25 | * This file contains setup code for the CRTC. | |
26 | */ | |
27 | ||
28 | static void mga_crtc_load_lut(struct drm_crtc *crtc) | |
29 | { | |
30 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
31 | struct drm_device *dev = crtc->dev; | |
32 | struct mga_device *mdev = dev->dev_private; | |
f4510a27 | 33 | struct drm_framebuffer *fb = crtc->primary->fb; |
414c4531 DA |
34 | int i; |
35 | ||
36 | if (!crtc->enabled) | |
37 | return; | |
38 | ||
39 | WREG8(DAC_INDEX + MGA1064_INDEX, 0); | |
40 | ||
de7500ea EE |
41 | if (fb && fb->bits_per_pixel == 16) { |
42 | int inc = (fb->depth == 15) ? 8 : 4; | |
43 | u8 r, b; | |
44 | for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { | |
45 | if (fb->depth == 16) { | |
46 | if (i > (MGAG200_LUT_SIZE >> 1)) { | |
47 | r = b = 0; | |
48 | } else { | |
49 | r = mga_crtc->lut_r[i << 1]; | |
50 | b = mga_crtc->lut_b[i << 1]; | |
51 | } | |
52 | } else { | |
53 | r = mga_crtc->lut_r[i]; | |
54 | b = mga_crtc->lut_b[i]; | |
55 | } | |
56 | /* VGA registers */ | |
57 | WREG8(DAC_INDEX + MGA1064_COL_PAL, r); | |
58 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); | |
59 | WREG8(DAC_INDEX + MGA1064_COL_PAL, b); | |
60 | } | |
61 | return; | |
62 | } | |
414c4531 DA |
63 | for (i = 0; i < MGAG200_LUT_SIZE; i++) { |
64 | /* VGA registers */ | |
65 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]); | |
66 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); | |
67 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]); | |
68 | } | |
69 | } | |
70 | ||
71 | static inline void mga_wait_vsync(struct mga_device *mdev) | |
72 | { | |
3cdc0e8d | 73 | unsigned long timeout = jiffies + HZ/10; |
414c4531 DA |
74 | unsigned int status = 0; |
75 | ||
76 | do { | |
77 | status = RREG32(MGAREG_Status); | |
3cdc0e8d CH |
78 | } while ((status & 0x08) && time_before(jiffies, timeout)); |
79 | timeout = jiffies + HZ/10; | |
414c4531 DA |
80 | status = 0; |
81 | do { | |
82 | status = RREG32(MGAREG_Status); | |
3cdc0e8d | 83 | } while (!(status & 0x08) && time_before(jiffies, timeout)); |
414c4531 DA |
84 | } |
85 | ||
86 | static inline void mga_wait_busy(struct mga_device *mdev) | |
87 | { | |
3cdc0e8d | 88 | unsigned long timeout = jiffies + HZ; |
414c4531 DA |
89 | unsigned int status = 0; |
90 | do { | |
91 | status = RREG8(MGAREG_Status + 2); | |
3cdc0e8d | 92 | } while ((status & 0x01) && time_before(jiffies, timeout)); |
414c4531 DA |
93 | } |
94 | ||
e829d7ef ML |
95 | #define P_ARRAY_SIZE 9 |
96 | ||
414c4531 DA |
97 | static int mga_g200se_set_plls(struct mga_device *mdev, long clock) |
98 | { | |
99 | unsigned int vcomax, vcomin, pllreffreq; | |
100 | unsigned int delta, tmpdelta, permitteddelta; | |
101 | unsigned int testp, testm, testn; | |
102 | unsigned int p, m, n; | |
103 | unsigned int computed; | |
e829d7ef ML |
104 | unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1}; |
105 | unsigned int fvv; | |
106 | unsigned int i; | |
414c4531 | 107 | |
e829d7ef | 108 | if (mdev->unique_rev_id <= 0x03) { |
414c4531 | 109 | |
e829d7ef ML |
110 | m = n = p = 0; |
111 | vcomax = 320000; | |
112 | vcomin = 160000; | |
113 | pllreffreq = 25000; | |
414c4531 | 114 | |
e829d7ef ML |
115 | delta = 0xffffffff; |
116 | permitteddelta = clock * 5 / 1000; | |
414c4531 | 117 | |
e829d7ef ML |
118 | for (testp = 8; testp > 0; testp /= 2) { |
119 | if (clock * testp > vcomax) | |
120 | continue; | |
121 | if (clock * testp < vcomin) | |
122 | continue; | |
123 | ||
124 | for (testn = 17; testn < 256; testn++) { | |
125 | for (testm = 1; testm < 32; testm++) { | |
126 | computed = (pllreffreq * testn) / | |
127 | (testm * testp); | |
128 | if (computed > clock) | |
129 | tmpdelta = computed - clock; | |
130 | else | |
131 | tmpdelta = clock - computed; | |
132 | if (tmpdelta < delta) { | |
133 | delta = tmpdelta; | |
134 | m = testm - 1; | |
135 | n = testn - 1; | |
136 | p = testp - 1; | |
137 | } | |
138 | } | |
139 | } | |
140 | } | |
141 | } else { | |
142 | ||
143 | ||
144 | m = n = p = 0; | |
145 | vcomax = 1600000; | |
146 | vcomin = 800000; | |
147 | pllreffreq = 25000; | |
148 | ||
149 | if (clock < 25000) | |
150 | clock = 25000; | |
151 | ||
152 | clock = clock * 2; | |
153 | ||
154 | delta = 0xFFFFFFFF; | |
155 | /* Permited delta is 0.5% as VESA Specification */ | |
156 | permitteddelta = clock * 5 / 1000; | |
157 | ||
158 | for (i = 0 ; i < P_ARRAY_SIZE ; i++) { | |
159 | testp = pvalues_e4[i]; | |
160 | ||
161 | if ((clock * testp) > vcomax) | |
162 | continue; | |
163 | if ((clock * testp) < vcomin) | |
164 | continue; | |
165 | ||
166 | for (testn = 50; testn <= 256; testn++) { | |
167 | for (testm = 1; testm <= 32; testm++) { | |
168 | computed = (pllreffreq * testn) / | |
169 | (testm * testp); | |
170 | if (computed > clock) | |
171 | tmpdelta = computed - clock; | |
172 | else | |
173 | tmpdelta = clock - computed; | |
174 | ||
175 | if (tmpdelta < delta) { | |
176 | delta = tmpdelta; | |
177 | m = testm - 1; | |
178 | n = testn - 1; | |
179 | p = testp - 1; | |
180 | } | |
414c4531 DA |
181 | } |
182 | } | |
183 | } | |
e829d7ef | 184 | |
d3922b69 | 185 | fvv = pllreffreq * (n + 1) / (m + 1); |
e829d7ef ML |
186 | fvv = (fvv - 800000) / 50000; |
187 | ||
188 | if (fvv > 15) | |
189 | fvv = 15; | |
190 | ||
191 | p |= (fvv << 4); | |
192 | m |= 0x80; | |
193 | ||
194 | clock = clock / 2; | |
414c4531 DA |
195 | } |
196 | ||
197 | if (delta > permitteddelta) { | |
198 | printk(KERN_WARNING "PLL delta too large\n"); | |
199 | return 1; | |
200 | } | |
201 | ||
202 | WREG_DAC(MGA1064_PIX_PLLC_M, m); | |
203 | WREG_DAC(MGA1064_PIX_PLLC_N, n); | |
204 | WREG_DAC(MGA1064_PIX_PLLC_P, p); | |
d3922b69 ML |
205 | |
206 | if (mdev->unique_rev_id >= 0x04) { | |
207 | WREG_DAC(0x1a, 0x09); | |
208 | msleep(20); | |
209 | WREG_DAC(0x1a, 0x01); | |
210 | ||
211 | } | |
212 | ||
414c4531 DA |
213 | return 0; |
214 | } | |
215 | ||
216 | static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) | |
217 | { | |
218 | unsigned int vcomax, vcomin, pllreffreq; | |
546aee51 | 219 | unsigned int delta, tmpdelta; |
6d857c18 | 220 | unsigned int testp, testm, testn, testp2; |
414c4531 DA |
221 | unsigned int p, m, n; |
222 | unsigned int computed; | |
223 | int i, j, tmpcount, vcount; | |
224 | bool pll_locked = false; | |
225 | u8 tmp; | |
226 | ||
227 | m = n = p = 0; | |
414c4531 DA |
228 | |
229 | delta = 0xffffffff; | |
414c4531 | 230 | |
6d857c18 ML |
231 | if (mdev->type == G200_EW3) { |
232 | ||
233 | vcomax = 800000; | |
234 | vcomin = 400000; | |
235 | pllreffreq = 25000; | |
236 | ||
237 | for (testp = 1; testp < 8; testp++) { | |
238 | for (testp2 = 1; testp2 < 8; testp2++) { | |
239 | if (testp < testp2) | |
240 | continue; | |
241 | if ((clock * testp * testp2) > vcomax) | |
242 | continue; | |
243 | if ((clock * testp * testp2) < vcomin) | |
244 | continue; | |
245 | for (testm = 1; testm < 26; testm++) { | |
246 | for (testn = 32; testn < 2048 ; testn++) { | |
247 | computed = (pllreffreq * testn) / | |
248 | (testm * testp * testp2); | |
249 | if (computed > clock) | |
250 | tmpdelta = computed - clock; | |
251 | else | |
252 | tmpdelta = clock - computed; | |
253 | if (tmpdelta < delta) { | |
254 | delta = tmpdelta; | |
255 | m = ((testn & 0x100) >> 1) | | |
256 | (testm); | |
257 | n = (testn & 0xFF); | |
258 | p = ((testn & 0x600) >> 3) | | |
259 | (testp2 << 3) | | |
260 | (testp); | |
261 | } | |
262 | } | |
263 | } | |
264 | } | |
265 | } | |
266 | } else { | |
414c4531 | 267 | |
6d857c18 ML |
268 | vcomax = 550000; |
269 | vcomin = 150000; | |
270 | pllreffreq = 48000; | |
271 | ||
272 | for (testp = 1; testp < 9; testp++) { | |
273 | if (clock * testp > vcomax) | |
274 | continue; | |
275 | if (clock * testp < vcomin) | |
276 | continue; | |
277 | ||
278 | for (testm = 1; testm < 17; testm++) { | |
279 | for (testn = 1; testn < 151; testn++) { | |
280 | computed = (pllreffreq * testn) / | |
281 | (testm * testp); | |
282 | if (computed > clock) | |
283 | tmpdelta = computed - clock; | |
284 | else | |
285 | tmpdelta = clock - computed; | |
286 | if (tmpdelta < delta) { | |
287 | delta = tmpdelta; | |
288 | n = testn - 1; | |
289 | m = (testm - 1) | | |
290 | ((n >> 1) & 0x80); | |
291 | p = testp - 1; | |
292 | } | |
414c4531 DA |
293 | } |
294 | } | |
295 | } | |
296 | } | |
297 | ||
298 | for (i = 0; i <= 32 && pll_locked == false; i++) { | |
299 | if (i > 0) { | |
300 | WREG8(MGAREG_CRTC_INDEX, 0x1e); | |
301 | tmp = RREG8(MGAREG_CRTC_DATA); | |
302 | if (tmp < 0xff) | |
303 | WREG8(MGAREG_CRTC_DATA, tmp+1); | |
304 | } | |
305 | ||
306 | /* set pixclkdis to 1 */ | |
307 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
308 | tmp = RREG8(DAC_DATA); | |
309 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 310 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
311 | |
312 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
313 | tmp = RREG8(DAC_DATA); | |
314 | tmp |= MGA1064_REMHEADCTL_CLKDIS; | |
fb70a669 | 315 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
316 | |
317 | /* select PLL Set C */ | |
318 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
319 | tmp |= 0x3 << 2; | |
320 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
321 | ||
322 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
323 | tmp = RREG8(DAC_DATA); | |
324 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; | |
fb70a669 | 325 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
326 | |
327 | udelay(500); | |
328 | ||
329 | /* reset the PLL */ | |
330 | WREG8(DAC_INDEX, MGA1064_VREF_CTL); | |
331 | tmp = RREG8(DAC_DATA); | |
332 | tmp &= ~0x04; | |
fb70a669 | 333 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
334 | |
335 | udelay(50); | |
336 | ||
337 | /* program pixel pll register */ | |
338 | WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); | |
339 | WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); | |
340 | WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); | |
341 | ||
342 | udelay(50); | |
343 | ||
344 | /* turn pll on */ | |
345 | WREG8(DAC_INDEX, MGA1064_VREF_CTL); | |
346 | tmp = RREG8(DAC_DATA); | |
347 | tmp |= 0x04; | |
348 | WREG_DAC(MGA1064_VREF_CTL, tmp); | |
349 | ||
350 | udelay(500); | |
351 | ||
352 | /* select the pixel pll */ | |
353 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
354 | tmp = RREG8(DAC_DATA); | |
355 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
356 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 357 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
358 | |
359 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
360 | tmp = RREG8(DAC_DATA); | |
361 | tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; | |
362 | tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; | |
fb70a669 | 363 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
364 | |
365 | /* reset dotclock rate bit */ | |
366 | WREG8(MGAREG_SEQ_INDEX, 1); | |
367 | tmp = RREG8(MGAREG_SEQ_DATA); | |
368 | tmp &= ~0x8; | |
369 | WREG8(MGAREG_SEQ_DATA, tmp); | |
370 | ||
371 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
372 | tmp = RREG8(DAC_DATA); | |
373 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 374 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
375 | |
376 | vcount = RREG8(MGAREG_VCOUNT); | |
377 | ||
378 | for (j = 0; j < 30 && pll_locked == false; j++) { | |
379 | tmpcount = RREG8(MGAREG_VCOUNT); | |
380 | if (tmpcount < vcount) | |
381 | vcount = 0; | |
382 | if ((tmpcount - vcount) > 2) | |
383 | pll_locked = true; | |
384 | else | |
385 | udelay(5); | |
386 | } | |
387 | } | |
388 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
389 | tmp = RREG8(DAC_DATA); | |
390 | tmp &= ~MGA1064_REMHEADCTL_CLKDIS; | |
391 | WREG_DAC(MGA1064_REMHEADCTL, tmp); | |
392 | return 0; | |
393 | } | |
394 | ||
395 | static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) | |
396 | { | |
397 | unsigned int vcomax, vcomin, pllreffreq; | |
546aee51 | 398 | unsigned int delta, tmpdelta; |
414c4531 DA |
399 | unsigned int testp, testm, testn; |
400 | unsigned int p, m, n; | |
401 | unsigned int computed; | |
402 | u8 tmp; | |
403 | ||
404 | m = n = p = 0; | |
405 | vcomax = 550000; | |
406 | vcomin = 150000; | |
407 | pllreffreq = 50000; | |
408 | ||
409 | delta = 0xffffffff; | |
414c4531 DA |
410 | |
411 | for (testp = 16; testp > 0; testp--) { | |
412 | if (clock * testp > vcomax) | |
413 | continue; | |
414 | if (clock * testp < vcomin) | |
415 | continue; | |
416 | ||
417 | for (testn = 1; testn < 257; testn++) { | |
418 | for (testm = 1; testm < 17; testm++) { | |
419 | computed = (pllreffreq * testn) / | |
420 | (testm * testp); | |
421 | if (computed > clock) | |
422 | tmpdelta = computed - clock; | |
423 | else | |
424 | tmpdelta = clock - computed; | |
425 | if (tmpdelta < delta) { | |
426 | delta = tmpdelta; | |
427 | n = testn - 1; | |
428 | m = testm - 1; | |
429 | p = testp - 1; | |
430 | } | |
431 | } | |
432 | } | |
433 | } | |
434 | ||
435 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
436 | tmp = RREG8(DAC_DATA); | |
437 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 438 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
439 | |
440 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
441 | tmp |= 0x3 << 2; | |
442 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
443 | ||
444 | WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); | |
445 | tmp = RREG8(DAC_DATA); | |
fb70a669 | 446 | WREG8(DAC_DATA, tmp & ~0x40); |
414c4531 DA |
447 | |
448 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
449 | tmp = RREG8(DAC_DATA); | |
450 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 451 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
452 | |
453 | WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); | |
454 | WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); | |
455 | WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); | |
456 | ||
457 | udelay(50); | |
458 | ||
459 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
460 | tmp = RREG8(DAC_DATA); | |
461 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 462 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
463 | |
464 | udelay(500); | |
465 | ||
466 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
467 | tmp = RREG8(DAC_DATA); | |
468 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
469 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 470 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
471 | |
472 | WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); | |
473 | tmp = RREG8(DAC_DATA); | |
fb70a669 | 474 | WREG8(DAC_DATA, tmp | 0x40); |
414c4531 DA |
475 | |
476 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
477 | tmp |= (0x3 << 2); | |
478 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
479 | ||
480 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
481 | tmp = RREG8(DAC_DATA); | |
482 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 483 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
484 | |
485 | return 0; | |
486 | } | |
487 | ||
488 | static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) | |
489 | { | |
490 | unsigned int vcomax, vcomin, pllreffreq; | |
546aee51 | 491 | unsigned int delta, tmpdelta; |
414c4531 DA |
492 | unsigned int testp, testm, testn; |
493 | unsigned int p, m, n; | |
494 | unsigned int computed; | |
495 | int i, j, tmpcount, vcount; | |
496 | u8 tmp; | |
497 | bool pll_locked = false; | |
498 | ||
499 | m = n = p = 0; | |
500 | vcomax = 800000; | |
501 | vcomin = 400000; | |
260b3f12 | 502 | pllreffreq = 33333; |
414c4531 DA |
503 | |
504 | delta = 0xffffffff; | |
414c4531 | 505 | |
260b3f12 | 506 | for (testp = 16; testp > 0; testp >>= 1) { |
414c4531 DA |
507 | if (clock * testp > vcomax) |
508 | continue; | |
509 | if (clock * testp < vcomin) | |
510 | continue; | |
511 | ||
512 | for (testm = 1; testm < 33; testm++) { | |
260b3f12 | 513 | for (testn = 17; testn < 257; testn++) { |
414c4531 DA |
514 | computed = (pllreffreq * testn) / |
515 | (testm * testp); | |
516 | if (computed > clock) | |
517 | tmpdelta = computed - clock; | |
518 | else | |
519 | tmpdelta = clock - computed; | |
520 | if (tmpdelta < delta) { | |
521 | delta = tmpdelta; | |
522 | n = testn - 1; | |
260b3f12 | 523 | m = (testm - 1); |
414c4531 DA |
524 | p = testp - 1; |
525 | } | |
526 | if ((clock * testp) >= 600000) | |
260b3f12 | 527 | p |= 0x80; |
414c4531 DA |
528 | } |
529 | } | |
530 | } | |
531 | for (i = 0; i <= 32 && pll_locked == false; i++) { | |
532 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
533 | tmp = RREG8(DAC_DATA); | |
534 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 535 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
536 | |
537 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
538 | tmp |= 0x3 << 2; | |
539 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
540 | ||
541 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
542 | tmp = RREG8(DAC_DATA); | |
543 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 544 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
545 | |
546 | udelay(500); | |
547 | ||
548 | WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); | |
549 | WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); | |
550 | WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); | |
551 | ||
552 | udelay(500); | |
553 | ||
554 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
555 | tmp = RREG8(DAC_DATA); | |
556 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
557 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 558 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
559 | |
560 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
561 | tmp = RREG8(DAC_DATA); | |
562 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
563 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 564 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
565 | |
566 | vcount = RREG8(MGAREG_VCOUNT); | |
567 | ||
568 | for (j = 0; j < 30 && pll_locked == false; j++) { | |
569 | tmpcount = RREG8(MGAREG_VCOUNT); | |
570 | if (tmpcount < vcount) | |
571 | vcount = 0; | |
572 | if ((tmpcount - vcount) > 2) | |
573 | pll_locked = true; | |
574 | else | |
575 | udelay(5); | |
576 | } | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | static int mga_g200er_set_plls(struct mga_device *mdev, long clock) | |
583 | { | |
584 | unsigned int vcomax, vcomin, pllreffreq; | |
585 | unsigned int delta, tmpdelta; | |
9830605d | 586 | int testr, testn, testm, testo; |
414c4531 | 587 | unsigned int p, m, n; |
9830605d | 588 | unsigned int computed, vco; |
414c4531 | 589 | int tmp; |
9830605d | 590 | const unsigned int m_div_val[] = { 1, 2, 4, 8 }; |
414c4531 DA |
591 | |
592 | m = n = p = 0; | |
593 | vcomax = 1488000; | |
594 | vcomin = 1056000; | |
595 | pllreffreq = 48000; | |
596 | ||
597 | delta = 0xffffffff; | |
598 | ||
599 | for (testr = 0; testr < 4; testr++) { | |
600 | if (delta == 0) | |
601 | break; | |
602 | for (testn = 5; testn < 129; testn++) { | |
603 | if (delta == 0) | |
604 | break; | |
605 | for (testm = 3; testm >= 0; testm--) { | |
606 | if (delta == 0) | |
607 | break; | |
608 | for (testo = 5; testo < 33; testo++) { | |
9830605d | 609 | vco = pllreffreq * (testn + 1) / |
414c4531 | 610 | (testr + 1); |
9830605d | 611 | if (vco < vcomin) |
414c4531 | 612 | continue; |
9830605d | 613 | if (vco > vcomax) |
414c4531 | 614 | continue; |
9830605d | 615 | computed = vco / (m_div_val[testm] * (testo + 1)); |
414c4531 DA |
616 | if (computed > clock) |
617 | tmpdelta = computed - clock; | |
618 | else | |
619 | tmpdelta = clock - computed; | |
620 | if (tmpdelta < delta) { | |
621 | delta = tmpdelta; | |
622 | m = testm | (testo << 3); | |
623 | n = testn; | |
624 | p = testr | (testr << 3); | |
625 | } | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | ||
631 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
632 | tmp = RREG8(DAC_DATA); | |
633 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 634 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
635 | |
636 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
637 | tmp = RREG8(DAC_DATA); | |
638 | tmp |= MGA1064_REMHEADCTL_CLKDIS; | |
fb70a669 | 639 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
640 | |
641 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
642 | tmp |= (0x3<<2) | 0xc0; | |
643 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
644 | ||
645 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
646 | tmp = RREG8(DAC_DATA); | |
647 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
648 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 649 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
650 | |
651 | udelay(500); | |
652 | ||
653 | WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); | |
654 | WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); | |
655 | WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); | |
656 | ||
657 | udelay(50); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static int mga_crtc_set_plls(struct mga_device *mdev, long clock) | |
663 | { | |
664 | switch(mdev->type) { | |
665 | case G200_SE_A: | |
666 | case G200_SE_B: | |
667 | return mga_g200se_set_plls(mdev, clock); | |
668 | break; | |
669 | case G200_WB: | |
6d857c18 | 670 | case G200_EW3: |
414c4531 DA |
671 | return mga_g200wb_set_plls(mdev, clock); |
672 | break; | |
673 | case G200_EV: | |
674 | return mga_g200ev_set_plls(mdev, clock); | |
675 | break; | |
676 | case G200_EH: | |
677 | return mga_g200eh_set_plls(mdev, clock); | |
678 | break; | |
679 | case G200_ER: | |
680 | return mga_g200er_set_plls(mdev, clock); | |
681 | break; | |
682 | } | |
683 | return 0; | |
684 | } | |
685 | ||
686 | static void mga_g200wb_prepare(struct drm_crtc *crtc) | |
687 | { | |
688 | struct mga_device *mdev = crtc->dev->dev_private; | |
689 | u8 tmp; | |
690 | int iter_max; | |
691 | ||
692 | /* 1- The first step is to warn the BMC of an upcoming mode change. | |
693 | * We are putting the misc<0> to output.*/ | |
694 | ||
695 | WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); | |
696 | tmp = RREG8(DAC_DATA); | |
697 | tmp |= 0x10; | |
698 | WREG_DAC(MGA1064_GEN_IO_CTL, tmp); | |
699 | ||
700 | /* we are putting a 1 on the misc<0> line */ | |
701 | WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); | |
702 | tmp = RREG8(DAC_DATA); | |
703 | tmp |= 0x10; | |
704 | WREG_DAC(MGA1064_GEN_IO_DATA, tmp); | |
705 | ||
706 | /* 2- Second step to mask and further scan request | |
707 | * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) | |
708 | */ | |
709 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
710 | tmp = RREG8(DAC_DATA); | |
711 | tmp |= 0x80; | |
712 | WREG_DAC(MGA1064_SPAREREG, tmp); | |
713 | ||
714 | /* 3a- the third step is to verifu if there is an active scan | |
715 | * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) | |
716 | */ | |
717 | iter_max = 300; | |
718 | while (!(tmp & 0x1) && iter_max) { | |
719 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
720 | tmp = RREG8(DAC_DATA); | |
721 | udelay(1000); | |
722 | iter_max--; | |
723 | } | |
724 | ||
725 | /* 3b- this step occurs only if the remove is actually scanning | |
726 | * we are waiting for the end of the frame which is a 1 on | |
727 | * remvsyncsts (XSPAREREG<1>) | |
728 | */ | |
729 | if (iter_max) { | |
730 | iter_max = 300; | |
731 | while ((tmp & 0x2) && iter_max) { | |
732 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
733 | tmp = RREG8(DAC_DATA); | |
734 | udelay(1000); | |
735 | iter_max--; | |
736 | } | |
737 | } | |
738 | } | |
739 | ||
740 | static void mga_g200wb_commit(struct drm_crtc *crtc) | |
741 | { | |
742 | u8 tmp; | |
743 | struct mga_device *mdev = crtc->dev->dev_private; | |
744 | ||
745 | /* 1- The first step is to ensure that the vrsten and hrsten are set */ | |
746 | WREG8(MGAREG_CRTCEXT_INDEX, 1); | |
747 | tmp = RREG8(MGAREG_CRTCEXT_DATA); | |
748 | WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); | |
749 | ||
750 | /* 2- second step is to assert the rstlvl2 */ | |
751 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); | |
752 | tmp = RREG8(DAC_DATA); | |
753 | tmp |= 0x8; | |
754 | WREG8(DAC_DATA, tmp); | |
755 | ||
756 | /* wait 10 us */ | |
757 | udelay(10); | |
758 | ||
759 | /* 3- deassert rstlvl2 */ | |
760 | tmp &= ~0x08; | |
761 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); | |
762 | WREG8(DAC_DATA, tmp); | |
763 | ||
764 | /* 4- remove mask of scan request */ | |
765 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
766 | tmp = RREG8(DAC_DATA); | |
767 | tmp &= ~0x80; | |
768 | WREG8(DAC_DATA, tmp); | |
769 | ||
770 | /* 5- put back a 0 on the misc<0> line */ | |
771 | WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); | |
772 | tmp = RREG8(DAC_DATA); | |
773 | tmp &= ~0x10; | |
774 | WREG_DAC(MGA1064_GEN_IO_DATA, tmp); | |
775 | } | |
776 | ||
9f1d0366 CH |
777 | /* |
778 | This is how the framebuffer base address is stored in g200 cards: | |
779 | * Assume @offset is the gpu_addr variable of the framebuffer object | |
780 | * Then addr is the number of _pixels_ (not bytes) from the start of | |
781 | VRAM to the first pixel we want to display. (divided by 2 for 32bit | |
782 | framebuffers) | |
783 | * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers | |
784 | addr<20> -> CRTCEXT0<6> | |
785 | addr<19-16> -> CRTCEXT0<3-0> | |
786 | addr<15-8> -> CRTCC<7-0> | |
787 | addr<7-0> -> CRTCD<7-0> | |
788 | CRTCEXT0 has to be programmed last to trigger an update and make the | |
789 | new addr variable take effect. | |
790 | */ | |
080fd6b5 | 791 | static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) |
414c4531 DA |
792 | { |
793 | struct mga_device *mdev = crtc->dev->dev_private; | |
794 | u32 addr; | |
795 | int count; | |
9f1d0366 | 796 | u8 crtcext0; |
414c4531 DA |
797 | |
798 | while (RREG8(0x1fda) & 0x08); | |
799 | while (!(RREG8(0x1fda) & 0x08)); | |
800 | ||
801 | count = RREG8(MGAREG_VCOUNT) + 2; | |
802 | while (RREG8(MGAREG_VCOUNT) < count); | |
803 | ||
9f1d0366 CH |
804 | WREG8(MGAREG_CRTCEXT_INDEX, 0); |
805 | crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); | |
806 | crtcext0 &= 0xB0; | |
807 | addr = offset / 8; | |
808 | /* Can't store addresses any higher than that... | |
809 | but we also don't have more than 16MB of memory, so it should be fine. */ | |
810 | WARN_ON(addr > 0x1fffff); | |
811 | crtcext0 |= (!!(addr & (1<<20)))<<6; | |
414c4531 DA |
812 | WREG_CRT(0x0d, (u8)(addr & 0xff)); |
813 | WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); | |
9f1d0366 | 814 | WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); |
414c4531 DA |
815 | } |
816 | ||
817 | ||
818 | /* ast is different - we will force move buffers out of VRAM */ | |
819 | static int mga_crtc_do_set_base(struct drm_crtc *crtc, | |
820 | struct drm_framebuffer *fb, | |
821 | int x, int y, int atomic) | |
822 | { | |
823 | struct mga_device *mdev = crtc->dev->dev_private; | |
824 | struct drm_gem_object *obj; | |
825 | struct mga_framebuffer *mga_fb; | |
826 | struct mgag200_bo *bo; | |
827 | int ret; | |
828 | u64 gpu_addr; | |
829 | ||
830 | /* push the previous fb to system ram */ | |
831 | if (!atomic && fb) { | |
832 | mga_fb = to_mga_framebuffer(fb); | |
833 | obj = mga_fb->obj; | |
834 | bo = gem_to_mga_bo(obj); | |
835 | ret = mgag200_bo_reserve(bo, false); | |
836 | if (ret) | |
837 | return ret; | |
838 | mgag200_bo_push_sysram(bo); | |
839 | mgag200_bo_unreserve(bo); | |
840 | } | |
841 | ||
f4510a27 | 842 | mga_fb = to_mga_framebuffer(crtc->primary->fb); |
414c4531 DA |
843 | obj = mga_fb->obj; |
844 | bo = gem_to_mga_bo(obj); | |
845 | ||
846 | ret = mgag200_bo_reserve(bo, false); | |
847 | if (ret) | |
848 | return ret; | |
849 | ||
850 | ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); | |
851 | if (ret) { | |
852 | mgag200_bo_unreserve(bo); | |
853 | return ret; | |
854 | } | |
855 | ||
856 | if (&mdev->mfbdev->mfb == mga_fb) { | |
857 | /* if pushing console in kmap it */ | |
858 | ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); | |
859 | if (ret) | |
860 | DRM_ERROR("failed to kmap fbcon\n"); | |
861 | ||
862 | } | |
863 | mgag200_bo_unreserve(bo); | |
864 | ||
414c4531 DA |
865 | mga_set_start_address(crtc, (u32)gpu_addr); |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
871 | struct drm_framebuffer *old_fb) | |
872 | { | |
873 | return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
874 | } | |
875 | ||
876 | static int mga_crtc_mode_set(struct drm_crtc *crtc, | |
877 | struct drm_display_mode *mode, | |
878 | struct drm_display_mode *adjusted_mode, | |
879 | int x, int y, struct drm_framebuffer *old_fb) | |
880 | { | |
881 | struct drm_device *dev = crtc->dev; | |
882 | struct mga_device *mdev = dev->dev_private; | |
883 | int hdisplay, hsyncstart, hsyncend, htotal; | |
884 | int vdisplay, vsyncstart, vsyncend, vtotal; | |
885 | int pitch; | |
886 | int option = 0, option2 = 0; | |
887 | int i; | |
888 | unsigned char misc = 0; | |
889 | unsigned char ext_vga[6]; | |
414c4531 DA |
890 | u8 bppshift; |
891 | ||
892 | static unsigned char dacvalue[] = { | |
893 | /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, | |
894 | /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
895 | /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
896 | /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, | |
897 | /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
898 | /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, | |
899 | /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, | |
900 | /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, | |
901 | /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
902 | /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 | |
903 | }; | |
904 | ||
f4510a27 | 905 | bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1]; |
414c4531 DA |
906 | |
907 | switch (mdev->type) { | |
908 | case G200_SE_A: | |
909 | case G200_SE_B: | |
910 | dacvalue[MGA1064_VREF_CTL] = 0x03; | |
911 | dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; | |
912 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | | |
913 | MGA1064_MISC_CTL_VGA8 | | |
914 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
915 | if (mdev->has_sdram) | |
916 | option = 0x40049120; | |
917 | else | |
918 | option = 0x4004d120; | |
919 | option2 = 0x00008000; | |
920 | break; | |
921 | case G200_WB: | |
6d857c18 | 922 | case G200_EW3: |
414c4531 DA |
923 | dacvalue[MGA1064_VREF_CTL] = 0x07; |
924 | option = 0x41049120; | |
925 | option2 = 0x0000b000; | |
926 | break; | |
927 | case G200_EV: | |
928 | dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; | |
929 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | | |
930 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
931 | option = 0x00000120; | |
932 | option2 = 0x0000b000; | |
933 | break; | |
934 | case G200_EH: | |
935 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | | |
936 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
937 | option = 0x00000120; | |
938 | option2 = 0x0000b000; | |
939 | break; | |
940 | case G200_ER: | |
414c4531 DA |
941 | break; |
942 | } | |
943 | ||
f4510a27 | 944 | switch (crtc->primary->fb->bits_per_pixel) { |
414c4531 DA |
945 | case 8: |
946 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; | |
947 | break; | |
948 | case 16: | |
f4510a27 | 949 | if (crtc->primary->fb->depth == 15) |
414c4531 DA |
950 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; |
951 | else | |
952 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; | |
953 | break; | |
954 | case 24: | |
955 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; | |
956 | break; | |
957 | case 32: | |
958 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; | |
959 | break; | |
960 | } | |
961 | ||
962 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
963 | misc |= 0x40; | |
964 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
965 | misc |= 0x80; | |
966 | ||
967 | ||
968 | for (i = 0; i < sizeof(dacvalue); i++) { | |
9d8aa55f | 969 | if ((i <= 0x17) || |
414c4531 DA |
970 | (i == 0x1b) || |
971 | (i == 0x1c) || | |
972 | ((i >= 0x1f) && (i <= 0x29)) || | |
973 | ((i >= 0x30) && (i <= 0x37))) | |
974 | continue; | |
975 | if (IS_G200_SE(mdev) && | |
976 | ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) | |
977 | continue; | |
6d857c18 ML |
978 | if ((mdev->type == G200_EV || |
979 | mdev->type == G200_WB || | |
980 | mdev->type == G200_EH || | |
981 | mdev->type == G200_EW3) && | |
414c4531 DA |
982 | (i >= 0x44) && (i <= 0x4e)) |
983 | continue; | |
984 | ||
985 | WREG_DAC(i, dacvalue[i]); | |
986 | } | |
987 | ||
1812a3db CH |
988 | if (mdev->type == G200_ER) |
989 | WREG_DAC(0x90, 0); | |
414c4531 DA |
990 | |
991 | if (option) | |
992 | pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); | |
993 | if (option2) | |
994 | pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); | |
995 | ||
996 | WREG_SEQ(2, 0xf); | |
997 | WREG_SEQ(3, 0); | |
998 | WREG_SEQ(4, 0xe); | |
999 | ||
f4510a27 MR |
1000 | pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8); |
1001 | if (crtc->primary->fb->bits_per_pixel == 24) | |
da558398 | 1002 | pitch = (pitch * 3) >> (4 - bppshift); |
414c4531 DA |
1003 | else |
1004 | pitch = pitch >> (4 - bppshift); | |
1005 | ||
1006 | hdisplay = mode->hdisplay / 8 - 1; | |
1007 | hsyncstart = mode->hsync_start / 8 - 1; | |
1008 | hsyncend = mode->hsync_end / 8 - 1; | |
1009 | htotal = mode->htotal / 8 - 1; | |
1010 | ||
1011 | /* Work around hardware quirk */ | |
1012 | if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) | |
1013 | htotal++; | |
1014 | ||
1015 | vdisplay = mode->vdisplay - 1; | |
1016 | vsyncstart = mode->vsync_start - 1; | |
1017 | vsyncend = mode->vsync_end - 1; | |
1018 | vtotal = mode->vtotal - 2; | |
1019 | ||
1020 | WREG_GFX(0, 0); | |
1021 | WREG_GFX(1, 0); | |
1022 | WREG_GFX(2, 0); | |
1023 | WREG_GFX(3, 0); | |
1024 | WREG_GFX(4, 0); | |
1025 | WREG_GFX(5, 0x40); | |
1026 | WREG_GFX(6, 0x5); | |
1027 | WREG_GFX(7, 0xf); | |
1028 | WREG_GFX(8, 0xf); | |
1029 | ||
1030 | WREG_CRT(0, htotal - 4); | |
1031 | WREG_CRT(1, hdisplay); | |
1032 | WREG_CRT(2, hdisplay); | |
1033 | WREG_CRT(3, (htotal & 0x1F) | 0x80); | |
1034 | WREG_CRT(4, hsyncstart); | |
1035 | WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); | |
1036 | WREG_CRT(6, vtotal & 0xFF); | |
1037 | WREG_CRT(7, ((vtotal & 0x100) >> 8) | | |
1038 | ((vdisplay & 0x100) >> 7) | | |
1039 | ((vsyncstart & 0x100) >> 6) | | |
1040 | ((vdisplay & 0x100) >> 5) | | |
1041 | ((vdisplay & 0x100) >> 4) | /* linecomp */ | |
1042 | ((vtotal & 0x200) >> 4)| | |
1043 | ((vdisplay & 0x200) >> 3) | | |
1044 | ((vsyncstart & 0x200) >> 2)); | |
1045 | WREG_CRT(9, ((vdisplay & 0x200) >> 4) | | |
1046 | ((vdisplay & 0x200) >> 3)); | |
1047 | WREG_CRT(10, 0); | |
1048 | WREG_CRT(11, 0); | |
1049 | WREG_CRT(12, 0); | |
1050 | WREG_CRT(13, 0); | |
1051 | WREG_CRT(14, 0); | |
1052 | WREG_CRT(15, 0); | |
1053 | WREG_CRT(16, vsyncstart & 0xFF); | |
1054 | WREG_CRT(17, (vsyncend & 0x0F) | 0x20); | |
1055 | WREG_CRT(18, vdisplay & 0xFF); | |
1056 | WREG_CRT(19, pitch & 0xFF); | |
1057 | WREG_CRT(20, 0); | |
1058 | WREG_CRT(21, vdisplay & 0xFF); | |
1059 | WREG_CRT(22, (vtotal + 1) & 0xFF); | |
1060 | WREG_CRT(23, 0xc3); | |
1061 | WREG_CRT(24, vdisplay & 0xFF); | |
1062 | ||
1063 | ext_vga[0] = 0; | |
1064 | ext_vga[5] = 0; | |
1065 | ||
1066 | /* TODO interlace */ | |
1067 | ||
1068 | ext_vga[0] |= (pitch & 0x300) >> 4; | |
1069 | ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | | |
1070 | ((hdisplay & 0x100) >> 7) | | |
1071 | ((hsyncstart & 0x100) >> 6) | | |
1072 | (htotal & 0x40); | |
1073 | ext_vga[2] = ((vtotal & 0xc00) >> 10) | | |
1074 | ((vdisplay & 0x400) >> 8) | | |
1075 | ((vdisplay & 0xc00) >> 7) | | |
1076 | ((vsyncstart & 0xc00) >> 5) | | |
1077 | ((vdisplay & 0x400) >> 3); | |
f4510a27 | 1078 | if (crtc->primary->fb->bits_per_pixel == 24) |
414c4531 DA |
1079 | ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; |
1080 | else | |
1081 | ext_vga[3] = ((1 << bppshift) - 1) | 0x80; | |
1082 | ext_vga[4] = 0; | |
6d857c18 | 1083 | if (mdev->type == G200_WB || mdev->type == G200_EW3) |
414c4531 DA |
1084 | ext_vga[1] |= 0x88; |
1085 | ||
414c4531 DA |
1086 | /* Set pixel clocks */ |
1087 | misc = 0x2d; | |
1088 | WREG8(MGA_MISC_OUT, misc); | |
1089 | ||
1090 | mga_crtc_set_plls(mdev, mode->clock); | |
1091 | ||
1092 | for (i = 0; i < 6; i++) { | |
1093 | WREG_ECRT(i, ext_vga[i]); | |
1094 | } | |
1095 | ||
1096 | if (mdev->type == G200_ER) | |
1812a3db | 1097 | WREG_ECRT(0x24, 0x5); |
414c4531 | 1098 | |
6d857c18 ML |
1099 | if (mdev->type == G200_EW3) |
1100 | WREG_ECRT(0x34, 0x5); | |
1101 | ||
414c4531 DA |
1102 | if (mdev->type == G200_EV) { |
1103 | WREG_ECRT(6, 0); | |
1104 | } | |
1105 | ||
1106 | WREG_ECRT(0, ext_vga[0]); | |
1107 | /* Enable mga pixel clock */ | |
1108 | misc = 0x2d; | |
1109 | ||
1110 | WREG8(MGA_MISC_OUT, misc); | |
1111 | ||
1112 | if (adjusted_mode) | |
1113 | memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); | |
1114 | ||
1115 | mga_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1116 | ||
1117 | /* reset tagfifo */ | |
1118 | if (mdev->type == G200_ER) { | |
1119 | u32 mem_ctl = RREG32(MGAREG_MEMCTL); | |
1120 | u8 seq1; | |
1121 | ||
1122 | /* screen off */ | |
1123 | WREG8(MGAREG_SEQ_INDEX, 0x01); | |
1124 | seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; | |
1125 | WREG8(MGAREG_SEQ_DATA, seq1); | |
1126 | ||
1127 | WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); | |
1128 | udelay(1000); | |
1129 | WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); | |
1130 | ||
1131 | WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); | |
1132 | } | |
1133 | ||
1134 | ||
1135 | if (IS_G200_SE(mdev)) { | |
abbee623 | 1136 | if (mdev->unique_rev_id >= 0x02) { |
414c4531 DA |
1137 | u8 hi_pri_lvl; |
1138 | u32 bpp; | |
1139 | u32 mb; | |
1140 | ||
f4510a27 | 1141 | if (crtc->primary->fb->bits_per_pixel > 16) |
414c4531 | 1142 | bpp = 32; |
f4510a27 | 1143 | else if (crtc->primary->fb->bits_per_pixel > 8) |
414c4531 DA |
1144 | bpp = 16; |
1145 | else | |
1146 | bpp = 8; | |
1147 | ||
1148 | mb = (mode->clock * bpp) / 1000; | |
1149 | if (mb > 3100) | |
1150 | hi_pri_lvl = 0; | |
1151 | else if (mb > 2600) | |
1152 | hi_pri_lvl = 1; | |
1153 | else if (mb > 1900) | |
1154 | hi_pri_lvl = 2; | |
1155 | else if (mb > 1160) | |
1156 | hi_pri_lvl = 3; | |
1157 | else if (mb > 440) | |
1158 | hi_pri_lvl = 4; | |
1159 | else | |
1160 | hi_pri_lvl = 5; | |
1161 | ||
91f8f105 CH |
1162 | WREG8(MGAREG_CRTCEXT_INDEX, 0x06); |
1163 | WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); | |
414c4531 | 1164 | } else { |
91f8f105 | 1165 | WREG8(MGAREG_CRTCEXT_INDEX, 0x06); |
abbee623 | 1166 | if (mdev->unique_rev_id >= 0x01) |
91f8f105 | 1167 | WREG8(MGAREG_CRTCEXT_DATA, 0x03); |
414c4531 | 1168 | else |
91f8f105 | 1169 | WREG8(MGAREG_CRTCEXT_DATA, 0x04); |
414c4531 DA |
1170 | } |
1171 | } | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ | |
1176 | static int mga_suspend(struct drm_crtc *crtc) | |
1177 | { | |
1178 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1179 | struct drm_device *dev = crtc->dev; | |
1180 | struct mga_device *mdev = dev->dev_private; | |
1181 | struct pci_dev *pdev = dev->pdev; | |
1182 | int option; | |
1183 | ||
1184 | if (mdev->suspended) | |
1185 | return 0; | |
1186 | ||
1187 | WREG_SEQ(1, 0x20); | |
1188 | WREG_ECRT(1, 0x30); | |
1189 | /* Disable the pixel clock */ | |
1190 | WREG_DAC(0x1a, 0x05); | |
1191 | /* Power down the DAC */ | |
1192 | WREG_DAC(0x1e, 0x18); | |
1193 | /* Power down the pixel PLL */ | |
1194 | WREG_DAC(0x1a, 0x0d); | |
1195 | ||
1196 | /* Disable PLLs and clocks */ | |
1197 | pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); | |
1198 | option &= ~(0x1F8024); | |
1199 | pci_write_config_dword(pdev, PCI_MGA_OPTION, option); | |
1200 | pci_set_power_state(pdev, PCI_D3hot); | |
1201 | pci_disable_device(pdev); | |
1202 | ||
1203 | mdev->suspended = true; | |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static int mga_resume(struct drm_crtc *crtc) | |
1209 | { | |
1210 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1211 | struct drm_device *dev = crtc->dev; | |
1212 | struct mga_device *mdev = dev->dev_private; | |
1213 | struct pci_dev *pdev = dev->pdev; | |
1214 | int option; | |
1215 | ||
1216 | if (!mdev->suspended) | |
1217 | return 0; | |
1218 | ||
1219 | pci_set_power_state(pdev, PCI_D0); | |
1220 | pci_enable_device(pdev); | |
1221 | ||
1222 | /* Disable sysclk */ | |
1223 | pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); | |
1224 | option &= ~(0x4); | |
1225 | pci_write_config_dword(pdev, PCI_MGA_OPTION, option); | |
1226 | ||
1227 | mdev->suspended = false; | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | #endif | |
1233 | ||
1234 | static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) | |
1235 | { | |
1236 | struct drm_device *dev = crtc->dev; | |
1237 | struct mga_device *mdev = dev->dev_private; | |
1238 | u8 seq1 = 0, crtcext1 = 0; | |
1239 | ||
1240 | switch (mode) { | |
1241 | case DRM_MODE_DPMS_ON: | |
1242 | seq1 = 0; | |
1243 | crtcext1 = 0; | |
1244 | mga_crtc_load_lut(crtc); | |
1245 | break; | |
1246 | case DRM_MODE_DPMS_STANDBY: | |
1247 | seq1 = 0x20; | |
1248 | crtcext1 = 0x10; | |
1249 | break; | |
1250 | case DRM_MODE_DPMS_SUSPEND: | |
1251 | seq1 = 0x20; | |
1252 | crtcext1 = 0x20; | |
1253 | break; | |
1254 | case DRM_MODE_DPMS_OFF: | |
1255 | seq1 = 0x20; | |
1256 | crtcext1 = 0x30; | |
1257 | break; | |
1258 | } | |
1259 | ||
1260 | #if 0 | |
1261 | if (mode == DRM_MODE_DPMS_OFF) { | |
1262 | mga_suspend(crtc); | |
1263 | } | |
1264 | #endif | |
1265 | WREG8(MGAREG_SEQ_INDEX, 0x01); | |
1266 | seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; | |
1267 | mga_wait_vsync(mdev); | |
1268 | mga_wait_busy(mdev); | |
1269 | WREG8(MGAREG_SEQ_DATA, seq1); | |
1270 | msleep(20); | |
1271 | WREG8(MGAREG_CRTCEXT_INDEX, 0x01); | |
1272 | crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; | |
1273 | WREG8(MGAREG_CRTCEXT_DATA, crtcext1); | |
1274 | ||
1275 | #if 0 | |
1276 | if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { | |
1277 | mga_resume(crtc); | |
1278 | drm_helper_resume_force_mode(dev); | |
1279 | } | |
1280 | #endif | |
1281 | } | |
1282 | ||
1283 | /* | |
1284 | * This is called before a mode is programmed. A typical use might be to | |
1285 | * enable DPMS during the programming to avoid seeing intermediate stages, | |
1286 | * but that's not relevant to us | |
1287 | */ | |
1288 | static void mga_crtc_prepare(struct drm_crtc *crtc) | |
1289 | { | |
1290 | struct drm_device *dev = crtc->dev; | |
1291 | struct mga_device *mdev = dev->dev_private; | |
1292 | u8 tmp; | |
1293 | ||
1294 | /* mga_resume(crtc);*/ | |
1295 | ||
1296 | WREG8(MGAREG_CRTC_INDEX, 0x11); | |
1297 | tmp = RREG8(MGAREG_CRTC_DATA); | |
1298 | WREG_CRT(0x11, tmp | 0x80); | |
1299 | ||
1300 | if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { | |
1301 | WREG_SEQ(0, 1); | |
1302 | msleep(50); | |
1303 | WREG_SEQ(1, 0x20); | |
1304 | msleep(20); | |
1305 | } else { | |
1306 | WREG8(MGAREG_SEQ_INDEX, 0x1); | |
1307 | tmp = RREG8(MGAREG_SEQ_DATA); | |
1308 | ||
1309 | /* start sync reset */ | |
1310 | WREG_SEQ(0, 1); | |
1311 | WREG_SEQ(1, tmp | 0x20); | |
1312 | } | |
1313 | ||
6d857c18 | 1314 | if (mdev->type == G200_WB || mdev->type == G200_EW3) |
414c4531 DA |
1315 | mga_g200wb_prepare(crtc); |
1316 | ||
1317 | WREG_CRT(17, 0); | |
1318 | } | |
1319 | ||
1320 | /* | |
1321 | * This is called after a mode is programmed. It should reverse anything done | |
1322 | * by the prepare function | |
1323 | */ | |
1324 | static void mga_crtc_commit(struct drm_crtc *crtc) | |
1325 | { | |
1326 | struct drm_device *dev = crtc->dev; | |
1327 | struct mga_device *mdev = dev->dev_private; | |
d584ff82 | 1328 | const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
414c4531 DA |
1329 | u8 tmp; |
1330 | ||
6d857c18 | 1331 | if (mdev->type == G200_WB || mdev->type == G200_EW3) |
414c4531 DA |
1332 | mga_g200wb_commit(crtc); |
1333 | ||
1334 | if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { | |
1335 | msleep(50); | |
1336 | WREG_SEQ(1, 0x0); | |
1337 | msleep(20); | |
1338 | WREG_SEQ(0, 0x3); | |
1339 | } else { | |
1340 | WREG8(MGAREG_SEQ_INDEX, 0x1); | |
1341 | tmp = RREG8(MGAREG_SEQ_DATA); | |
1342 | ||
1343 | tmp &= ~0x20; | |
1344 | WREG_SEQ(0x1, tmp); | |
1345 | WREG_SEQ(0, 3); | |
1346 | } | |
1347 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * The core can pass us a set of gamma values to program. We actually only | |
1352 | * use this for 8-bit mode so can't perform smooth fades on deeper modes, | |
1353 | * but it's a requirement that we provide the function | |
1354 | */ | |
7ea77283 ML |
1355 | static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
1356 | u16 *blue, uint32_t size) | |
414c4531 DA |
1357 | { |
1358 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
414c4531 DA |
1359 | int i; |
1360 | ||
7ea77283 | 1361 | for (i = 0; i < size; i++) { |
414c4531 DA |
1362 | mga_crtc->lut_r[i] = red[i] >> 8; |
1363 | mga_crtc->lut_g[i] = green[i] >> 8; | |
1364 | mga_crtc->lut_b[i] = blue[i] >> 8; | |
1365 | } | |
1366 | mga_crtc_load_lut(crtc); | |
7ea77283 ML |
1367 | |
1368 | return 0; | |
414c4531 DA |
1369 | } |
1370 | ||
1371 | /* Simple cleanup function */ | |
1372 | static void mga_crtc_destroy(struct drm_crtc *crtc) | |
1373 | { | |
1374 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1375 | ||
1376 | drm_crtc_cleanup(crtc); | |
1377 | kfree(mga_crtc); | |
1378 | } | |
1379 | ||
64c29076 EE |
1380 | static void mga_crtc_disable(struct drm_crtc *crtc) |
1381 | { | |
1382 | int ret; | |
1383 | DRM_DEBUG_KMS("\n"); | |
1384 | mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
f4510a27 MR |
1385 | if (crtc->primary->fb) { |
1386 | struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); | |
64c29076 EE |
1387 | struct drm_gem_object *obj = mga_fb->obj; |
1388 | struct mgag200_bo *bo = gem_to_mga_bo(obj); | |
1389 | ret = mgag200_bo_reserve(bo, false); | |
1390 | if (ret) | |
1391 | return; | |
1392 | mgag200_bo_push_sysram(bo); | |
1393 | mgag200_bo_unreserve(bo); | |
1394 | } | |
f4510a27 | 1395 | crtc->primary->fb = NULL; |
64c29076 EE |
1396 | } |
1397 | ||
414c4531 DA |
1398 | /* These provide the minimum set of functions required to handle a CRTC */ |
1399 | static const struct drm_crtc_funcs mga_crtc_funcs = { | |
a080db9f CH |
1400 | .cursor_set = mga_crtc_cursor_set, |
1401 | .cursor_move = mga_crtc_cursor_move, | |
414c4531 DA |
1402 | .gamma_set = mga_crtc_gamma_set, |
1403 | .set_config = drm_crtc_helper_set_config, | |
1404 | .destroy = mga_crtc_destroy, | |
1405 | }; | |
1406 | ||
1407 | static const struct drm_crtc_helper_funcs mga_helper_funcs = { | |
64c29076 | 1408 | .disable = mga_crtc_disable, |
414c4531 | 1409 | .dpms = mga_crtc_dpms, |
414c4531 DA |
1410 | .mode_set = mga_crtc_mode_set, |
1411 | .mode_set_base = mga_crtc_mode_set_base, | |
1412 | .prepare = mga_crtc_prepare, | |
1413 | .commit = mga_crtc_commit, | |
1414 | .load_lut = mga_crtc_load_lut, | |
1415 | }; | |
1416 | ||
1417 | /* CRTC setup */ | |
f1998fe2 | 1418 | static void mga_crtc_init(struct mga_device *mdev) |
414c4531 | 1419 | { |
414c4531 DA |
1420 | struct mga_crtc *mga_crtc; |
1421 | int i; | |
1422 | ||
1423 | mga_crtc = kzalloc(sizeof(struct mga_crtc) + | |
1424 | (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), | |
1425 | GFP_KERNEL); | |
1426 | ||
1427 | if (mga_crtc == NULL) | |
1428 | return; | |
1429 | ||
f1998fe2 | 1430 | drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); |
414c4531 DA |
1431 | |
1432 | drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); | |
1433 | mdev->mode_info.crtc = mga_crtc; | |
1434 | ||
1435 | for (i = 0; i < MGAG200_LUT_SIZE; i++) { | |
1436 | mga_crtc->lut_r[i] = i; | |
1437 | mga_crtc->lut_g[i] = i; | |
1438 | mga_crtc->lut_b[i] = i; | |
1439 | } | |
1440 | ||
1441 | drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); | |
1442 | } | |
1443 | ||
1444 | /** Sets the color ramps on behalf of fbcon */ | |
1445 | void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
1446 | u16 blue, int regno) | |
1447 | { | |
1448 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1449 | ||
1450 | mga_crtc->lut_r[regno] = red >> 8; | |
1451 | mga_crtc->lut_g[regno] = green >> 8; | |
1452 | mga_crtc->lut_b[regno] = blue >> 8; | |
1453 | } | |
1454 | ||
1455 | /** Gets the color ramps on behalf of fbcon */ | |
1456 | void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
1457 | u16 *blue, int regno) | |
1458 | { | |
1459 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1460 | ||
1461 | *red = (u16)mga_crtc->lut_r[regno] << 8; | |
1462 | *green = (u16)mga_crtc->lut_g[regno] << 8; | |
1463 | *blue = (u16)mga_crtc->lut_b[regno] << 8; | |
1464 | } | |
1465 | ||
1466 | /* | |
1467 | * The encoder comes after the CRTC in the output pipeline, but before | |
1468 | * the connector. It's responsible for ensuring that the digital | |
1469 | * stream is appropriately converted into the output format. Setup is | |
1470 | * very simple in this case - all we have to do is inform qemu of the | |
1471 | * colour depth in order to ensure that it displays appropriately | |
1472 | */ | |
1473 | ||
1474 | /* | |
1475 | * These functions are analagous to those in the CRTC code, but are intended | |
1476 | * to handle any encoder-specific limitations | |
1477 | */ | |
414c4531 DA |
1478 | static void mga_encoder_mode_set(struct drm_encoder *encoder, |
1479 | struct drm_display_mode *mode, | |
1480 | struct drm_display_mode *adjusted_mode) | |
1481 | { | |
1482 | ||
1483 | } | |
1484 | ||
1485 | static void mga_encoder_dpms(struct drm_encoder *encoder, int state) | |
1486 | { | |
1487 | return; | |
1488 | } | |
1489 | ||
1490 | static void mga_encoder_prepare(struct drm_encoder *encoder) | |
1491 | { | |
1492 | } | |
1493 | ||
1494 | static void mga_encoder_commit(struct drm_encoder *encoder) | |
1495 | { | |
1496 | } | |
1497 | ||
080fd6b5 | 1498 | static void mga_encoder_destroy(struct drm_encoder *encoder) |
414c4531 DA |
1499 | { |
1500 | struct mga_encoder *mga_encoder = to_mga_encoder(encoder); | |
1501 | drm_encoder_cleanup(encoder); | |
1502 | kfree(mga_encoder); | |
1503 | } | |
1504 | ||
1505 | static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { | |
1506 | .dpms = mga_encoder_dpms, | |
414c4531 DA |
1507 | .mode_set = mga_encoder_mode_set, |
1508 | .prepare = mga_encoder_prepare, | |
1509 | .commit = mga_encoder_commit, | |
1510 | }; | |
1511 | ||
1512 | static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { | |
1513 | .destroy = mga_encoder_destroy, | |
1514 | }; | |
1515 | ||
1516 | static struct drm_encoder *mga_encoder_init(struct drm_device *dev) | |
1517 | { | |
1518 | struct drm_encoder *encoder; | |
1519 | struct mga_encoder *mga_encoder; | |
1520 | ||
1521 | mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); | |
1522 | if (!mga_encoder) | |
1523 | return NULL; | |
1524 | ||
1525 | encoder = &mga_encoder->base; | |
1526 | encoder->possible_crtcs = 0x1; | |
1527 | ||
1528 | drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, | |
13a3d91f | 1529 | DRM_MODE_ENCODER_DAC, NULL); |
414c4531 DA |
1530 | drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); |
1531 | ||
1532 | return encoder; | |
1533 | } | |
1534 | ||
1535 | ||
1536 | static int mga_vga_get_modes(struct drm_connector *connector) | |
1537 | { | |
1538 | struct mga_connector *mga_connector = to_mga_connector(connector); | |
1539 | struct edid *edid; | |
1540 | int ret = 0; | |
1541 | ||
1542 | edid = drm_get_edid(connector, &mga_connector->i2c->adapter); | |
1543 | if (edid) { | |
1544 | drm_mode_connector_update_edid_property(connector, edid); | |
1545 | ret = drm_add_edid_modes(connector, edid); | |
414c4531 DA |
1546 | kfree(edid); |
1547 | } | |
1548 | return ret; | |
1549 | } | |
1550 | ||
abbee623 JL |
1551 | static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, |
1552 | int bits_per_pixel) | |
1553 | { | |
1554 | uint32_t total_area, divisor; | |
c24ca5be | 1555 | uint64_t active_area, pixels_per_second, bandwidth; |
abbee623 JL |
1556 | uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; |
1557 | ||
1558 | divisor = 1024; | |
1559 | ||
1560 | if (!mode->htotal || !mode->vtotal || !mode->clock) | |
1561 | return 0; | |
1562 | ||
1563 | active_area = mode->hdisplay * mode->vdisplay; | |
1564 | total_area = mode->htotal * mode->vtotal; | |
1565 | ||
1566 | pixels_per_second = active_area * mode->clock * 1000; | |
1567 | do_div(pixels_per_second, total_area); | |
1568 | ||
1569 | bandwidth = pixels_per_second * bytes_per_pixel * 100; | |
1570 | do_div(bandwidth, divisor); | |
1571 | ||
1572 | return (uint32_t)(bandwidth); | |
1573 | } | |
1574 | ||
1575 | #define MODE_BANDWIDTH MODE_BAD | |
1576 | ||
414c4531 DA |
1577 | static int mga_vga_mode_valid(struct drm_connector *connector, |
1578 | struct drm_display_mode *mode) | |
1579 | { | |
0ba53171 CH |
1580 | struct drm_device *dev = connector->dev; |
1581 | struct mga_device *mdev = (struct mga_device*)dev->dev_private; | |
0ba53171 | 1582 | int bpp = 32; |
0ba53171 | 1583 | |
abbee623 JL |
1584 | if (IS_G200_SE(mdev)) { |
1585 | if (mdev->unique_rev_id == 0x01) { | |
1586 | if (mode->hdisplay > 1600) | |
1587 | return MODE_VIRTUAL_X; | |
1588 | if (mode->vdisplay > 1200) | |
1589 | return MODE_VIRTUAL_Y; | |
1590 | if (mga_vga_calculate_mode_bandwidth(mode, bpp) | |
1591 | > (24400 * 1024)) | |
1592 | return MODE_BANDWIDTH; | |
e829d7ef | 1593 | } else if (mdev->unique_rev_id == 0x02) { |
abbee623 JL |
1594 | if (mode->hdisplay > 1920) |
1595 | return MODE_VIRTUAL_X; | |
1596 | if (mode->vdisplay > 1200) | |
1597 | return MODE_VIRTUAL_Y; | |
1598 | if (mga_vga_calculate_mode_bandwidth(mode, bpp) | |
1599 | > (30100 * 1024)) | |
1600 | return MODE_BANDWIDTH; | |
1601 | } | |
1602 | } else if (mdev->type == G200_WB) { | |
1603 | if (mode->hdisplay > 1280) | |
1604 | return MODE_VIRTUAL_X; | |
1605 | if (mode->vdisplay > 1024) | |
1606 | return MODE_VIRTUAL_Y; | |
1607 | if (mga_vga_calculate_mode_bandwidth(mode, | |
1608 | bpp > (31877 * 1024))) | |
1609 | return MODE_BANDWIDTH; | |
1610 | } else if (mdev->type == G200_EV && | |
1611 | (mga_vga_calculate_mode_bandwidth(mode, bpp) | |
1612 | > (32700 * 1024))) { | |
1613 | return MODE_BANDWIDTH; | |
ec22b4aa | 1614 | } else if (mdev->type == G200_EH && |
abbee623 JL |
1615 | (mga_vga_calculate_mode_bandwidth(mode, bpp) |
1616 | > (37500 * 1024))) { | |
1617 | return MODE_BANDWIDTH; | |
ec22b4aa | 1618 | } else if (mdev->type == G200_ER && |
abbee623 JL |
1619 | (mga_vga_calculate_mode_bandwidth(mode, |
1620 | bpp) > (55000 * 1024))) { | |
1621 | return MODE_BANDWIDTH; | |
1622 | } | |
414c4531 | 1623 | |
25161084 AJ |
1624 | if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || |
1625 | (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { | |
1626 | return MODE_H_ILLEGAL; | |
1627 | } | |
1628 | ||
414c4531 DA |
1629 | if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || |
1630 | mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || | |
1631 | mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || | |
1632 | mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { | |
1633 | return MODE_BAD; | |
1634 | } | |
1635 | ||
0ba53171 | 1636 | /* Validate the mode input by the user */ |
eaf99c74 CW |
1637 | if (connector->cmdline_mode.specified) { |
1638 | if (connector->cmdline_mode.bpp_specified) | |
1639 | bpp = connector->cmdline_mode.bpp; | |
0ba53171 CH |
1640 | } |
1641 | ||
1642 | if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { | |
eaf99c74 CW |
1643 | if (connector->cmdline_mode.specified) |
1644 | connector->cmdline_mode.specified = false; | |
0ba53171 CH |
1645 | return MODE_BAD; |
1646 | } | |
1647 | ||
414c4531 DA |
1648 | return MODE_OK; |
1649 | } | |
1650 | ||
080fd6b5 | 1651 | static struct drm_encoder *mga_connector_best_encoder(struct drm_connector |
414c4531 DA |
1652 | *connector) |
1653 | { | |
1654 | int enc_id = connector->encoder_ids[0]; | |
414c4531 | 1655 | /* pick the encoder ids */ |
c7e95114 RC |
1656 | if (enc_id) |
1657 | return drm_encoder_find(connector->dev, enc_id); | |
414c4531 DA |
1658 | return NULL; |
1659 | } | |
1660 | ||
1661 | static enum drm_connector_status mga_vga_detect(struct drm_connector | |
1662 | *connector, bool force) | |
1663 | { | |
1664 | return connector_status_connected; | |
1665 | } | |
1666 | ||
1667 | static void mga_connector_destroy(struct drm_connector *connector) | |
1668 | { | |
1669 | struct mga_connector *mga_connector = to_mga_connector(connector); | |
1670 | mgag200_i2c_destroy(mga_connector->i2c); | |
1671 | drm_connector_cleanup(connector); | |
1672 | kfree(connector); | |
1673 | } | |
1674 | ||
71cb7495 | 1675 | static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { |
414c4531 DA |
1676 | .get_modes = mga_vga_get_modes, |
1677 | .mode_valid = mga_vga_mode_valid, | |
1678 | .best_encoder = mga_connector_best_encoder, | |
1679 | }; | |
1680 | ||
71cb7495 | 1681 | static const struct drm_connector_funcs mga_vga_connector_funcs = { |
414c4531 DA |
1682 | .dpms = drm_helper_connector_dpms, |
1683 | .detect = mga_vga_detect, | |
1684 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1685 | .destroy = mga_connector_destroy, | |
1686 | }; | |
1687 | ||
1688 | static struct drm_connector *mga_vga_init(struct drm_device *dev) | |
1689 | { | |
1690 | struct drm_connector *connector; | |
1691 | struct mga_connector *mga_connector; | |
1692 | ||
1693 | mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); | |
1694 | if (!mga_connector) | |
1695 | return NULL; | |
1696 | ||
1697 | connector = &mga_connector->base; | |
1698 | ||
1699 | drm_connector_init(dev, connector, | |
1700 | &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); | |
1701 | ||
1702 | drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); | |
1703 | ||
34ea3d38 | 1704 | drm_connector_register(connector); |
3d5a1c5e | 1705 | |
414c4531 DA |
1706 | mga_connector->i2c = mgag200_i2c_create(dev); |
1707 | if (!mga_connector->i2c) | |
1708 | DRM_ERROR("failed to add ddc bus\n"); | |
1709 | ||
1710 | return connector; | |
1711 | } | |
1712 | ||
1713 | ||
1714 | int mgag200_modeset_init(struct mga_device *mdev) | |
1715 | { | |
1716 | struct drm_encoder *encoder; | |
1717 | struct drm_connector *connector; | |
1718 | int ret; | |
1719 | ||
1720 | mdev->mode_info.mode_config_initialized = true; | |
1721 | ||
1722 | mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; | |
1723 | mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; | |
1724 | ||
1725 | mdev->dev->mode_config.fb_base = mdev->mc.vram_base; | |
1726 | ||
f1998fe2 | 1727 | mga_crtc_init(mdev); |
414c4531 DA |
1728 | |
1729 | encoder = mga_encoder_init(mdev->dev); | |
1730 | if (!encoder) { | |
1731 | DRM_ERROR("mga_encoder_init failed\n"); | |
1732 | return -1; | |
1733 | } | |
1734 | ||
1735 | connector = mga_vga_init(mdev->dev); | |
1736 | if (!connector) { | |
1737 | DRM_ERROR("mga_vga_init failed\n"); | |
1738 | return -1; | |
1739 | } | |
1740 | ||
1741 | drm_mode_connector_attach_encoder(connector, encoder); | |
1742 | ||
1743 | ret = mgag200_fbdev_init(mdev); | |
1744 | if (ret) { | |
1745 | DRM_ERROR("mga_fbdev_init failed\n"); | |
1746 | return ret; | |
1747 | } | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | void mgag200_modeset_fini(struct mga_device *mdev) | |
1753 | { | |
1754 | ||
1755 | } |