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drm/mgag200: Don't change unrelated registers during modeset
[deliverable/linux.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
CommitLineData
414c4531
DA		 1/*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14#include <linux/delay.h>
15
760285e7
DH		 16#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
414c4531
DA		 18
19#include "mgag200_drv.h"
20
21#define MGAG200_LUT_SIZE 256
22
23/*
24 * This file contains setup code for the CRTC.
25 */
26
27static void mga_crtc_load_lut(struct drm_crtc *crtc)
28{
29 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
30 struct drm_device *dev = crtc->dev;
31 struct mga_device *mdev = dev->dev_private;
32 int i;
33
34 if (!crtc->enabled)
35 return;
36
37 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
38
39 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
40 /* VGA registers */
41 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
42 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
43 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
44 }
45}
46
47static inline void mga_wait_vsync(struct mga_device *mdev)
48{
49 unsigned int count = 0;
50 unsigned int status = 0;
51
52 do {
53 status = RREG32(MGAREG_Status);
54 count++;
55 } while ((status & 0x08) && (count < 250000));
56 count = 0;
57 status = 0;
58 do {
59 status = RREG32(MGAREG_Status);
60 count++;
61 } while (!(status & 0x08) && (count < 250000));
62}
63
64static inline void mga_wait_busy(struct mga_device *mdev)
65{
66 unsigned int count = 0;
67 unsigned int status = 0;
68 do {
69 status = RREG8(MGAREG_Status + 2);
70 count++;
71 } while ((status & 0x01) && (count < 500000));
72}
73
74/*
75 * The core passes the desired mode to the CRTC code to see whether any
76 * CRTC-specific modifications need to be made to it. We're in a position
77 * to just pass that straight through, so this does nothing
78 */
79static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae
LP		 80 const struct drm_display_mode *mode,
81 struct drm_display_mode *adjusted_mode)
414c4531
DA		 82{
83 return true;
84}
85
86static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
87{
88 unsigned int vcomax, vcomin, pllreffreq;
89 unsigned int delta, tmpdelta, permitteddelta;
90 unsigned int testp, testm, testn;
91 unsigned int p, m, n;
92 unsigned int computed;
93
94 m = n = p = 0;
95 vcomax = 320000;
96 vcomin = 160000;
97 pllreffreq = 25000;
98
99 delta = 0xffffffff;
100 permitteddelta = clock * 5 / 1000;
101
102 for (testp = 8; testp > 0; testp /= 2) {
103 if (clock * testp > vcomax)
104 continue;
105 if (clock * testp < vcomin)
106 continue;
107
108 for (testn = 17; testn < 256; testn++) {
109 for (testm = 1; testm < 32; testm++) {
110 computed = (pllreffreq * testn) /
111 (testm * testp);
112 if (computed > clock)
113 tmpdelta = computed - clock;
114 else
115 tmpdelta = clock - computed;
116 if (tmpdelta < delta) {
117 delta = tmpdelta;
118 m = testm - 1;
119 n = testn - 1;
120 p = testp - 1;
121 }
122 }
123 }
124 }
125
126 if (delta > permitteddelta) {
127 printk(KERN_WARNING "PLL delta too large\n");
128 return 1;
129 }
130
131 WREG_DAC(MGA1064_PIX_PLLC_M, m);
132 WREG_DAC(MGA1064_PIX_PLLC_N, n);
133 WREG_DAC(MGA1064_PIX_PLLC_P, p);
134 return 0;
135}
136
137static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
138{
139 unsigned int vcomax, vcomin, pllreffreq;
140 unsigned int delta, tmpdelta, permitteddelta;
141 unsigned int testp, testm, testn;
142 unsigned int p, m, n;
143 unsigned int computed;
144 int i, j, tmpcount, vcount;
145 bool pll_locked = false;
146 u8 tmp;
147
148 m = n = p = 0;
149 vcomax = 550000;
150 vcomin = 150000;
151 pllreffreq = 48000;
152
153 delta = 0xffffffff;
154 permitteddelta = clock * 5 / 1000;
155
156 for (testp = 1; testp < 9; testp++) {
157 if (clock * testp > vcomax)
158 continue;
159 if (clock * testp < vcomin)
160 continue;
161
162 for (testm = 1; testm < 17; testm++) {
163 for (testn = 1; testn < 151; testn++) {
164 computed = (pllreffreq * testn) /
165 (testm * testp);
166 if (computed > clock)
167 tmpdelta = computed - clock;
168 else
169 tmpdelta = clock - computed;
170 if (tmpdelta < delta) {
171 delta = tmpdelta;
172 n = testn - 1;
173 m = (testm - 1) | ((n >> 1) & 0x80);
174 p = testp - 1;
175 }
176 }
177 }
178 }
179
180 for (i = 0; i <= 32 && pll_locked == false; i++) {
181 if (i > 0) {
182 WREG8(MGAREG_CRTC_INDEX, 0x1e);
183 tmp = RREG8(MGAREG_CRTC_DATA);
184 if (tmp < 0xff)
185 WREG8(MGAREG_CRTC_DATA, tmp+1);
186 }
187
188 /* set pixclkdis to 1 */
189 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
190 tmp = RREG8(DAC_DATA);
191 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
192 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
193
194 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
195 tmp = RREG8(DAC_DATA);
196 tmp |= MGA1064_REMHEADCTL_CLKDIS;
197 WREG_DAC(MGA1064_REMHEADCTL, tmp);
198
199 /* select PLL Set C */
200 tmp = RREG8(MGAREG_MEM_MISC_READ);
201 tmp |= 0x3 << 2;
202 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
203
204 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
205 tmp = RREG8(DAC_DATA);
206 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
207 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
208
209 udelay(500);
210
211 /* reset the PLL */
212 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
213 tmp = RREG8(DAC_DATA);
214 tmp &= ~0x04;
215 WREG_DAC(MGA1064_VREF_CTL, tmp);
216
217 udelay(50);
218
219 /* program pixel pll register */
220 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
221 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
222 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
223
224 udelay(50);
225
226 /* turn pll on */
227 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
228 tmp = RREG8(DAC_DATA);
229 tmp |= 0x04;
230 WREG_DAC(MGA1064_VREF_CTL, tmp);
231
232 udelay(500);
233
234 /* select the pixel pll */
235 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
236 tmp = RREG8(DAC_DATA);
237 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
238 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
239 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
240
241 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
242 tmp = RREG8(DAC_DATA);
243 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
244 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
245 WREG_DAC(MGA1064_REMHEADCTL, tmp);
246
247 /* reset dotclock rate bit */
248 WREG8(MGAREG_SEQ_INDEX, 1);
249 tmp = RREG8(MGAREG_SEQ_DATA);
250 tmp &= ~0x8;
251 WREG8(MGAREG_SEQ_DATA, tmp);
252
253 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
254 tmp = RREG8(DAC_DATA);
255 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
256 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
257
258 vcount = RREG8(MGAREG_VCOUNT);
259
260 for (j = 0; j < 30 && pll_locked == false; j++) {
261 tmpcount = RREG8(MGAREG_VCOUNT);
262 if (tmpcount < vcount)
263 vcount = 0;
264 if ((tmpcount - vcount) > 2)
265 pll_locked = true;
266 else
267 udelay(5);
268 }
269 }
270 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
271 tmp = RREG8(DAC_DATA);
272 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
273 WREG_DAC(MGA1064_REMHEADCTL, tmp);
274 return 0;
275}
276
277static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
278{
279 unsigned int vcomax, vcomin, pllreffreq;
280 unsigned int delta, tmpdelta, permitteddelta;
281 unsigned int testp, testm, testn;
282 unsigned int p, m, n;
283 unsigned int computed;
284 u8 tmp;
285
286 m = n = p = 0;
287 vcomax = 550000;
288 vcomin = 150000;
289 pllreffreq = 50000;
290
291 delta = 0xffffffff;
292 permitteddelta = clock * 5 / 1000;
293
294 for (testp = 16; testp > 0; testp--) {
295 if (clock * testp > vcomax)
296 continue;
297 if (clock * testp < vcomin)
298 continue;
299
300 for (testn = 1; testn < 257; testn++) {
301 for (testm = 1; testm < 17; testm++) {
302 computed = (pllreffreq * testn) /
303 (testm * testp);
304 if (computed > clock)
305 tmpdelta = computed - clock;
306 else
307 tmpdelta = clock - computed;
308 if (tmpdelta < delta) {
309 delta = tmpdelta;
310 n = testn - 1;
311 m = testm - 1;
312 p = testp - 1;
313 }
314 }
315 }
316 }
317
318 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
319 tmp = RREG8(DAC_DATA);
320 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
321 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
322
323 tmp = RREG8(MGAREG_MEM_MISC_READ);
324 tmp |= 0x3 << 2;
325 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
326
327 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
328 tmp = RREG8(DAC_DATA);
329 WREG_DAC(MGA1064_PIX_PLL_STAT, tmp & ~0x40);
330
331 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
332 tmp = RREG8(DAC_DATA);
333 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
334 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
335
336 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
337 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
338 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
339
340 udelay(50);
341
342 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
343 tmp = RREG8(DAC_DATA);
344 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
345 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
346
347 udelay(500);
348
349 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
350 tmp = RREG8(DAC_DATA);
351 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
352 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
353 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
354
355 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
356 tmp = RREG8(DAC_DATA);
357 WREG_DAC(MGA1064_PIX_PLL_STAT, tmp | 0x40);
358
359 tmp = RREG8(MGAREG_MEM_MISC_READ);
360 tmp |= (0x3 << 2);
361 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
362
363 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
364 tmp = RREG8(DAC_DATA);
365 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
366 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
367
368 return 0;
369}
370
371static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
372{
373 unsigned int vcomax, vcomin, pllreffreq;
374 unsigned int delta, tmpdelta, permitteddelta;
375 unsigned int testp, testm, testn;
376 unsigned int p, m, n;
377 unsigned int computed;
378 int i, j, tmpcount, vcount;
379 u8 tmp;
380 bool pll_locked = false;
381
382 m = n = p = 0;
383 vcomax = 800000;
384 vcomin = 400000;
260b3f12 385 pllreffreq = 33333;
414c4531
DA		 386
387 delta = 0xffffffff;
388 permitteddelta = clock * 5 / 1000;
389
260b3f12 390 for (testp = 16; testp > 0; testp >>= 1) {
414c4531
DA		 391 if (clock * testp > vcomax)
392 continue;
393 if (clock * testp < vcomin)
394 continue;
395
396 for (testm = 1; testm < 33; testm++) {
260b3f12 397 for (testn = 17; testn < 257; testn++) {
414c4531
DA		 398 computed = (pllreffreq * testn) /
399 (testm * testp);
400 if (computed > clock)
401 tmpdelta = computed - clock;
402 else
403 tmpdelta = clock - computed;
404 if (tmpdelta < delta) {
405 delta = tmpdelta;
406 n = testn - 1;
260b3f12 407 m = (testm - 1);
414c4531
DA		 408 p = testp - 1;
409 }
410 if ((clock * testp) >= 600000)
260b3f12 411 p |= 0x80;
414c4531
DA		 412 }
413 }
414 }
415 for (i = 0; i <= 32 && pll_locked == false; i++) {
416 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
417 tmp = RREG8(DAC_DATA);
418 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
419 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
420
421 tmp = RREG8(MGAREG_MEM_MISC_READ);
422 tmp |= 0x3 << 2;
423 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
424
425 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
426 tmp = RREG8(DAC_DATA);
427 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
428 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
429
430 udelay(500);
431
432 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
433 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
434 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
435
436 udelay(500);
437
438 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
439 tmp = RREG8(DAC_DATA);
440 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
441 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
442 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
443
444 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
445 tmp = RREG8(DAC_DATA);
446 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
447 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
448 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
449
450 vcount = RREG8(MGAREG_VCOUNT);
451
452 for (j = 0; j < 30 && pll_locked == false; j++) {
453 tmpcount = RREG8(MGAREG_VCOUNT);
454 if (tmpcount < vcount)
455 vcount = 0;
456 if ((tmpcount - vcount) > 2)
457 pll_locked = true;
458 else
459 udelay(5);
460 }
461 }
462
463 return 0;
464}
465
466static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
467{
468 unsigned int vcomax, vcomin, pllreffreq;
469 unsigned int delta, tmpdelta;
9830605d 470 int testr, testn, testm, testo;
414c4531 471 unsigned int p, m, n;
9830605d 472 unsigned int computed, vco;
414c4531 473 int tmp;
9830605d 474 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
414c4531
DA		 475
476 m = n = p = 0;
477 vcomax = 1488000;
478 vcomin = 1056000;
479 pllreffreq = 48000;
480
481 delta = 0xffffffff;
482
483 for (testr = 0; testr < 4; testr++) {
484 if (delta == 0)
485 break;
486 for (testn = 5; testn < 129; testn++) {
487 if (delta == 0)
488 break;
489 for (testm = 3; testm >= 0; testm--) {
490 if (delta == 0)
491 break;
492 for (testo = 5; testo < 33; testo++) {
9830605d 493 vco = pllreffreq * (testn + 1) /
414c4531 494 (testr + 1);
9830605d 495 if (vco < vcomin)
414c4531 496 continue;
9830605d 497 if (vco > vcomax)
414c4531 498 continue;
9830605d 499 computed = vco / (m_div_val[testm] * (testo + 1));
414c4531
DA		 500 if (computed > clock)
501 tmpdelta = computed - clock;
502 else
503 tmpdelta = clock - computed;
504 if (tmpdelta < delta) {
505 delta = tmpdelta;
506 m = testm | (testo << 3);
507 n = testn;
508 p = testr | (testr << 3);
509 }
510 }
511 }
512 }
513 }
514
515 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
516 tmp = RREG8(DAC_DATA);
517 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
518 WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
519
520 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
521 tmp = RREG8(DAC_DATA);
522 tmp |= MGA1064_REMHEADCTL_CLKDIS;
523 WREG_DAC(MGA1064_REMHEADCTL, tmp);
524
525 tmp = RREG8(MGAREG_MEM_MISC_READ);
526 tmp |= (0x3<<2) | 0xc0;
527 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
528
529 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
530 tmp = RREG8(DAC_DATA);
531 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
532 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
533 WREG_DAC(MGA1064_PIX_CLK_CTL, tmp);
534
535 udelay(500);
536
537 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
538 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
539 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
540
541 udelay(50);
542
543 return 0;
544}
545
546static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
547{
548 switch(mdev->type) {
549 case G200_SE_A:
550 case G200_SE_B:
551 return mga_g200se_set_plls(mdev, clock);
552 break;
553 case G200_WB:
554 return mga_g200wb_set_plls(mdev, clock);
555 break;
556 case G200_EV:
557 return mga_g200ev_set_plls(mdev, clock);
558 break;
559 case G200_EH:
560 return mga_g200eh_set_plls(mdev, clock);
561 break;
562 case G200_ER:
563 return mga_g200er_set_plls(mdev, clock);
564 break;
565 }
566 return 0;
567}
568
569static void mga_g200wb_prepare(struct drm_crtc *crtc)
570{
571 struct mga_device *mdev = crtc->dev->dev_private;
572 u8 tmp;
573 int iter_max;
574
575 /* 1- The first step is to warn the BMC of an upcoming mode change.
576 * We are putting the misc<0> to output.*/
577
578 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
579 tmp = RREG8(DAC_DATA);
580 tmp |= 0x10;
581 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
582
583 /* we are putting a 1 on the misc<0> line */
584 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
585 tmp = RREG8(DAC_DATA);
586 tmp |= 0x10;
587 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
588
589 /* 2- Second step to mask and further scan request
590 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
591 */
592 WREG8(DAC_INDEX, MGA1064_SPAREREG);
593 tmp = RREG8(DAC_DATA);
594 tmp |= 0x80;
595 WREG_DAC(MGA1064_SPAREREG, tmp);
596
597 /* 3a- the third step is to verifu if there is an active scan
598 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
599 */
600 iter_max = 300;
601 while (!(tmp & 0x1) && iter_max) {
602 WREG8(DAC_INDEX, MGA1064_SPAREREG);
603 tmp = RREG8(DAC_DATA);
604 udelay(1000);
605 iter_max--;
606 }
607
608 /* 3b- this step occurs only if the remove is actually scanning
609 * we are waiting for the end of the frame which is a 1 on
610 * remvsyncsts (XSPAREREG<1>)
611 */
612 if (iter_max) {
613 iter_max = 300;
614 while ((tmp & 0x2) && iter_max) {
615 WREG8(DAC_INDEX, MGA1064_SPAREREG);
616 tmp = RREG8(DAC_DATA);
617 udelay(1000);
618 iter_max--;
619 }
620 }
621}
622
623static void mga_g200wb_commit(struct drm_crtc *crtc)
624{
625 u8 tmp;
626 struct mga_device *mdev = crtc->dev->dev_private;
627
628 /* 1- The first step is to ensure that the vrsten and hrsten are set */
629 WREG8(MGAREG_CRTCEXT_INDEX, 1);
630 tmp = RREG8(MGAREG_CRTCEXT_DATA);
631 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
632
633 /* 2- second step is to assert the rstlvl2 */
634 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
635 tmp = RREG8(DAC_DATA);
636 tmp |= 0x8;
637 WREG8(DAC_DATA, tmp);
638
639 /* wait 10 us */
640 udelay(10);
641
642 /* 3- deassert rstlvl2 */
643 tmp &= ~0x08;
644 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
645 WREG8(DAC_DATA, tmp);
646
647 /* 4- remove mask of scan request */
648 WREG8(DAC_INDEX, MGA1064_SPAREREG);
649 tmp = RREG8(DAC_DATA);
650 tmp &= ~0x80;
651 WREG8(DAC_DATA, tmp);
652
653 /* 5- put back a 0 on the misc<0> line */
654 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
655 tmp = RREG8(DAC_DATA);
656 tmp &= ~0x10;
657 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
658}
659
660
661void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
662{
663 struct mga_device *mdev = crtc->dev->dev_private;
664 u32 addr;
665 int count;
666
667 while (RREG8(0x1fda) & 0x08);
668 while (!(RREG8(0x1fda) & 0x08));
669
670 count = RREG8(MGAREG_VCOUNT) + 2;
671 while (RREG8(MGAREG_VCOUNT) < count);
672
673 addr = offset >> 2;
674 WREG_CRT(0x0d, (u8)(addr & 0xff));
675 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
676 WREG_CRT(0xaf, (u8)(addr >> 16) & 0xf);
677}
678
679
680/* ast is different - we will force move buffers out of VRAM */
681static int mga_crtc_do_set_base(struct drm_crtc *crtc,
682 struct drm_framebuffer *fb,
683 int x, int y, int atomic)
684{
685 struct mga_device *mdev = crtc->dev->dev_private;
686 struct drm_gem_object *obj;
687 struct mga_framebuffer *mga_fb;
688 struct mgag200_bo *bo;
689 int ret;
690 u64 gpu_addr;
691
692 /* push the previous fb to system ram */
693 if (!atomic && fb) {
694 mga_fb = to_mga_framebuffer(fb);
695 obj = mga_fb->obj;
696 bo = gem_to_mga_bo(obj);
697 ret = mgag200_bo_reserve(bo, false);
698 if (ret)
699 return ret;
700 mgag200_bo_push_sysram(bo);
701 mgag200_bo_unreserve(bo);
702 }
703
704 mga_fb = to_mga_framebuffer(crtc->fb);
705 obj = mga_fb->obj;
706 bo = gem_to_mga_bo(obj);
707
708 ret = mgag200_bo_reserve(bo, false);
709 if (ret)
710 return ret;
711
712 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
713 if (ret) {
714 mgag200_bo_unreserve(bo);
715 return ret;
716 }
717
718 if (&mdev->mfbdev->mfb == mga_fb) {
719 /* if pushing console in kmap it */
720 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
721 if (ret)
722 DRM_ERROR("failed to kmap fbcon\n");
723
724 }
725 mgag200_bo_unreserve(bo);
726
727 DRM_INFO("mga base %llx\n", gpu_addr);
728
729 mga_set_start_address(crtc, (u32)gpu_addr);
730
731 return 0;
732}
733
734static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
735 struct drm_framebuffer *old_fb)
736{
737 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
738}
739
740static int mga_crtc_mode_set(struct drm_crtc *crtc,
741 struct drm_display_mode *mode,
742 struct drm_display_mode *adjusted_mode,
743 int x, int y, struct drm_framebuffer *old_fb)
744{
745 struct drm_device *dev = crtc->dev;
746 struct mga_device *mdev = dev->dev_private;
747 int hdisplay, hsyncstart, hsyncend, htotal;
748 int vdisplay, vsyncstart, vsyncend, vtotal;
749 int pitch;
750 int option = 0, option2 = 0;
751 int i;
752 unsigned char misc = 0;
753 unsigned char ext_vga[6];
754 unsigned char ext_vga_index24;
755 unsigned char dac_index90 = 0;
756 u8 bppshift;
757
758 static unsigned char dacvalue[] = {
759 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
760 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
761 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
762 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
763 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
765 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
766 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
767 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
768 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
769 };
770
771 bppshift = mdev->bpp_shifts[(crtc->fb->bits_per_pixel >> 3) - 1];
772
773 switch (mdev->type) {
774 case G200_SE_A:
775 case G200_SE_B:
776 dacvalue[MGA1064_VREF_CTL] = 0x03;
777 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
778 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
779 MGA1064_MISC_CTL_VGA8 |
780 MGA1064_MISC_CTL_DAC_RAM_CS;
781 if (mdev->has_sdram)
782 option = 0x40049120;
783 else
784 option = 0x4004d120;
785 option2 = 0x00008000;
786 break;
787 case G200_WB:
788 dacvalue[MGA1064_VREF_CTL] = 0x07;
789 option = 0x41049120;
790 option2 = 0x0000b000;
791 break;
792 case G200_EV:
793 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
794 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
795 MGA1064_MISC_CTL_DAC_RAM_CS;
796 option = 0x00000120;
797 option2 = 0x0000b000;
798 break;
799 case G200_EH:
800 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
801 MGA1064_MISC_CTL_DAC_RAM_CS;
802 option = 0x00000120;
803 option2 = 0x0000b000;
804 break;
805 case G200_ER:
806 dac_index90 = 0;
807 break;
808 }
809
810 switch (crtc->fb->bits_per_pixel) {
811 case 8:
812 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
813 break;
814 case 16:
815 if (crtc->fb->depth == 15)
816 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
817 else
818 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
819 break;
820 case 24:
821 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
822 break;
823 case 32:
824 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
825 break;
826 }
827
828 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
829 misc |= 0x40;
830 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
831 misc |= 0x80;
832
833
834 for (i = 0; i < sizeof(dacvalue); i++) {
9d8aa55f 835 if ((i <= 0x17) ||
414c4531
DA		 836 (i == 0x1b) ||
837 (i == 0x1c) ||
838 ((i >= 0x1f) && (i <= 0x29)) ||
839 ((i >= 0x30) && (i <= 0x37)))
840 continue;
841 if (IS_G200_SE(mdev) &&
842 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
843 continue;
844 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
845 (i >= 0x44) && (i <= 0x4e))
846 continue;
847
848 WREG_DAC(i, dacvalue[i]);
849 }
850
851 if (mdev->type == G200_ER) {
852 WREG_DAC(0x90, dac_index90);
853 }
854
855
856 if (option)
857 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
858 if (option2)
859 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
860
861 WREG_SEQ(2, 0xf);
862 WREG_SEQ(3, 0);
863 WREG_SEQ(4, 0xe);
864
865 pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8);
866 if (crtc->fb->bits_per_pixel == 24)
867 pitch = pitch >> (4 - bppshift);
868 else
869 pitch = pitch >> (4 - bppshift);
870
871 hdisplay = mode->hdisplay / 8 - 1;
872 hsyncstart = mode->hsync_start / 8 - 1;
873 hsyncend = mode->hsync_end / 8 - 1;
874 htotal = mode->htotal / 8 - 1;
875
876 /* Work around hardware quirk */
877 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
878 htotal++;
879
880 vdisplay = mode->vdisplay - 1;
881 vsyncstart = mode->vsync_start - 1;
882 vsyncend = mode->vsync_end - 1;
883 vtotal = mode->vtotal - 2;
884
885 WREG_GFX(0, 0);
886 WREG_GFX(1, 0);
887 WREG_GFX(2, 0);
888 WREG_GFX(3, 0);
889 WREG_GFX(4, 0);
890 WREG_GFX(5, 0x40);
891 WREG_GFX(6, 0x5);
892 WREG_GFX(7, 0xf);
893 WREG_GFX(8, 0xf);
894
895 WREG_CRT(0, htotal - 4);
896 WREG_CRT(1, hdisplay);
897 WREG_CRT(2, hdisplay);
898 WREG_CRT(3, (htotal & 0x1F) | 0x80);
899 WREG_CRT(4, hsyncstart);
900 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
901 WREG_CRT(6, vtotal & 0xFF);
902 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
903 ((vdisplay & 0x100) >> 7) |
904 ((vsyncstart & 0x100) >> 6) |
905 ((vdisplay & 0x100) >> 5) |
906 ((vdisplay & 0x100) >> 4) | /* linecomp */
907 ((vtotal & 0x200) >> 4)|
908 ((vdisplay & 0x200) >> 3) |
909 ((vsyncstart & 0x200) >> 2));
910 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
911 ((vdisplay & 0x200) >> 3));
912 WREG_CRT(10, 0);
913 WREG_CRT(11, 0);
914 WREG_CRT(12, 0);
915 WREG_CRT(13, 0);
916 WREG_CRT(14, 0);
917 WREG_CRT(15, 0);
918 WREG_CRT(16, vsyncstart & 0xFF);
919 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
920 WREG_CRT(18, vdisplay & 0xFF);
921 WREG_CRT(19, pitch & 0xFF);
922 WREG_CRT(20, 0);
923 WREG_CRT(21, vdisplay & 0xFF);
924 WREG_CRT(22, (vtotal + 1) & 0xFF);
925 WREG_CRT(23, 0xc3);
926 WREG_CRT(24, vdisplay & 0xFF);
927
928 ext_vga[0] = 0;
929 ext_vga[5] = 0;
930
931 /* TODO interlace */
932
933 ext_vga[0] |= (pitch & 0x300) >> 4;
934 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
935 ((hdisplay & 0x100) >> 7) |
936 ((hsyncstart & 0x100) >> 6) |
937 (htotal & 0x40);
938 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
939 ((vdisplay & 0x400) >> 8) |
940 ((vdisplay & 0xc00) >> 7) |
941 ((vsyncstart & 0xc00) >> 5) |
942 ((vdisplay & 0x400) >> 3);
943 if (crtc->fb->bits_per_pixel == 24)
944 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
945 else
946 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
947 ext_vga[4] = 0;
948 if (mdev->type == G200_WB)
949 ext_vga[1] |= 0x88;
950
951 ext_vga_index24 = 0x05;
952
953 /* Set pixel clocks */
954 misc = 0x2d;
955 WREG8(MGA_MISC_OUT, misc);
956
957 mga_crtc_set_plls(mdev, mode->clock);
958
959 for (i = 0; i < 6; i++) {
960 WREG_ECRT(i, ext_vga[i]);
961 }
962
963 if (mdev->type == G200_ER)
964 WREG_ECRT(24, ext_vga_index24);
965
966 if (mdev->type == G200_EV) {
967 WREG_ECRT(6, 0);
968 }
969
970 WREG_ECRT(0, ext_vga[0]);
971 /* Enable mga pixel clock */
972 misc = 0x2d;
973
974 WREG8(MGA_MISC_OUT, misc);
975
976 if (adjusted_mode)
977 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
978
979 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
980
981 /* reset tagfifo */
982 if (mdev->type == G200_ER) {
983 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
984 u8 seq1;
985
986 /* screen off */
987 WREG8(MGAREG_SEQ_INDEX, 0x01);
988 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
989 WREG8(MGAREG_SEQ_DATA, seq1);
990
991 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
992 udelay(1000);
993 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
994
995 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
996 }
997
998
999 if (IS_G200_SE(mdev)) {
1000 if (mdev->reg_1e24 >= 0x02) {
1001 u8 hi_pri_lvl;
1002 u32 bpp;
1003 u32 mb;
1004
1005 if (crtc->fb->bits_per_pixel > 16)
1006 bpp = 32;
1007 else if (crtc->fb->bits_per_pixel > 8)
1008 bpp = 16;
1009 else
1010 bpp = 8;
1011
1012 mb = (mode->clock * bpp) / 1000;
1013 if (mb > 3100)
1014 hi_pri_lvl = 0;
1015 else if (mb > 2600)
1016 hi_pri_lvl = 1;
1017 else if (mb > 1900)
1018 hi_pri_lvl = 2;
1019 else if (mb > 1160)
1020 hi_pri_lvl = 3;
1021 else if (mb > 440)
1022 hi_pri_lvl = 4;
1023 else
1024 hi_pri_lvl = 5;
1025
1026 WREG8(0x1fde, 0x06);
1027 WREG8(0x1fdf, hi_pri_lvl);
1028 } else {
1029 if (mdev->reg_1e24 >= 0x01)
1030 WREG8(0x1fdf, 0x03);
1031 else
1032 WREG8(0x1fdf, 0x04);
1033 }
1034 }
1035 return 0;
1036}
1037
1038#if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1039static int mga_suspend(struct drm_crtc *crtc)
1040{
1041 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1042 struct drm_device *dev = crtc->dev;
1043 struct mga_device *mdev = dev->dev_private;
1044 struct pci_dev *pdev = dev->pdev;
1045 int option;
1046
1047 if (mdev->suspended)
1048 return 0;
1049
1050 WREG_SEQ(1, 0x20);
1051 WREG_ECRT(1, 0x30);
1052 /* Disable the pixel clock */
1053 WREG_DAC(0x1a, 0x05);
1054 /* Power down the DAC */
1055 WREG_DAC(0x1e, 0x18);
1056 /* Power down the pixel PLL */
1057 WREG_DAC(0x1a, 0x0d);
1058
1059 /* Disable PLLs and clocks */
1060 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1061 option &= ~(0x1F8024);
1062 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1063 pci_set_power_state(pdev, PCI_D3hot);
1064 pci_disable_device(pdev);
1065
1066 mdev->suspended = true;
1067
1068 return 0;
1069}
1070
1071static int mga_resume(struct drm_crtc *crtc)
1072{
1073 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1074 struct drm_device *dev = crtc->dev;
1075 struct mga_device *mdev = dev->dev_private;
1076 struct pci_dev *pdev = dev->pdev;
1077 int option;
1078
1079 if (!mdev->suspended)
1080 return 0;
1081
1082 pci_set_power_state(pdev, PCI_D0);
1083 pci_enable_device(pdev);
1084
1085 /* Disable sysclk */
1086 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1087 option &= ~(0x4);
1088 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1089
1090 mdev->suspended = false;
1091
1092 return 0;
1093}
1094
1095#endif
1096
1097static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1098{
1099 struct drm_device *dev = crtc->dev;
1100 struct mga_device *mdev = dev->dev_private;
1101 u8 seq1 = 0, crtcext1 = 0;
1102
1103 switch (mode) {
1104 case DRM_MODE_DPMS_ON:
1105 seq1 = 0;
1106 crtcext1 = 0;
1107 mga_crtc_load_lut(crtc);
1108 break;
1109 case DRM_MODE_DPMS_STANDBY:
1110 seq1 = 0x20;
1111 crtcext1 = 0x10;
1112 break;
1113 case DRM_MODE_DPMS_SUSPEND:
1114 seq1 = 0x20;
1115 crtcext1 = 0x20;
1116 break;
1117 case DRM_MODE_DPMS_OFF:
1118 seq1 = 0x20;
1119 crtcext1 = 0x30;
1120 break;
1121 }
1122
1123#if 0
1124 if (mode == DRM_MODE_DPMS_OFF) {
1125 mga_suspend(crtc);
1126 }
1127#endif
1128 WREG8(MGAREG_SEQ_INDEX, 0x01);
1129 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1130 mga_wait_vsync(mdev);
1131 mga_wait_busy(mdev);
1132 WREG8(MGAREG_SEQ_DATA, seq1);
1133 msleep(20);
1134 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1135 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1136 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1137
1138#if 0
1139 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1140 mga_resume(crtc);
1141 drm_helper_resume_force_mode(dev);
1142 }
1143#endif
1144}
1145
1146/*
1147 * This is called before a mode is programmed. A typical use might be to
1148 * enable DPMS during the programming to avoid seeing intermediate stages,
1149 * but that's not relevant to us
1150 */
1151static void mga_crtc_prepare(struct drm_crtc *crtc)
1152{
1153 struct drm_device *dev = crtc->dev;
1154 struct mga_device *mdev = dev->dev_private;
1155 u8 tmp;
1156
1157 /* mga_resume(crtc);*/
1158
1159 WREG8(MGAREG_CRTC_INDEX, 0x11);
1160 tmp = RREG8(MGAREG_CRTC_DATA);
1161 WREG_CRT(0x11, tmp | 0x80);
1162
1163 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1164 WREG_SEQ(0, 1);
1165 msleep(50);
1166 WREG_SEQ(1, 0x20);
1167 msleep(20);
1168 } else {
1169 WREG8(MGAREG_SEQ_INDEX, 0x1);
1170 tmp = RREG8(MGAREG_SEQ_DATA);
1171
1172 /* start sync reset */
1173 WREG_SEQ(0, 1);
1174 WREG_SEQ(1, tmp | 0x20);
1175 }
1176
1177 if (mdev->type == G200_WB)
1178 mga_g200wb_prepare(crtc);
1179
1180 WREG_CRT(17, 0);
1181}
1182
1183/*
1184 * This is called after a mode is programmed. It should reverse anything done
1185 * by the prepare function
1186 */
1187static void mga_crtc_commit(struct drm_crtc *crtc)
1188{
1189 struct drm_device *dev = crtc->dev;
1190 struct mga_device *mdev = dev->dev_private;
1191 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1192 u8 tmp;
1193
1194 if (mdev->type == G200_WB)
1195 mga_g200wb_commit(crtc);
1196
1197 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1198 msleep(50);
1199 WREG_SEQ(1, 0x0);
1200 msleep(20);
1201 WREG_SEQ(0, 0x3);
1202 } else {
1203 WREG8(MGAREG_SEQ_INDEX, 0x1);
1204 tmp = RREG8(MGAREG_SEQ_DATA);
1205
1206 tmp &= ~0x20;
1207 WREG_SEQ(0x1, tmp);
1208 WREG_SEQ(0, 3);
1209 }
1210 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1211}
1212
1213/*
1214 * The core can pass us a set of gamma values to program. We actually only
1215 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1216 * but it's a requirement that we provide the function
1217 */
1218static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1219 u16 *blue, uint32_t start, uint32_t size)
1220{
1221 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1222 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1223 int i;
1224
1225 for (i = start; i < end; i++) {
1226 mga_crtc->lut_r[i] = red[i] >> 8;
1227 mga_crtc->lut_g[i] = green[i] >> 8;
1228 mga_crtc->lut_b[i] = blue[i] >> 8;
1229 }
1230 mga_crtc_load_lut(crtc);
1231}
1232
1233/* Simple cleanup function */
1234static void mga_crtc_destroy(struct drm_crtc *crtc)
1235{
1236 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1237
1238 drm_crtc_cleanup(crtc);
1239 kfree(mga_crtc);
1240}
1241
1242/* These provide the minimum set of functions required to handle a CRTC */
1243static const struct drm_crtc_funcs mga_crtc_funcs = {
1244 .gamma_set = mga_crtc_gamma_set,
1245 .set_config = drm_crtc_helper_set_config,
1246 .destroy = mga_crtc_destroy,
1247};
1248
1249static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1250 .dpms = mga_crtc_dpms,
1251 .mode_fixup = mga_crtc_mode_fixup,
1252 .mode_set = mga_crtc_mode_set,
1253 .mode_set_base = mga_crtc_mode_set_base,
1254 .prepare = mga_crtc_prepare,
1255 .commit = mga_crtc_commit,
1256 .load_lut = mga_crtc_load_lut,
1257};
1258
1259/* CRTC setup */
f1998fe2 1260static void mga_crtc_init(struct mga_device *mdev)
414c4531 1261{
414c4531
DA		 1262 struct mga_crtc *mga_crtc;
1263 int i;
1264
1265 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1266 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1267 GFP_KERNEL);
1268
1269 if (mga_crtc == NULL)
1270 return;
1271
f1998fe2 1272 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
414c4531
DA		 1273
1274 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1275 mdev->mode_info.crtc = mga_crtc;
1276
1277 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1278 mga_crtc->lut_r[i] = i;
1279 mga_crtc->lut_g[i] = i;
1280 mga_crtc->lut_b[i] = i;
1281 }
1282
1283 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1284}
1285
1286/** Sets the color ramps on behalf of fbcon */
1287void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1288 u16 blue, int regno)
1289{
1290 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1291
1292 mga_crtc->lut_r[regno] = red >> 8;
1293 mga_crtc->lut_g[regno] = green >> 8;
1294 mga_crtc->lut_b[regno] = blue >> 8;
1295}
1296
1297/** Gets the color ramps on behalf of fbcon */
1298void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1299 u16 *blue, int regno)
1300{
1301 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1302
1303 *red = (u16)mga_crtc->lut_r[regno] << 8;
1304 *green = (u16)mga_crtc->lut_g[regno] << 8;
1305 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1306}
1307
1308/*
1309 * The encoder comes after the CRTC in the output pipeline, but before
1310 * the connector. It's responsible for ensuring that the digital
1311 * stream is appropriately converted into the output format. Setup is
1312 * very simple in this case - all we have to do is inform qemu of the
1313 * colour depth in order to ensure that it displays appropriately
1314 */
1315
1316/*
1317 * These functions are analagous to those in the CRTC code, but are intended
1318 * to handle any encoder-specific limitations
1319 */
1320static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
e811f5ae
LP		 1321 const struct drm_display_mode *mode,
1322 struct drm_display_mode *adjusted_mode)
414c4531
DA		 1323{
1324 return true;
1325}
1326
1327static void mga_encoder_mode_set(struct drm_encoder *encoder,
1328 struct drm_display_mode *mode,
1329 struct drm_display_mode *adjusted_mode)
1330{
1331
1332}
1333
1334static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1335{
1336 return;
1337}
1338
1339static void mga_encoder_prepare(struct drm_encoder *encoder)
1340{
1341}
1342
1343static void mga_encoder_commit(struct drm_encoder *encoder)
1344{
1345}
1346
1347void mga_encoder_destroy(struct drm_encoder *encoder)
1348{
1349 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1350 drm_encoder_cleanup(encoder);
1351 kfree(mga_encoder);
1352}
1353
1354static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1355 .dpms = mga_encoder_dpms,
1356 .mode_fixup = mga_encoder_mode_fixup,
1357 .mode_set = mga_encoder_mode_set,
1358 .prepare = mga_encoder_prepare,
1359 .commit = mga_encoder_commit,
1360};
1361
1362static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1363 .destroy = mga_encoder_destroy,
1364};
1365
1366static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1367{
1368 struct drm_encoder *encoder;
1369 struct mga_encoder *mga_encoder;
1370
1371 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1372 if (!mga_encoder)
1373 return NULL;
1374
1375 encoder = &mga_encoder->base;
1376 encoder->possible_crtcs = 0x1;
1377
1378 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1379 DRM_MODE_ENCODER_DAC);
1380 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1381
1382 return encoder;
1383}
1384
1385
1386static int mga_vga_get_modes(struct drm_connector *connector)
1387{
1388 struct mga_connector *mga_connector = to_mga_connector(connector);
1389 struct edid *edid;
1390 int ret = 0;
1391
1392 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1393 if (edid) {
1394 drm_mode_connector_update_edid_property(connector, edid);
1395 ret = drm_add_edid_modes(connector, edid);
414c4531
DA		 1396 kfree(edid);
1397 }
1398 return ret;
1399}
1400
1401static int mga_vga_mode_valid(struct drm_connector *connector,
1402 struct drm_display_mode *mode)
1403{
0ba53171
CH		 1404 struct drm_device *dev = connector->dev;
1405 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1406 struct mga_fbdev *mfbdev = mdev->mfbdev;
1407 struct drm_fb_helper *fb_helper = &mfbdev->helper;
1408 struct drm_fb_helper_connector *fb_helper_conn = NULL;
1409 int bpp = 32;
1410 int i = 0;
1411
414c4531
DA		 1412 /* FIXME: Add bandwidth and g200se limitations */
1413
1414 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1415 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1416 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1417 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1418 return MODE_BAD;
1419 }
1420
0ba53171
CH		 1421 /* Validate the mode input by the user */
1422 for (i = 0; i < fb_helper->connector_count; i++) {
1423 if (fb_helper->connector_info[i]->connector == connector) {
1424 /* Found the helper for this connector */
1425 fb_helper_conn = fb_helper->connector_info[i];
1426 if (fb_helper_conn->cmdline_mode.specified) {
1427 if (fb_helper_conn->cmdline_mode.bpp_specified) {
1428 bpp = fb_helper_conn->cmdline_mode.bpp;
1429 }
1430 }
1431 }
1432 }
1433
1434 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1435 if (fb_helper_conn)
1436 fb_helper_conn->cmdline_mode.specified = false;
1437 return MODE_BAD;
1438 }
1439
414c4531
DA		 1440 return MODE_OK;
1441}
1442
1443struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1444 *connector)
1445{
1446 int enc_id = connector->encoder_ids[0];
1447 struct drm_mode_object *obj;
1448 struct drm_encoder *encoder;
1449
1450 /* pick the encoder ids */
1451 if (enc_id) {
1452 obj =
1453 drm_mode_object_find(connector->dev, enc_id,
1454 DRM_MODE_OBJECT_ENCODER);
1455 if (!obj)
1456 return NULL;
1457 encoder = obj_to_encoder(obj);
1458 return encoder;
1459 }
1460 return NULL;
1461}
1462
1463static enum drm_connector_status mga_vga_detect(struct drm_connector
1464 *connector, bool force)
1465{
1466 return connector_status_connected;
1467}
1468
1469static void mga_connector_destroy(struct drm_connector *connector)
1470{
1471 struct mga_connector *mga_connector = to_mga_connector(connector);
1472 mgag200_i2c_destroy(mga_connector->i2c);
1473 drm_connector_cleanup(connector);
1474 kfree(connector);
1475}
1476
1477struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1478 .get_modes = mga_vga_get_modes,
1479 .mode_valid = mga_vga_mode_valid,
1480 .best_encoder = mga_connector_best_encoder,
1481};
1482
1483struct drm_connector_funcs mga_vga_connector_funcs = {
1484 .dpms = drm_helper_connector_dpms,
1485 .detect = mga_vga_detect,
1486 .fill_modes = drm_helper_probe_single_connector_modes,
1487 .destroy = mga_connector_destroy,
1488};
1489
1490static struct drm_connector *mga_vga_init(struct drm_device *dev)
1491{
1492 struct drm_connector *connector;
1493 struct mga_connector *mga_connector;
1494
1495 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1496 if (!mga_connector)
1497 return NULL;
1498
1499 connector = &mga_connector->base;
1500
1501 drm_connector_init(dev, connector,
1502 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1503
1504 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1505
1506 mga_connector->i2c = mgag200_i2c_create(dev);
1507 if (!mga_connector->i2c)
1508 DRM_ERROR("failed to add ddc bus\n");
1509
1510 return connector;
1511}
1512
1513
1514int mgag200_modeset_init(struct mga_device *mdev)
1515{
1516 struct drm_encoder *encoder;
1517 struct drm_connector *connector;
1518 int ret;
1519
1520 mdev->mode_info.mode_config_initialized = true;
1521
1522 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1523 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1524
1525 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1526
f1998fe2 1527 mga_crtc_init(mdev);
414c4531
DA		 1528
1529 encoder = mga_encoder_init(mdev->dev);
1530 if (!encoder) {
1531 DRM_ERROR("mga_encoder_init failed\n");
1532 return -1;
1533 }
1534
1535 connector = mga_vga_init(mdev->dev);
1536 if (!connector) {
1537 DRM_ERROR("mga_vga_init failed\n");
1538 return -1;
1539 }
1540
1541 drm_mode_connector_attach_encoder(connector, encoder);
1542
1543 ret = mgag200_fbdev_init(mdev);
1544 if (ret) {
1545 DRM_ERROR("mga_fbdev_init failed\n");
1546 return ret;
1547 }
1548
1549 return 0;
1550}
1551
1552void mgag200_modeset_fini(struct mga_device *mdev)
1553{
1554
1555}
Linux kernel - Deliverables
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