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drm/msm: mdp4_format -> mdp_format
[deliverable/linux.git] / drivers / gpu / drm / msm / mdp / mdp4 / mdp4_kms.h
CommitLineData
c8afe684
RC		 1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MDP4_KMS_H__
19#define __MDP4_KMS_H__
20
c8afe684 21#include "msm_drv.h"
10a02eb6 22#include "mdp/mdp_kms.h"
c8afe684
RC		 23#include "mdp4.xml.h"
24
25
26/* For transiently registering for different MDP4 irqs that various parts
27 * of the KMS code need during setup/configuration. We these are not
28 * necessarily the same as what drm_vblank_get/put() are requesting, and
29 * the hysteresis in drm_vblank_put() is not necessarily desirable for
30 * internal housekeeping related irq usage.
31 */
32struct mdp4_irq {
33 struct list_head node;
34 uint32_t irqmask;
35 bool registered;
36 void (*irq)(struct mdp4_irq *irq, uint32_t irqstatus);
37};
38
39struct mdp4_kms {
40 struct msm_kms base;
41
42 struct drm_device *dev;
43
44 int rev;
45
46 /* mapper-id used to request GEM buffer mapped for scanout: */
47 int id;
48
49 void __iomem *mmio;
50
51 struct regulator *dsi_pll_vdda;
52 struct regulator *dsi_pll_vddio;
53 struct regulator *vdd;
54
55 struct clk *clk;
56 struct clk *pclk;
57 struct clk *lut_clk;
58
59 /* irq handling: */
60 bool in_irq;
61 struct list_head irq_list; /* list of mdp4_irq */
62 uint32_t vblank_mask; /* irq bits set for userspace vblank */
63 struct mdp4_irq error_handler;
64};
65#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
66
67/* platform config data (ie. from DT, or pdata) */
68struct mdp4_platform_config {
69 struct iommu_domain *iommu;
70 uint32_t max_clk;
71};
72
c8afe684
RC		 73static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
74{
75 msm_writel(data, mdp4_kms->mmio + reg);
76}
77
78static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
79{
80 return msm_readl(mdp4_kms->mmio + reg);
81}
82
22ba8b6b 83static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
c8afe684
RC		 84{
85 switch (pipe) {
86 case VG1: return MDP4_OVERLAY_FLUSH_VG1;
87 case VG2: return MDP4_OVERLAY_FLUSH_VG2;
88 case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
89 case RGB2: return MDP4_OVERLAY_FLUSH_RGB1;
90 default: return 0;
91 }
92}
93
94static inline uint32_t ovlp2flush(int ovlp)
95{
96 switch (ovlp) {
97 case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
98 case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
99 default: return 0;
100 }
101}
102
103static inline uint32_t dma2irq(enum mdp4_dma dma)
104{
105 switch (dma) {
106 case DMA_P: return MDP4_IRQ_DMA_P_DONE;
107 case DMA_S: return MDP4_IRQ_DMA_S_DONE;
108 case DMA_E: return MDP4_IRQ_DMA_E_DONE;
109 default: return 0;
110 }
111}
112
113static inline uint32_t dma2err(enum mdp4_dma dma)
114{
115 switch (dma) {
116 case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
117 case DMA_S: return 0; // ???
118 case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
119 default: return 0;
120 }
121}
122
a8623918 123static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
facb4f4e 124 enum mdp_mixer_stage_id stage)
a8623918
RC		 125{
126 uint32_t mixer_cfg = 0;
127
128 switch (pipe) {
129 case VG1:
130 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
131 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
132 break;
133 case VG2:
134 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
135 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
136 break;
137 case RGB1:
138 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
139 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
140 break;
141 case RGB2:
142 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
143 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
144 break;
145 case RGB3:
146 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
147 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
148 break;
149 case VG3:
150 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
151 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
152 break;
153 case VG4:
154 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
155 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
156 break;
157 default:
158 WARN_ON("invalid pipe");
159 break;
160 }
161
162 return mixer_cfg;
163}
164
c8afe684
RC		 165int mdp4_disable(struct mdp4_kms *mdp4_kms);
166int mdp4_enable(struct mdp4_kms *mdp4_kms);
167
168void mdp4_irq_preinstall(struct msm_kms *kms);
169int mdp4_irq_postinstall(struct msm_kms *kms);
170void mdp4_irq_uninstall(struct msm_kms *kms);
171irqreturn_t mdp4_irq(struct msm_kms *kms);
172void mdp4_irq_wait(struct mdp4_kms *mdp4_kms, uint32_t irqmask);
173void mdp4_irq_register(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
174void mdp4_irq_unregister(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
175int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
176void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
177
10a02eb6
RC		 178static inline
179uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
180 uint32_t max_formats)
181{
182 /* TODO when we have YUV, we need to filter supported formats
183 * based on pipe_id..
184 */
185 return mdp_get_formats(pixel_formats, max_formats);
186}
c8afe684
RC		 187
188void mdp4_plane_install_properties(struct drm_plane *plane,
189 struct drm_mode_object *obj);
190void mdp4_plane_set_scanout(struct drm_plane *plane,
191 struct drm_framebuffer *fb);
192int mdp4_plane_mode_set(struct drm_plane *plane,
193 struct drm_crtc *crtc, struct drm_framebuffer *fb,
194 int crtc_x, int crtc_y,
195 unsigned int crtc_w, unsigned int crtc_h,
196 uint32_t src_x, uint32_t src_y,
197 uint32_t src_w, uint32_t src_h);
22ba8b6b 198enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
c8afe684 199struct drm_plane *mdp4_plane_init(struct drm_device *dev,
22ba8b6b 200 enum mdp4_pipe pipe_id, bool private_plane);
c8afe684
RC		 201
202uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
2a2b8fa6 203void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
c8afe684
RC		 204void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
205void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
a8623918
RC		 206void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
207void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
c8afe684
RC		 208struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
209 struct drm_plane *plane, int id, int ovlp_id,
210 enum mdp4_dma dma_id);
211
212long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
213struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
214
215#ifdef CONFIG_MSM_BUS_SCALING
216static inline int match_dev_name(struct device *dev, void *data)
217{
218 return !strcmp(dev_name(dev), data);
219}
220/* bus scaling data is associated with extra pointless platform devices,
221 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
222 * to find their pdata to make the bus-scaling stuff work.
223 */
224static inline void *mdp4_find_pdata(const char *devname)
225{
226 struct device *dev;
227 dev = bus_find_device(&platform_bus_type, NULL,
228 (void *)devname, match_dev_name);
229 return dev ? dev->platform_data : NULL;
230}
231#endif
232
233#endif /* __MDP4_KMS_H__ */
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