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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5.xml.h
CommitLineData
facb4f4e
RC		 1#ifndef MDP5_XML
2#define MDP5_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
8a4247d6
SV		 11- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 27229 bytes, from 2015-02-10 17:00:41)
12- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15)
13- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-01-23 16:20:19)
facb4f4e 14
8a264743 15Copyright (C) 2013-2015 by the following authors:
facb4f4e
RC		 16- Rob Clark <robdclark@gmail.com> (robclark)
17
18Permission is hereby granted, free of charge, to any person obtaining
19a copy of this software and associated documentation files (the
20"Software"), to deal in the Software without restriction, including
21without limitation the rights to use, copy, modify, merge, publish,
22distribute, sublicense, and/or sell copies of the Software, and to
23permit persons to whom the Software is furnished to do so, subject to
24the following conditions:
25
26The above copyright notice and this permission notice (including the
27next paragraph) shall be included in all copies or substantial
28portions of the Software.
29
30THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
31EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
32MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
33IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
34LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
35OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
36WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
37*/
38
39
40enum mdp5_intf {
41 INTF_DSI = 1,
42 INTF_HDMI = 3,
43 INTF_LCDC = 5,
44 INTF_eDP = 9,
45};
46
47enum mdp5_intfnum {
48 NO_INTF = 0,
49 INTF0 = 1,
50 INTF1 = 2,
51 INTF2 = 3,
52 INTF3 = 4,
53};
54
55enum mdp5_pipe {
56 SSPP_VIG0 = 0,
57 SSPP_VIG1 = 1,
58 SSPP_VIG2 = 2,
59 SSPP_RGB0 = 3,
60 SSPP_RGB1 = 4,
61 SSPP_RGB2 = 5,
62 SSPP_DMA0 = 6,
63 SSPP_DMA1 = 7,
3d47fd47
SV		 64 SSPP_VIG3 = 8,
65 SSPP_RGB3 = 9,
facb4f4e
RC		 66};
67
68enum mdp5_ctl_mode {
69 MODE_NONE = 0,
70 MODE_ROT0 = 1,
71 MODE_ROT1 = 2,
72 MODE_WB0 = 3,
73 MODE_WB1 = 4,
74 MODE_WFD = 5,
75};
76
77enum mdp5_pack_3d {
78 PACK_3D_FRAME_INT = 0,
79 PACK_3D_H_ROW_INT = 1,
80 PACK_3D_V_ROW_INT = 2,
81 PACK_3D_COL_INT = 3,
82};
83
facb4f4e
RC		 84enum mdp5_scale_filter {
85 SCALE_FILTER_NEAREST = 0,
86 SCALE_FILTER_BIL = 1,
87 SCALE_FILTER_PCMN = 2,
88 SCALE_FILTER_CA = 3,
89};
90
91enum mdp5_pipe_bwc {
92 BWC_LOSSLESS = 0,
93 BWC_Q_HIGH = 1,
94 BWC_Q_MED = 2,
95};
96
97enum mdp5_client_id {
98 CID_UNUSED = 0,
99 CID_VIG0_Y = 1,
100 CID_VIG0_CR = 2,
101 CID_VIG0_CB = 3,
102 CID_VIG1_Y = 4,
103 CID_VIG1_CR = 5,
104 CID_VIG1_CB = 6,
105 CID_VIG2_Y = 7,
106 CID_VIG2_CR = 8,
107 CID_VIG2_CB = 9,
108 CID_DMA0_Y = 10,
109 CID_DMA0_CR = 11,
110 CID_DMA0_CB = 12,
111 CID_DMA1_Y = 13,
112 CID_DMA1_CR = 14,
113 CID_DMA1_CB = 15,
114 CID_RGB0 = 16,
115 CID_RGB1 = 17,
116 CID_RGB2 = 18,
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SV		 117 CID_VIG3_Y = 19,
118 CID_VIG3_CR = 20,
119 CID_VIG3_CB = 21,
120 CID_RGB3 = 22,
121 CID_MAX = 23,
facb4f4e
RC		 122};
123
8a264743
RC		 124enum mdp5_cursor_format {
125 CURSOR_FMT_ARGB8888 = 0,
126 CURSOR_FMT_ARGB1555 = 2,
127 CURSOR_FMT_ARGB4444 = 4,
128};
129
130enum mdp5_cursor_alpha {
131 CURSOR_ALPHA_CONST = 0,
132 CURSOR_ALPHA_PER_PIXEL = 2,
133};
134
facb4f4e
RC		 135enum mdp5_igc_type {
136 IGC_VIG = 0,
137 IGC_RGB = 1,
138 IGC_DMA = 2,
139 IGC_DSPP = 3,
140};
141
8a264743
RC		 142enum mdp5_data_format {
143 DATA_FORMAT_RGB = 0,
144 DATA_FORMAT_YUV = 1,
145};
146
facb4f4e
RC		 147#define MDP5_IRQ_INTF0_WB_ROT_COMP 0x00000001
148#define MDP5_IRQ_INTF1_WB_ROT_COMP 0x00000002
149#define MDP5_IRQ_INTF2_WB_ROT_COMP 0x00000004
150#define MDP5_IRQ_INTF3_WB_ROT_COMP 0x00000008
151#define MDP5_IRQ_INTF0_WB_WFD 0x00000010
152#define MDP5_IRQ_INTF1_WB_WFD 0x00000020
153#define MDP5_IRQ_INTF2_WB_WFD 0x00000040
154#define MDP5_IRQ_INTF3_WB_WFD 0x00000080
155#define MDP5_IRQ_INTF0_PING_PONG_COMP 0x00000100
156#define MDP5_IRQ_INTF1_PING_PONG_COMP 0x00000200
157#define MDP5_IRQ_INTF2_PING_PONG_COMP 0x00000400
158#define MDP5_IRQ_INTF3_PING_PONG_COMP 0x00000800
159#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR 0x00001000
160#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR 0x00002000
161#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR 0x00004000
162#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR 0x00008000
163#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR 0x00010000
164#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR 0x00020000
165#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR 0x00040000
166#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR 0x00080000
167#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF 0x00100000
168#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF 0x00200000
169#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF 0x00400000
170#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF 0x00800000
171#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
172#define MDP5_IRQ_INTF0_VSYNC 0x02000000
173#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
174#define MDP5_IRQ_INTF1_VSYNC 0x08000000
175#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
176#define MDP5_IRQ_INTF2_VSYNC 0x20000000
177#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
178#define MDP5_IRQ_INTF3_VSYNC 0x80000000
179#define REG_MDP5_HW_VERSION 0x00000000
180
181#define REG_MDP5_HW_INTR_STATUS 0x00000010
182#define MDP5_HW_INTR_STATUS_INTR_MDP 0x00000001
183#define MDP5_HW_INTR_STATUS_INTR_DSI0 0x00000010
184#define MDP5_HW_INTR_STATUS_INTR_DSI1 0x00000020
185#define MDP5_HW_INTR_STATUS_INTR_HDMI 0x00000100
186#define MDP5_HW_INTR_STATUS_INTR_EDP 0x00001000
187
188#define REG_MDP5_MDP_VERSION 0x00000100
189#define MDP5_MDP_VERSION_MINOR__MASK 0x00ff0000
190#define MDP5_MDP_VERSION_MINOR__SHIFT 16
191static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
192{
193 return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK;
194}
195#define MDP5_MDP_VERSION_MAJOR__MASK 0xf0000000
196#define MDP5_MDP_VERSION_MAJOR__SHIFT 28
197static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val)
198{
199 return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK;
200}
201
202#define REG_MDP5_DISP_INTF_SEL 0x00000104
203#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
204#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
205static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)
206{
207 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
208}
209#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
210#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
211static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)
212{
213 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
214}
215#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
216#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
217static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)
218{
219 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
220}
221#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
222#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
223static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)
224{
225 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
226}
227
228#define REG_MDP5_INTR_EN 0x00000110
229
230#define REG_MDP5_INTR_STATUS 0x00000114
231
232#define REG_MDP5_INTR_CLEAR 0x00000118
233
234#define REG_MDP5_HIST_INTR_EN 0x0000011c
235
236#define REG_MDP5_HIST_INTR_STATUS 0x00000120
237
238#define REG_MDP5_HIST_INTR_CLEAR 0x00000124
239
240static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }
241
242static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; }
243#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
244#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
245static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
246{
247 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
248}
249#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
250#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
251static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
252{
253 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
254}
255#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
256#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
257static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
258{
259 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
260}
261
262static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; }
263
264static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; }
265#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
266#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
267static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
268{
269 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
270}
271#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
272#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
273static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
274{
275 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
276}
277#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
278#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
279static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
280{
281 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
282}
283
284static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
285{
286 switch (idx) {
287 case IGC_VIG: return 0x00000300;
288 case IGC_RGB: return 0x00000310;
289 case IGC_DMA: return 0x00000320;
290 case IGC_DSPP: return 0x00000400;
291 default: return INVALID_IDX(idx);
292 }
293}
294static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
295
296static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
297
298static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
299#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
300#define MDP5_IGC_LUT_REG_VAL__SHIFT 0
301static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
302{
303 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
304}
305#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
306#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
307#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
308#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
309
3d47fd47
SV		 310static inline uint32_t __offset_CTL(uint32_t idx)
311{
312 switch (idx) {
313 case 0: return (mdp5_cfg->ctl.base[0]);
314 case 1: return (mdp5_cfg->ctl.base[1]);
315 case 2: return (mdp5_cfg->ctl.base[2]);
316 case 3: return (mdp5_cfg->ctl.base[3]);
317 case 4: return (mdp5_cfg->ctl.base[4]);
318 default: return INVALID_IDX(idx);
319 }
320}
321static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
facb4f4e 322
3d47fd47
SV		 323static inline uint32_t __offset_LAYER(uint32_t idx)
324{
325 switch (idx) {
326 case 0: return 0x00000000;
327 case 1: return 0x00000004;
328 case 2: return 0x00000008;
329 case 3: return 0x0000000c;
330 case 4: return 0x00000010;
331 case 5: return 0x00000024;
332 default: return INVALID_IDX(idx);
333 }
334}
335static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
facb4f4e 336
3d47fd47 337static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
facb4f4e
RC		 338#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
339#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
340static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
341{
342 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
343}
344#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
345#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
346static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
347{
348 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
349}
350#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
351#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
352static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
353{
354 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
355}
356#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
357#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
358static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
359{
360 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
361}
362#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
363#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
364static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
365{
366 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
367}
368#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
369#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
370static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
371{
372 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
373}
374#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
375#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
376static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
377{
378 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
379}
380#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
381#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
382static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
383{
384 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
385}
386#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
387#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
3d47fd47
SV		 388#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
389#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
390static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
391{
392 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
393}
394#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
395#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
396static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
397{
398 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
399}
facb4f4e 400
3d47fd47 401static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
facb4f4e
RC		 402#define MDP5_CTL_OP_MODE__MASK 0x0000000f
403#define MDP5_CTL_OP_MODE__SHIFT 0
404static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
405{
406 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
407}
408#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
409#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
410static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
411{
412 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
413}
414#define MDP5_CTL_OP_CMD_MODE 0x00020000
415#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
416#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
417#define MDP5_CTL_OP_PACK_3D__SHIFT 20
418static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
419{
420 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
421}
422
3d47fd47 423static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
facb4f4e
RC		 424#define MDP5_CTL_FLUSH_VIG0 0x00000001
425#define MDP5_CTL_FLUSH_VIG1 0x00000002
426#define MDP5_CTL_FLUSH_VIG2 0x00000004
427#define MDP5_CTL_FLUSH_RGB0 0x00000008
428#define MDP5_CTL_FLUSH_RGB1 0x00000010
429#define MDP5_CTL_FLUSH_RGB2 0x00000020
430#define MDP5_CTL_FLUSH_LM0 0x00000040
431#define MDP5_CTL_FLUSH_LM1 0x00000080
432#define MDP5_CTL_FLUSH_LM2 0x00000100
3d47fd47
SV		 433#define MDP5_CTL_FLUSH_LM3 0x00000200
434#define MDP5_CTL_FLUSH_LM4 0x00000400
facb4f4e
RC		 435#define MDP5_CTL_FLUSH_DMA0 0x00000800
436#define MDP5_CTL_FLUSH_DMA1 0x00001000
437#define MDP5_CTL_FLUSH_DSPP0 0x00002000
438#define MDP5_CTL_FLUSH_DSPP1 0x00004000
439#define MDP5_CTL_FLUSH_DSPP2 0x00008000
440#define MDP5_CTL_FLUSH_CTL 0x00020000
3d47fd47
SV		 441#define MDP5_CTL_FLUSH_VIG3 0x00040000
442#define MDP5_CTL_FLUSH_RGB3 0x00080000
443#define MDP5_CTL_FLUSH_LM5 0x00100000
444#define MDP5_CTL_FLUSH_DSPP3 0x00200000
facb4f4e 445
3d47fd47 446static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
facb4f4e 447
3d47fd47 448static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
facb4f4e 449
3d47fd47
SV		 450static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
451{
452 switch (idx) {
453 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
454 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
455 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
456 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
457 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
458 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
459 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
460 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
461 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
462 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
463 default: return INVALID_IDX(idx);
464 }
465}
466static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
facb4f4e 467
8a264743
RC		 468static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
469#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
470#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
471static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
472{
473 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
474}
475#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
476#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
477static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
478{
479 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
480}
481#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
482
3d47fd47 483static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
facb4f4e 484
3d47fd47 485static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
facb4f4e 486
3d47fd47 487static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
facb4f4e 488
8a264743
RC		 489static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
490#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
491#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
492static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
493{
494 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
495}
496#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
497#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
498static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
499{
500 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
501}
502
503static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
504#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
505#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
506static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
507{
508 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
509}
510#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
511#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
512static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
513{
514 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
515}
516
517static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
518#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
519#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
520static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
521{
522 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
523}
524#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
525#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
526static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
527{
528 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
529}
530
531static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
532#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
533#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
534static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
535{
536 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
537}
538#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
539#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
540static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
541{
542 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
543}
544
545static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
546#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
547#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
548static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
549{
550 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
551}
552
553static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
554
555static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
556#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
557#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
558static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
559{
560 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
561}
562#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
563#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
564static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
565{
566 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
567}
568
569static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
570
571static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
572#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
573#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
574static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
575{
576 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
577}
578#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
579#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
580static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
581{
582 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
583}
584
585static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
586
587static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
588#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
589#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
590static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
591{
592 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
593}
594
595static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
596
597static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
598#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
599#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
600static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
601{
602 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
603}
604
3d47fd47 605static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
facb4f4e
RC		 606#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
607#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
608static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
609{
610 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
611}
612#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
613#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
614static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
615{
616 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
617}
618
3d47fd47 619static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
facb4f4e
RC		 620#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
621#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
622static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
623{
624 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
625}
626#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
627#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
628static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
629{
630 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
631}
632
3d47fd47 633static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
facb4f4e
RC		 634#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
635#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
636static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
637{
638 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
639}
640#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
641#define MDP5_PIPE_SRC_XY_X__SHIFT 0
642static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
643{
644 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
645}
646
3d47fd47 647static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
facb4f4e
RC		 648#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
649#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
650static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
651{
652 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
653}
654#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
655#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
656static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
657{
658 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
659}
660
3d47fd47 661static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
facb4f4e
RC		 662#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
663#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
664static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
665{
666 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
667}
668#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
669#define MDP5_PIPE_OUT_XY_X__SHIFT 0
670static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
671{
672 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
673}
674
3d47fd47 675static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
facb4f4e 676
3d47fd47 677static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
facb4f4e 678
3d47fd47 679static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
facb4f4e 680
3d47fd47 681static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
facb4f4e 682
3d47fd47 683static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
facb4f4e
RC		 684#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
685#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
686static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
687{
688 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
689}
690#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
691#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
692static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
693{
694 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
695}
696
3d47fd47 697static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
facb4f4e
RC		 698#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
699#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
700static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
701{
702 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
703}
704#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
705#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
706static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
707{
708 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
709}
710
3d47fd47 711static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
facb4f4e 712
3d47fd47 713static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
facb4f4e
RC		 714#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
715#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
716static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
717{
718 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
719}
720#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
721#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
722static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
723{
724 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
725}
726#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
727#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
728static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
729{
730 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
731}
732#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
733#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
734static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
735{
736 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
737}
738#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
739#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
740#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
741static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
742{
743 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
744}
745#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
746#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
747#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
748static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
749{
750 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
751}
752#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
753#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
8a264743 754#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000
facb4f4e 755#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
8a264743 756static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
facb4f4e
RC		 757{
758 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
759}
760#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
761#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
8a264743 762static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
facb4f4e
RC		 763{
764 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
765}
766
3d47fd47 767static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
facb4f4e
RC		 768#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
769#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
770static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
771{
772 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
773}
774#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
775#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
776static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
777{
778 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
779}
780#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
781#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
782static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
783{
784 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
785}
786#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
787#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
788static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
789{
790 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
791}
792
3d47fd47 793static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
facb4f4e
RC		 794#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
795#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
796#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
797static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
798{
799 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
800}
801#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
802#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
803#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
804#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
805#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
806#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
807#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
808
3d47fd47 809static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
facb4f4e 810
3d47fd47 811static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
facb4f4e 812
3d47fd47 813static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
facb4f4e 814
3d47fd47 815static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
facb4f4e 816
3d47fd47 817static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
facb4f4e 818
3d47fd47 819static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
facb4f4e 820
3d47fd47 821static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
facb4f4e 822
3d47fd47 823static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
facb4f4e 824
3d47fd47 825static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
facb4f4e 826
3d47fd47 827static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
facb4f4e 828
3d47fd47 829static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
facb4f4e 830
3d47fd47 831static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
facb4f4e
RC		 832#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
833#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
834static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
835{
836 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
837}
838#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
839#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
840static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
841{
842 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
843}
844
3d47fd47 845static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
facb4f4e
RC		 846#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
847#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
848#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
849#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
850static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
851{
852 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
853}
854#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
855#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
856static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
857{
858 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
859}
860#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
861#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
862static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
863{
864 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
865}
866#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
867#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
868static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
869{
870 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
871}
872#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
873#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
874static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
875{
876 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
877}
878#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
879#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
880static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
881{
882 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
883}
884
3d47fd47 885static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
facb4f4e 886
3d47fd47 887static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
facb4f4e 888
8a264743
RC		 889static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
890
891static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
892
3d47fd47 893static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
facb4f4e 894
3d47fd47 895static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
facb4f4e 896
3d47fd47
SV		 897static inline uint32_t __offset_LM(uint32_t idx)
898{
899 switch (idx) {
900 case 0: return (mdp5_cfg->lm.base[0]);
901 case 1: return (mdp5_cfg->lm.base[1]);
902 case 2: return (mdp5_cfg->lm.base[2]);
903 case 3: return (mdp5_cfg->lm.base[3]);
904 case 4: return (mdp5_cfg->lm.base[4]);
8a4247d6 905 case 5: return (mdp5_cfg->lm.base[5]);
3d47fd47
SV		 906 default: return INVALID_IDX(idx);
907 }
908}
909static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
facb4f4e 910
3d47fd47 911static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
facb4f4e
RC		 912#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
913#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
914#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
915#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
916
3d47fd47 917static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
facb4f4e
RC		 918#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
919#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
920static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
921{
922 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
923}
924#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
925#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
926static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
927{
928 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
929}
930
3d47fd47 931static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
facb4f4e 932
3d47fd47 933static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
facb4f4e 934
3d47fd47 935static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 936
3d47fd47 937static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
facb4f4e
RC		 938#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
939#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
940static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
941{
942 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
943}
944#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
945#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
946#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
947#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
948#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
949#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
950static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
951{
952 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
953}
954#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
955#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
956#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
957#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
958
3d47fd47 959static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 960
3d47fd47 961static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 962
3d47fd47 963static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
facb4f4e 964
3d47fd47 965static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 966
3d47fd47 967static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 968
3d47fd47 969static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 970
3d47fd47 971static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
facb4f4e 972
3d47fd47 973static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 974
3d47fd47 975static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 976
3d47fd47 977static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
facb4f4e 978
3d47fd47 979static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
8a264743
RC		 980#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
981#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
982static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
983{
984 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
985}
986#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
987#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
988static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
989{
990 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
991}
facb4f4e 992
3d47fd47 993static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
8a264743
RC		 994#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
995#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
996static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
997{
998 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
999}
1000#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1001#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1002static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1003{
1004 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1005}
facb4f4e 1006
3d47fd47 1007static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
8a264743
RC		 1008#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1009#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1010static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1011{
1012 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1013}
1014#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1015#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1016static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1017{
1018 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1019}
facb4f4e 1020
3d47fd47 1021static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
8a264743
RC		 1022#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1023#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1024static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1025{
1026 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1027}
facb4f4e 1028
3d47fd47 1029static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
8a264743
RC		 1030#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1031#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1032static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1033{
1034 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1035}
facb4f4e 1036
3d47fd47 1037static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
facb4f4e 1038
3d47fd47 1039static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
8a264743
RC		 1040#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1041#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1042static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1043{
1044 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1045}
1046#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1047#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1048static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1049{
1050 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1051}
facb4f4e 1052
3d47fd47 1053static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
8a264743
RC		 1054#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1055#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1056#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1057static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1058{
1059 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1060}
1061#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
facb4f4e 1062
3d47fd47 1063static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
facb4f4e 1064
3d47fd47 1065static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
facb4f4e 1066
3d47fd47 1067static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
facb4f4e 1068
3d47fd47 1069static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
facb4f4e 1070
3d47fd47 1071static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
facb4f4e 1072
3d47fd47 1073static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
facb4f4e 1074
3d47fd47
SV		 1075static inline uint32_t __offset_DSPP(uint32_t idx)
1076{
1077 switch (idx) {
1078 case 0: return (mdp5_cfg->dspp.base[0]);
1079 case 1: return (mdp5_cfg->dspp.base[1]);
1080 case 2: return (mdp5_cfg->dspp.base[2]);
1081 case 3: return (mdp5_cfg->dspp.base[3]);
1082 default: return INVALID_IDX(idx);
1083 }
1084}
1085static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
facb4f4e 1086
3d47fd47 1087static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
facb4f4e
RC		 1088#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1089#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1090#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1091static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1092{
1093 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1094}
1095#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1096#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1097#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1098#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1099#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1100#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1101#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1102#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1103
3d47fd47 1104static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
facb4f4e 1105
3d47fd47 1106static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
facb4f4e 1107
3d47fd47 1108static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
facb4f4e 1109
3d47fd47 1110static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
facb4f4e 1111
3d47fd47 1112static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
facb4f4e 1113
3d47fd47 1114static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
facb4f4e 1115
3d47fd47 1116static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
facb4f4e 1117
3d47fd47 1118static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
facb4f4e 1119
3d47fd47
SV		 1120static inline uint32_t __offset_INTF(uint32_t idx)
1121{
1122 switch (idx) {
1123 case 0: return (mdp5_cfg->intf.base[0]);
1124 case 1: return (mdp5_cfg->intf.base[1]);
1125 case 2: return (mdp5_cfg->intf.base[2]);
1126 case 3: return (mdp5_cfg->intf.base[3]);
1127 case 4: return (mdp5_cfg->intf.base[4]);
1128 default: return INVALID_IDX(idx);
1129 }
1130}
1131static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
facb4f4e 1132
3d47fd47 1133static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
facb4f4e 1134
3d47fd47 1135static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
facb4f4e 1136
3d47fd47 1137static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
facb4f4e
RC		 1138#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1139#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1140static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1141{
1142 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1143}
1144#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1145#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1146static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1147{
1148 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1149}
1150
3d47fd47 1151static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
facb4f4e 1152
3d47fd47 1153static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
facb4f4e 1154
3d47fd47 1155static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
facb4f4e 1156
3d47fd47 1157static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
facb4f4e 1158
3d47fd47 1159static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
facb4f4e 1160
3d47fd47 1161static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
facb4f4e 1162
3d47fd47 1163static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
facb4f4e 1164
3d47fd47 1165static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
facb4f4e 1166
3d47fd47 1167static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
facb4f4e
RC		 1168#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1169#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1170static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1171{
1172 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1173}
1174#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1175
3d47fd47 1176static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
facb4f4e
RC		 1177#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1178#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1179static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1180{
1181 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1182}
1183
3d47fd47 1184static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
facb4f4e 1185
3d47fd47 1186static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
facb4f4e 1187
3d47fd47 1188static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
facb4f4e
RC		 1189#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1190#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1191static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1192{
1193 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1194}
1195#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1196#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1197static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1198{
1199 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1200}
1201
3d47fd47 1202static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
facb4f4e
RC		 1203#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1204#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1205static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1206{
1207 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1208}
1209#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1210#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1211static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1212{
1213 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1214}
1215#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1216
3d47fd47 1217static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
facb4f4e 1218
3d47fd47 1219static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
facb4f4e 1220
3d47fd47 1221static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
facb4f4e 1222
3d47fd47 1223static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
facb4f4e
RC		 1224#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1225#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1226#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1227
3d47fd47 1228static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
facb4f4e 1229
3d47fd47 1230static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
facb4f4e 1231
3d47fd47 1232static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
facb4f4e 1233
3d47fd47 1234static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
facb4f4e 1235
3d47fd47 1236static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
facb4f4e 1237
3d47fd47 1238static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
facb4f4e 1239
3d47fd47 1240static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
facb4f4e 1241
3d47fd47 1242static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
facb4f4e 1243
3d47fd47 1244static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
facb4f4e 1245
3d47fd47 1246static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
facb4f4e 1247
3d47fd47 1248static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
facb4f4e 1249
3d47fd47 1250static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
facb4f4e 1251
3d47fd47 1252static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
facb4f4e 1253
3d47fd47 1254static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
facb4f4e 1255
3d47fd47 1256static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
facb4f4e 1257
3d47fd47 1258static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
facb4f4e 1259
3d47fd47 1260static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
facb4f4e 1261
3d47fd47 1262static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
facb4f4e 1263
3d47fd47 1264static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
facb4f4e 1265
3d47fd47
SV		 1266static inline uint32_t __offset_AD(uint32_t idx)
1267{
1268 switch (idx) {
1269 case 0: return (mdp5_cfg->ad.base[0]);
1270 case 1: return (mdp5_cfg->ad.base[1]);
1271 default: return INVALID_IDX(idx);
1272 }
1273}
1274static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
facb4f4e 1275
3d47fd47 1276static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
facb4f4e 1277
3d47fd47 1278static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
facb4f4e 1279
3d47fd47 1280static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
facb4f4e 1281
3d47fd47 1282static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
facb4f4e 1283
3d47fd47 1284static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
facb4f4e 1285
3d47fd47 1286static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
facb4f4e 1287
3d47fd47 1288static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
facb4f4e 1289
3d47fd47 1290static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
facb4f4e 1291
3d47fd47 1292static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
facb4f4e 1293
3d47fd47 1294static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
facb4f4e 1295
3d47fd47 1296static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
facb4f4e 1297
3d47fd47 1298static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
facb4f4e 1299
3d47fd47 1300static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
facb4f4e 1301
3d47fd47 1302static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
facb4f4e 1303
3d47fd47 1304static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
facb4f4e 1305
3d47fd47 1306static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
facb4f4e 1307
3d47fd47 1308static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
facb4f4e 1309
3d47fd47 1310static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
facb4f4e 1311
3d47fd47 1312static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
facb4f4e 1313
3d47fd47 1314static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
facb4f4e 1315
3d47fd47 1316static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
facb4f4e 1317
3d47fd47 1318static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
facb4f4e 1319
3d47fd47 1320static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
facb4f4e 1321
3d47fd47 1322static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
facb4f4e 1323
3d47fd47 1324static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
facb4f4e 1325
3d47fd47 1326static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
facb4f4e 1327
3d47fd47 1328static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
facb4f4e 1329
3d47fd47 1330static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
facb4f4e 1331
3d47fd47 1332static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
facb4f4e 1333
3d47fd47 1334static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
facb4f4e 1335
3d47fd47 1336static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
facb4f4e 1337
3d47fd47 1338static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
facb4f4e 1339
3d47fd47 1340static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
facb4f4e 1341
3d47fd47 1342static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
facb4f4e
RC		 1343
1344
1345#endif /* MDP5_XML */
Linux kernel - Deliverables
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