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drm/atomic: Make prepare_fb/cleanup_fb only take state, v3.
[deliverable/linux.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_plane.c
CommitLineData
06c0dd96 1/*
bef799fb 2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
06c0dd96
RC		 3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "mdp5_kms.h"
20
06c0dd96
RC		 21struct mdp5_plane {
22 struct drm_plane base;
23 const char *name;
24
25 enum mdp5_pipe pipe;
26
0deed25b
SV		 27 spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */
28 uint32_t reg_offset;
3498409f 29 uint32_t caps;
0deed25b
SV		 30
31 uint32_t flush_mask; /* used to commit pipe registers */
32
06c0dd96
RC		 33 uint32_t nformats;
34 uint32_t formats[32];
06c0dd96
RC		 35};
36#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
37
ed851963
RC		 38static int mdp5_plane_mode_set(struct drm_plane *plane,
39 struct drm_crtc *crtc, struct drm_framebuffer *fb,
40 int crtc_x, int crtc_y,
41 unsigned int crtc_w, unsigned int crtc_h,
42 uint32_t src_x, uint32_t src_y,
43 uint32_t src_w, uint32_t src_h);
bef799fb 44
ed851963
RC		 45static void set_scanout_locked(struct drm_plane *plane,
46 struct drm_framebuffer *fb);
47
06c0dd96
RC		 48static struct mdp5_kms *get_kms(struct drm_plane *plane)
49{
50 struct msm_drm_private *priv = plane->dev->dev_private;
51 return to_mdp5_kms(to_mdp_kms(priv->kms));
52}
53
ed851963 54static bool plane_enabled(struct drm_plane_state *state)
06c0dd96 55{
ed851963 56 return state->fb && state->crtc;
06c0dd96
RC		 57}
58
06c0dd96
RC		 59static void mdp5_plane_destroy(struct drm_plane *plane)
60{
61 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
62
ed851963 63 drm_plane_helper_disable(plane);
06c0dd96
RC		 64 drm_plane_cleanup(plane);
65
66 kfree(mdp5_plane);
67}
68
8089082f 69static void mdp5_plane_install_rotation_property(struct drm_device *dev,
70 struct drm_plane *plane)
71{
72 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
73
74 if (!(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP) &&
75 !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP))
76 return;
77
78 if (!dev->mode_config.rotation_property)
79 dev->mode_config.rotation_property =
80 drm_mode_create_rotation_property(dev,
81 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y));
82
83 if (dev->mode_config.rotation_property)
84 drm_object_attach_property(&plane->base,
85 dev->mode_config.rotation_property,
86 0);
87}
88
06c0dd96 89/* helper to install properties which are common to planes and crtcs */
4ff696ea 90static void mdp5_plane_install_properties(struct drm_plane *plane,
06c0dd96
RC		 91 struct drm_mode_object *obj)
92{
12987781 93 struct drm_device *dev = plane->dev;
94 struct msm_drm_private *dev_priv = dev->dev_private;
95 struct drm_property *prop;
96
97#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
98 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
99 if (!prop) { \
100 prop = drm_property_##fnc(dev, 0, #name, \
101 ##__VA_ARGS__); \
102 if (!prop) { \
103 dev_warn(dev->dev, \
104 "Create property %s failed\n", \
105 #name); \
106 return; \
107 } \
108 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
109 } \
110 drm_object_attach_property(&plane->base, prop, init_val); \
111 } while (0)
112
113#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
114 INSTALL_PROPERTY(name, NAME, init_val, \
115 create_range, min, max)
116
117#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
118 INSTALL_PROPERTY(name, NAME, init_val, \
119 create_enum, name##_prop_enum_list, \
120 ARRAY_SIZE(name##_prop_enum_list))
121
122 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
123
8089082f 124 mdp5_plane_install_rotation_property(dev, plane);
125
12987781 126#undef INSTALL_RANGE_PROPERTY
127#undef INSTALL_ENUM_PROPERTY
128#undef INSTALL_PROPERTY
06c0dd96
RC		 129}
130
12987781 131static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
132 struct drm_plane_state *state, struct drm_property *property,
133 uint64_t val)
134{
135 struct drm_device *dev = plane->dev;
136 struct mdp5_plane_state *pstate;
137 struct msm_drm_private *dev_priv = dev->dev_private;
138 int ret = 0;
139
140 pstate = to_mdp5_plane_state(state);
141
142#define SET_PROPERTY(name, NAME, type) do { \
143 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
144 pstate->name = (type)val; \
145 DBG("Set property %s %d", #name, (type)val); \
146 goto done; \
147 } \
148 } while (0)
149
150 SET_PROPERTY(zpos, ZPOS, uint8_t);
151
152 dev_err(dev->dev, "Invalid property\n");
153 ret = -EINVAL;
154done:
155 return ret;
156#undef SET_PROPERTY
157}
158
12987781 159static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
160 const struct drm_plane_state *state,
161 struct drm_property *property, uint64_t *val)
162{
163 struct drm_device *dev = plane->dev;
164 struct mdp5_plane_state *pstate;
165 struct msm_drm_private *dev_priv = dev->dev_private;
166 int ret = 0;
167
168 pstate = to_mdp5_plane_state(state);
169
170#define GET_PROPERTY(name, NAME, type) do { \
171 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
172 *val = pstate->name; \
173 DBG("Get property %s %lld", #name, *val); \
174 goto done; \
175 } \
176 } while (0)
177
178 GET_PROPERTY(zpos, ZPOS, uint8_t);
179
180 dev_err(dev->dev, "Invalid property\n");
181 ret = -EINVAL;
182done:
183 return ret;
184#undef SET_PROPERTY
06c0dd96
RC		 185}
186
ed851963
RC		 187static void mdp5_plane_reset(struct drm_plane *plane)
188{
189 struct mdp5_plane_state *mdp5_state;
190
191 if (plane->state && plane->state->fb)
192 drm_framebuffer_unreference(plane->state->fb);
193
194 kfree(to_mdp5_plane_state(plane->state));
195 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
196
12987781 197 /* assign default blend parameters */
198 mdp5_state->alpha = 255;
199 mdp5_state->premultiplied = 0;
200
201 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
202 mdp5_state->zpos = STAGE_BASE;
203 else
204 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
205
07cc0ef6 206 mdp5_state->base.plane = plane;
ed851963
RC		 207
208 plane->state = &mdp5_state->base;
209}
210
211static struct drm_plane_state *
212mdp5_plane_duplicate_state(struct drm_plane *plane)
213{
214 struct mdp5_plane_state *mdp5_state;
215
216 if (WARN_ON(!plane->state))
217 return NULL;
218
219 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
220 sizeof(*mdp5_state), GFP_KERNEL);
221
222 if (mdp5_state && mdp5_state->base.fb)
223 drm_framebuffer_reference(mdp5_state->base.fb);
224
225 mdp5_state->mode_changed = false;
226 mdp5_state->pending = false;
227
228 return &mdp5_state->base;
229}
230
231static void mdp5_plane_destroy_state(struct drm_plane *plane,
232 struct drm_plane_state *state)
233{
234 if (state->fb)
235 drm_framebuffer_unreference(state->fb);
236
237 kfree(to_mdp5_plane_state(state));
238}
239
06c0dd96 240static const struct drm_plane_funcs mdp5_plane_funcs = {
ed851963
RC		 241 .update_plane = drm_atomic_helper_update_plane,
242 .disable_plane = drm_atomic_helper_disable_plane,
06c0dd96 243 .destroy = mdp5_plane_destroy,
8089082f 244 .set_property = drm_atomic_helper_plane_set_property,
12987781 245 .atomic_set_property = mdp5_plane_atomic_set_property,
246 .atomic_get_property = mdp5_plane_atomic_get_property,
ed851963
RC		 247 .reset = mdp5_plane_reset,
248 .atomic_duplicate_state = mdp5_plane_duplicate_state,
249 .atomic_destroy_state = mdp5_plane_destroy_state,
06c0dd96
RC		 250};
251
ed851963 252static int mdp5_plane_prepare_fb(struct drm_plane *plane,
d136dfee 253 const struct drm_plane_state *new_state)
06c0dd96 254{
ed851963 255 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
06c0dd96 256 struct mdp5_kms *mdp5_kms = get_kms(plane);
844f9111
ML		 257 struct drm_framebuffer *fb = new_state->fb;
258
259 if (!new_state->fb)
260 return 0;
06c0dd96 261
ed851963
RC		 262 DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id);
263 return msm_framebuffer_prepare(fb, mdp5_kms->id);
0deed25b
SV		 264}
265
ed851963 266static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
d136dfee 267 const struct drm_plane_state *old_state)
0deed25b
SV		 268{
269 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
270 struct mdp5_kms *mdp5_kms = get_kms(plane);
844f9111
ML		 271 struct drm_framebuffer *fb = old_state->fb;
272
273 if (!fb)
274 return;
0deed25b 275
ed851963
RC		 276 DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id);
277 msm_framebuffer_cleanup(fb, mdp5_kms->id);
278}
0deed25b 279
ed851963
RC		 280static int mdp5_plane_atomic_check(struct drm_plane *plane,
281 struct drm_plane_state *state)
282{
283 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
284 struct drm_plane_state *old_state = plane->state;
3498409f 285 const struct mdp_format *format;
8089082f 286 bool vflip, hflip;
ed851963
RC		 287
288 DBG("%s: check (%d -> %d)", mdp5_plane->name,
289 plane_enabled(old_state), plane_enabled(state));
290
3498409f 291 if (plane_enabled(state)) {
292 format = to_mdp_format(msm_framebuffer_format(state->fb));
293 if (MDP_FORMAT_IS_YUV(format) &&
294 !pipe_supports_yuv(mdp5_plane->caps)) {
295 dev_err(plane->dev->dev,
296 "Pipe doesn't support YUV\n");
297
298 return -EINVAL;
299 }
300
301 if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) &&
302 (((state->src_w >> 16) != state->crtc_w) ||
303 ((state->src_h >> 16) != state->crtc_h))) {
304 dev_err(plane->dev->dev,
305 "Pipe doesn't support scaling (%dx%d -> %dx%d)\n",
306 state->src_w >> 16, state->src_h >> 16,
307 state->crtc_w, state->crtc_h);
308
309 return -EINVAL;
310 }
8089082f 311
312 hflip = !!(state->rotation & BIT(DRM_REFLECT_X));
313 vflip = !!(state->rotation & BIT(DRM_REFLECT_Y));
314 if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) ||
315 (hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) {
316 dev_err(plane->dev->dev,
317 "Pipe doesn't support flip\n");
318
319 return -EINVAL;
320 }
3498409f 321 }
322
ed851963
RC		 323 if (plane_enabled(state) && plane_enabled(old_state)) {
324 /* we cannot change SMP block configuration during scanout: */
325 bool full_modeset = false;
326 if (state->fb->pixel_format != old_state->fb->pixel_format) {
327 DBG("%s: pixel_format change!", mdp5_plane->name);
328 full_modeset = true;
329 }
330 if (state->src_w != old_state->src_w) {
331 DBG("%s: src_w change!", mdp5_plane->name);
332 full_modeset = true;
333 }
334 if (to_mdp5_plane_state(old_state)->pending) {
335 DBG("%s: still pending!", mdp5_plane->name);
336 full_modeset = true;
337 }
338 if (full_modeset) {
339 struct drm_crtc_state *crtc_state =
340 drm_atomic_get_crtc_state(state->state, state->crtc);
341 crtc_state->mode_changed = true;
342 to_mdp5_plane_state(state)->mode_changed = true;
343 }
344 } else {
345 to_mdp5_plane_state(state)->mode_changed = true;
346 }
06c0dd96 347
ed851963
RC		 348 return 0;
349}
350
f1c37e1a
TR		 351static void mdp5_plane_atomic_update(struct drm_plane *plane,
352 struct drm_plane_state *old_state)
ed851963
RC		 353{
354 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
355 struct drm_plane_state *state = plane->state;
356
357 DBG("%s: update", mdp5_plane->name);
0deed25b 358
ed851963
RC		 359 if (!plane_enabled(state)) {
360 to_mdp5_plane_state(state)->pending = true;
ed851963
RC		 361 } else if (to_mdp5_plane_state(state)->mode_changed) {
362 int ret;
363 to_mdp5_plane_state(state)->pending = true;
364 ret = mdp5_plane_mode_set(plane,
365 state->crtc, state->fb,
366 state->crtc_x, state->crtc_y,
367 state->crtc_w, state->crtc_h,
368 state->src_x, state->src_y,
369 state->src_w, state->src_h);
370 /* atomic_check should have ensured that this doesn't fail */
371 WARN_ON(ret < 0);
372 } else {
373 unsigned long flags;
374 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
375 set_scanout_locked(plane, state->fb);
376 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
377 }
0deed25b
SV		 378}
379
ed851963
RC		 380static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
381 .prepare_fb = mdp5_plane_prepare_fb,
382 .cleanup_fb = mdp5_plane_cleanup_fb,
383 .atomic_check = mdp5_plane_atomic_check,
384 .atomic_update = mdp5_plane_atomic_update,
385};
386
387static void set_scanout_locked(struct drm_plane *plane,
0deed25b
SV		 388 struct drm_framebuffer *fb)
389{
390 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
ed851963
RC		 391 struct mdp5_kms *mdp5_kms = get_kms(plane);
392 enum mdp5_pipe pipe = mdp5_plane->pipe;
06c0dd96 393
ed851963
RC		 394 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
395 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
396 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
0deed25b 397
ed851963
RC		 398 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
399 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
400 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
401
402 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
403 msm_framebuffer_iova(fb, mdp5_kms->id, 0));
404 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
405 msm_framebuffer_iova(fb, mdp5_kms->id, 1));
406 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
407 msm_framebuffer_iova(fb, mdp5_kms->id, 2));
408 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
755c814a 409 msm_framebuffer_iova(fb, mdp5_kms->id, 3));
06c0dd96
RC		 410
411 plane->fb = fb;
412}
413
f8d9b515
SV		 414/* Note: mdp5_plane->pipe_lock must be locked */
415static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
416{
417 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
418 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
419
420 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
421}
422
423/* Note: mdp5_plane->pipe_lock must be locked */
424static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
425 struct csc_cfg *csc)
426{
427 uint32_t i, mode = 0; /* RGB, no CSC */
428 uint32_t *matrix;
429
430 if (unlikely(!csc))
431 return;
432
433 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
434 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
435 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
436 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
437 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
438 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
439
440 matrix = csc->matrix;
441 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
442 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
443 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
444 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
445 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
446 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
447 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
448 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
449 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
450 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
451 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
452 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
453 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
454 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
455
456 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
457 uint32_t *pre_clamp = csc->pre_clamp;
458 uint32_t *post_clamp = csc->post_clamp;
459
460 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
461 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
462 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
463
464 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
465 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
466 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
467
468 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
469 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
470
471 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
472 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
473 }
474}
475
476#define PHASE_STEP_SHIFT 21
477#define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
478
479static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
480{
481 uint32_t unit;
482
483 if (src == 0 || dst == 0)
484 return -EINVAL;
485
486 /*
487 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
488 * where 2^21 represents the unity "1" in fixed-point hardware design.
489 * This leaves 5 bits for the integer part (downscale case):
490 * -> maximum downscale ratio = 0b1_1111 = 31
491 */
492 if (src > (dst * DOWN_SCALE_RATIO_MAX))
493 return -EOVERFLOW;
494
495 unit = 1 << PHASE_STEP_SHIFT;
496 *out_phase = mult_frac(unit, src, dst);
497
498 return 0;
499}
500
bef799fb
SV		 501static int calc_scalex_steps(struct drm_plane *plane,
502 uint32_t pixel_format, uint32_t src, uint32_t dest,
f8d9b515
SV		 503 uint32_t phasex_steps[2])
504{
bef799fb
SV		 505 struct mdp5_kms *mdp5_kms = get_kms(plane);
506 struct device *dev = mdp5_kms->dev->dev;
f8d9b515
SV		 507 uint32_t phasex_step;
508 unsigned int hsub;
509 int ret;
510
511 ret = calc_phase_step(src, dest, &phasex_step);
bef799fb
SV		 512 if (ret) {
513 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
f8d9b515 514 return ret;
bef799fb 515 }
f8d9b515
SV		 516
517 hsub = drm_format_horz_chroma_subsampling(pixel_format);
518
519 phasex_steps[0] = phasex_step;
520 phasex_steps[1] = phasex_step / hsub;
521
522 return 0;
523}
524
bef799fb
SV		 525static int calc_scaley_steps(struct drm_plane *plane,
526 uint32_t pixel_format, uint32_t src, uint32_t dest,
f8d9b515
SV		 527 uint32_t phasey_steps[2])
528{
bef799fb
SV		 529 struct mdp5_kms *mdp5_kms = get_kms(plane);
530 struct device *dev = mdp5_kms->dev->dev;
f8d9b515
SV		 531 uint32_t phasey_step;
532 unsigned int vsub;
533 int ret;
534
535 ret = calc_phase_step(src, dest, &phasey_step);
bef799fb
SV		 536 if (ret) {
537 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
f8d9b515 538 return ret;
bef799fb 539 }
f8d9b515
SV		 540
541 vsub = drm_format_vert_chroma_subsampling(pixel_format);
542
543 phasey_steps[0] = phasey_step;
544 phasey_steps[1] = phasey_step / vsub;
545
546 return 0;
547}
548
bef799fb
SV		 549static uint32_t get_scale_config(enum mdp_chroma_samp_type chroma_sample,
550 uint32_t src, uint32_t dest, bool hor)
f8d9b515 551{
bef799fb
SV		 552 uint32_t y_filter = (src <= dest) ? SCALE_FILTER_CA : SCALE_FILTER_PCMN;
553 uint32_t y_a_filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
554 uint32_t uv_filter = ((src / 2) <= dest) ? /* 2x upsample */
555 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
556 uint32_t value = 0;
557
558 if (chroma_sample == CHROMA_420 || chroma_sample == CHROMA_H2V1) {
559 if (hor)
560 value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
561 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_filter) |
562 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter) |
563 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter);
564 else
565 value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
566 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_filter) |
567 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter) |
568 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter);
569 } else if (src != dest) {
570 if (hor)
571 value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
572 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_a_filter) |
573 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter);
574 else
575 value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
576 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_a_filter) |
577 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter);
578 }
f8d9b515 579
bef799fb 580 return value;
f8d9b515
SV		 581}
582
ed851963 583static int mdp5_plane_mode_set(struct drm_plane *plane,
06c0dd96
RC		 584 struct drm_crtc *crtc, struct drm_framebuffer *fb,
585 int crtc_x, int crtc_y,
586 unsigned int crtc_w, unsigned int crtc_h,
587 uint32_t src_x, uint32_t src_y,
588 uint32_t src_w, uint32_t src_h)
589{
590 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
8089082f 591 struct drm_plane_state *pstate = plane->state;
06c0dd96
RC		 592 struct mdp5_kms *mdp5_kms = get_kms(plane);
593 enum mdp5_pipe pipe = mdp5_plane->pipe;
594 const struct mdp_format *format;
595 uint32_t nplanes, config = 0;
f8d9b515
SV		 596 /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */
597 uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,};
06c0dd96 598 uint32_t hdecm = 0, vdecm = 0;
f8d9b515 599 uint32_t pix_format;
8089082f 600 bool vflip, hflip;
0deed25b 601 unsigned long flags;
bfcdfb0e 602 int ret;
06c0dd96
RC		 603
604 nplanes = drm_format_num_planes(fb->pixel_format);
605
606 /* bad formats should already be rejected: */
607 if (WARN_ON(nplanes > pipe2nclients(pipe)))
608 return -EINVAL;
609
f8d9b515
SV		 610 format = to_mdp_format(msm_framebuffer_format(fb));
611 pix_format = format->base.pixel_format;
612
06c0dd96
RC		 613 /* src values are in Q16 fixed point, convert to integer: */
614 src_x = src_x >> 16;
615 src_y = src_y >> 16;
616 src_w = src_w >> 16;
617 src_h = src_h >> 16;
618
619 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
620 fb->base.id, src_x, src_y, src_w, src_h,
621 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
622
bfcdfb0e 623 /* Request some memory from the SMP: */
42238da8 624 ret = mdp5_smp_request(mdp5_kms->smp,
9cc137a3 625 mdp5_plane->pipe, format, src_w, false);
bfcdfb0e
SV		 626 if (ret)
627 return ret;
06c0dd96
RC		 628
629 /*
630 * Currently we update the hw for allocations/requests immediately,
631 * but once atomic modeset/pageflip is in place, the allocation
632 * would move into atomic->check_plane_state(), while updating the
633 * hw would remain here:
634 */
42238da8 635 mdp5_smp_configure(mdp5_kms->smp, pipe);
06c0dd96 636
bef799fb
SV		 637 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
638 if (ret)
639 return ret;
f8d9b515 640
bef799fb
SV		 641 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step);
642 if (ret)
643 return ret;
06c0dd96 644
bef799fb
SV		 645 /* TODO calc hdecm, vdecm */
646
647 /* SCALE is used to both scale and up-sample chroma components */
648 config |= get_scale_config(format->chroma_sample, src_w, crtc_w, true);
649 config |= get_scale_config(format->chroma_sample, src_h, crtc_h, false);
650 DBG("scale config = %x", config);
06c0dd96 651
8089082f 652 hflip = !!(pstate->rotation & BIT(DRM_REFLECT_X));
653 vflip = !!(pstate->rotation & BIT(DRM_REFLECT_Y));
654
0deed25b
SV		 655 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
656
06c0dd96 657 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
de31ea69
HL		 658 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(fb->width) |
659 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(fb->height));
06c0dd96
RC		 660
661 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
662 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
663 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
664
665 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
666 MDP5_PIPE_SRC_XY_X(src_x) |
667 MDP5_PIPE_SRC_XY_Y(src_y));
668
669 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
670 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
671 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
672
673 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
674 MDP5_PIPE_OUT_XY_X(crtc_x) |
675 MDP5_PIPE_OUT_XY_Y(crtc_y));
676
06c0dd96
RC		 677 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
678 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
679 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
680 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
681 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
682 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
683 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
684 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
685 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
2d3584eb 686 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
f8d9b515 687 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
06c0dd96
RC		 688
689 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
690 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
691 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
692 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
693 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
694
695 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
8089082f 696 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
697 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
06c0dd96
RC		 698 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
699
700 /* not using secure mode: */
701 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
702
3498409f 703 if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) {
704 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
705 phasex_step[0]);
706 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
707 phasey_step[0]);
708 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
709 phasex_step[1]);
710 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
711 phasey_step[1]);
712 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
713 MDP5_PIPE_DECIMATION_VERT(vdecm) |
714 MDP5_PIPE_DECIMATION_HORZ(hdecm));
715 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
716 }
717
718 if (mdp5_plane->caps & MDP_PIPE_CAP_CSC) {
719 if (MDP_FORMAT_IS_YUV(format))
720 csc_enable(mdp5_kms, pipe,
721 mdp_get_default_csc_cfg(CSC_YUV2RGB));
722 else
723 csc_disable(mdp5_kms, pipe);
724 }
06c0dd96 725
ed851963 726 set_scanout_locked(plane, fb);
0deed25b
SV		 727
728 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
729
0deed25b 730 return ret;
06c0dd96
RC		 731}
732
733void mdp5_plane_complete_flip(struct drm_plane *plane)
734{
735 struct mdp5_kms *mdp5_kms = get_kms(plane);
ed851963
RC		 736 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
737 enum mdp5_pipe pipe = mdp5_plane->pipe;
738
739 DBG("%s: complete flip", mdp5_plane->name);
06c0dd96 740
42238da8 741 mdp5_smp_commit(mdp5_kms->smp, pipe);
ed851963
RC		 742
743 to_mdp5_plane_state(plane->state)->pending = false;
06c0dd96
RC		 744}
745
746enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
747{
748 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
749 return mdp5_plane->pipe;
750}
751
0deed25b
SV		 752uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
753{
754 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
755
756 return mdp5_plane->flush_mask;
757}
758
657c63f0
WX		 759/* called after vsync in thread context */
760void mdp5_plane_complete_commit(struct drm_plane *plane,
761 struct drm_plane_state *state)
762{
763 struct mdp5_kms *mdp5_kms = get_kms(plane);
764 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
765 enum mdp5_pipe pipe = mdp5_plane->pipe;
766
767 if (!plane_enabled(plane->state)) {
768 DBG("%s: free SMP", mdp5_plane->name);
769 mdp5_smp_release(mdp5_kms->smp, pipe);
770 }
771}
772
06c0dd96
RC		 773/* initialize plane */
774struct drm_plane *mdp5_plane_init(struct drm_device *dev,
3498409f 775 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset,
776 uint32_t caps)
06c0dd96
RC		 777{
778 struct drm_plane *plane = NULL;
779 struct mdp5_plane *mdp5_plane;
780 int ret;
2d82d188 781 enum drm_plane_type type;
06c0dd96
RC		 782
783 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
784 if (!mdp5_plane) {
785 ret = -ENOMEM;
786 goto fail;
787 }
788
789 plane = &mdp5_plane->base;
790
791 mdp5_plane->pipe = pipe;
792 mdp5_plane->name = pipe2name(pipe);
3498409f 793 mdp5_plane->caps = caps;
06c0dd96 794
3498409f 795 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
796 ARRAY_SIZE(mdp5_plane->formats),
797 !pipe_supports_yuv(mdp5_plane->caps));
06c0dd96 798
0deed25b
SV		 799 mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe);
800 mdp5_plane->reg_offset = reg_offset;
801 spin_lock_init(&mdp5_plane->pipe_lock);
802
2d82d188 803 type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
ed851963 804 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
2d82d188
MR		 805 mdp5_plane->formats, mdp5_plane->nformats,
806 type);
ed851963
RC		 807 if (ret)
808 goto fail;
809
810 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
06c0dd96
RC		 811
812 mdp5_plane_install_properties(plane, &plane->base);
813
814 return plane;
815
816fail:
817 if (plane)
818 mdp5_plane_destroy(plane);
819
820 return ERR_PTR(ret);
821}
Linux kernel - Deliverables
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