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drm/msm/mdp: mark if a MDP format is YUV at definition
[deliverable/linux.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_plane.c
CommitLineData
06c0dd96 1/*
0deed25b 2 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
06c0dd96
RC		 3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "mdp5_kms.h"
20
06c0dd96
RC		 21struct mdp5_plane {
22 struct drm_plane base;
23 const char *name;
24
25 enum mdp5_pipe pipe;
26
0deed25b
SV		 27 spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */
28 uint32_t reg_offset;
29
30 uint32_t flush_mask; /* used to commit pipe registers */
31
06c0dd96
RC		 32 uint32_t nformats;
33 uint32_t formats[32];
06c0dd96
RC		 34};
35#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
36
ed851963
RC		 37static int mdp5_plane_mode_set(struct drm_plane *plane,
38 struct drm_crtc *crtc, struct drm_framebuffer *fb,
39 int crtc_x, int crtc_y,
40 unsigned int crtc_w, unsigned int crtc_h,
41 uint32_t src_x, uint32_t src_y,
42 uint32_t src_w, uint32_t src_h);
43static void set_scanout_locked(struct drm_plane *plane,
44 struct drm_framebuffer *fb);
45
06c0dd96
RC		 46static struct mdp5_kms *get_kms(struct drm_plane *plane)
47{
48 struct msm_drm_private *priv = plane->dev->dev_private;
49 return to_mdp5_kms(to_mdp_kms(priv->kms));
50}
51
ed851963 52static bool plane_enabled(struct drm_plane_state *state)
06c0dd96 53{
ed851963 54 return state->fb && state->crtc;
06c0dd96
RC		 55}
56
06c0dd96
RC		 57static void mdp5_plane_destroy(struct drm_plane *plane)
58{
59 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
60
ed851963 61 drm_plane_helper_disable(plane);
06c0dd96
RC		 62 drm_plane_cleanup(plane);
63
64 kfree(mdp5_plane);
65}
66
67/* helper to install properties which are common to planes and crtcs */
4ff696ea 68static void mdp5_plane_install_properties(struct drm_plane *plane,
06c0dd96
RC		 69 struct drm_mode_object *obj)
70{
12987781 71 struct drm_device *dev = plane->dev;
72 struct msm_drm_private *dev_priv = dev->dev_private;
73 struct drm_property *prop;
74
75#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
76 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
77 if (!prop) { \
78 prop = drm_property_##fnc(dev, 0, #name, \
79 ##__VA_ARGS__); \
80 if (!prop) { \
81 dev_warn(dev->dev, \
82 "Create property %s failed\n", \
83 #name); \
84 return; \
85 } \
86 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
87 } \
88 drm_object_attach_property(&plane->base, prop, init_val); \
89 } while (0)
90
91#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
92 INSTALL_PROPERTY(name, NAME, init_val, \
93 create_range, min, max)
94
95#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
96 INSTALL_PROPERTY(name, NAME, init_val, \
97 create_enum, name##_prop_enum_list, \
98 ARRAY_SIZE(name##_prop_enum_list))
99
100 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
101
102#undef INSTALL_RANGE_PROPERTY
103#undef INSTALL_ENUM_PROPERTY
104#undef INSTALL_PROPERTY
06c0dd96
RC		 105}
106
12987781 107static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
108 struct drm_plane_state *state, struct drm_property *property,
109 uint64_t val)
110{
111 struct drm_device *dev = plane->dev;
112 struct mdp5_plane_state *pstate;
113 struct msm_drm_private *dev_priv = dev->dev_private;
114 int ret = 0;
115
116 pstate = to_mdp5_plane_state(state);
117
118#define SET_PROPERTY(name, NAME, type) do { \
119 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
120 pstate->name = (type)val; \
121 DBG("Set property %s %d", #name, (type)val); \
122 goto done; \
123 } \
124 } while (0)
125
126 SET_PROPERTY(zpos, ZPOS, uint8_t);
127
128 dev_err(dev->dev, "Invalid property\n");
129 ret = -EINVAL;
130done:
131 return ret;
132#undef SET_PROPERTY
133}
134
135static int mdp5_plane_set_property(struct drm_plane *plane,
06c0dd96
RC		 136 struct drm_property *property, uint64_t val)
137{
12987781 138 return mdp5_plane_atomic_set_property(plane, plane->state, property,
139 val);
140}
141
142static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
143 const struct drm_plane_state *state,
144 struct drm_property *property, uint64_t *val)
145{
146 struct drm_device *dev = plane->dev;
147 struct mdp5_plane_state *pstate;
148 struct msm_drm_private *dev_priv = dev->dev_private;
149 int ret = 0;
150
151 pstate = to_mdp5_plane_state(state);
152
153#define GET_PROPERTY(name, NAME, type) do { \
154 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
155 *val = pstate->name; \
156 DBG("Get property %s %lld", #name, *val); \
157 goto done; \
158 } \
159 } while (0)
160
161 GET_PROPERTY(zpos, ZPOS, uint8_t);
162
163 dev_err(dev->dev, "Invalid property\n");
164 ret = -EINVAL;
165done:
166 return ret;
167#undef SET_PROPERTY
06c0dd96
RC		 168}
169
ed851963
RC		 170static void mdp5_plane_reset(struct drm_plane *plane)
171{
172 struct mdp5_plane_state *mdp5_state;
173
174 if (plane->state && plane->state->fb)
175 drm_framebuffer_unreference(plane->state->fb);
176
177 kfree(to_mdp5_plane_state(plane->state));
178 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
179
12987781 180 /* assign default blend parameters */
181 mdp5_state->alpha = 255;
182 mdp5_state->premultiplied = 0;
183
184 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
185 mdp5_state->zpos = STAGE_BASE;
186 else
187 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
188
07cc0ef6 189 mdp5_state->base.plane = plane;
ed851963
RC		 190
191 plane->state = &mdp5_state->base;
192}
193
194static struct drm_plane_state *
195mdp5_plane_duplicate_state(struct drm_plane *plane)
196{
197 struct mdp5_plane_state *mdp5_state;
198
199 if (WARN_ON(!plane->state))
200 return NULL;
201
202 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
203 sizeof(*mdp5_state), GFP_KERNEL);
204
205 if (mdp5_state && mdp5_state->base.fb)
206 drm_framebuffer_reference(mdp5_state->base.fb);
207
208 mdp5_state->mode_changed = false;
209 mdp5_state->pending = false;
210
211 return &mdp5_state->base;
212}
213
214static void mdp5_plane_destroy_state(struct drm_plane *plane,
215 struct drm_plane_state *state)
216{
217 if (state->fb)
218 drm_framebuffer_unreference(state->fb);
219
220 kfree(to_mdp5_plane_state(state));
221}
222
06c0dd96 223static const struct drm_plane_funcs mdp5_plane_funcs = {
ed851963
RC		 224 .update_plane = drm_atomic_helper_update_plane,
225 .disable_plane = drm_atomic_helper_disable_plane,
06c0dd96
RC		 226 .destroy = mdp5_plane_destroy,
227 .set_property = mdp5_plane_set_property,
12987781 228 .atomic_set_property = mdp5_plane_atomic_set_property,
229 .atomic_get_property = mdp5_plane_atomic_get_property,
ed851963
RC		 230 .reset = mdp5_plane_reset,
231 .atomic_duplicate_state = mdp5_plane_duplicate_state,
232 .atomic_destroy_state = mdp5_plane_destroy_state,
06c0dd96
RC		 233};
234
ed851963 235static int mdp5_plane_prepare_fb(struct drm_plane *plane,
d136dfee
TU		 236 struct drm_framebuffer *fb,
237 const struct drm_plane_state *new_state)
06c0dd96 238{
ed851963 239 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
06c0dd96 240 struct mdp5_kms *mdp5_kms = get_kms(plane);
06c0dd96 241
ed851963
RC		 242 DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id);
243 return msm_framebuffer_prepare(fb, mdp5_kms->id);
0deed25b
SV		 244}
245
ed851963 246static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
d136dfee
TU		 247 struct drm_framebuffer *fb,
248 const struct drm_plane_state *old_state)
0deed25b
SV		 249{
250 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
251 struct mdp5_kms *mdp5_kms = get_kms(plane);
0deed25b 252
ed851963
RC		 253 DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id);
254 msm_framebuffer_cleanup(fb, mdp5_kms->id);
255}
0deed25b 256
ed851963
RC		 257static int mdp5_plane_atomic_check(struct drm_plane *plane,
258 struct drm_plane_state *state)
259{
260 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
261 struct drm_plane_state *old_state = plane->state;
262
263 DBG("%s: check (%d -> %d)", mdp5_plane->name,
264 plane_enabled(old_state), plane_enabled(state));
265
266 if (plane_enabled(state) && plane_enabled(old_state)) {
267 /* we cannot change SMP block configuration during scanout: */
268 bool full_modeset = false;
269 if (state->fb->pixel_format != old_state->fb->pixel_format) {
270 DBG("%s: pixel_format change!", mdp5_plane->name);
271 full_modeset = true;
272 }
273 if (state->src_w != old_state->src_w) {
274 DBG("%s: src_w change!", mdp5_plane->name);
275 full_modeset = true;
276 }
277 if (to_mdp5_plane_state(old_state)->pending) {
278 DBG("%s: still pending!", mdp5_plane->name);
279 full_modeset = true;
280 }
281 if (full_modeset) {
282 struct drm_crtc_state *crtc_state =
283 drm_atomic_get_crtc_state(state->state, state->crtc);
284 crtc_state->mode_changed = true;
285 to_mdp5_plane_state(state)->mode_changed = true;
286 }
287 } else {
288 to_mdp5_plane_state(state)->mode_changed = true;
289 }
06c0dd96 290
ed851963
RC		 291 return 0;
292}
293
f1c37e1a
TR		 294static void mdp5_plane_atomic_update(struct drm_plane *plane,
295 struct drm_plane_state *old_state)
ed851963
RC		 296{
297 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
298 struct drm_plane_state *state = plane->state;
299
300 DBG("%s: update", mdp5_plane->name);
0deed25b 301
ed851963
RC		 302 if (!plane_enabled(state)) {
303 to_mdp5_plane_state(state)->pending = true;
ed851963
RC		 304 } else if (to_mdp5_plane_state(state)->mode_changed) {
305 int ret;
306 to_mdp5_plane_state(state)->pending = true;
307 ret = mdp5_plane_mode_set(plane,
308 state->crtc, state->fb,
309 state->crtc_x, state->crtc_y,
310 state->crtc_w, state->crtc_h,
311 state->src_x, state->src_y,
312 state->src_w, state->src_h);
313 /* atomic_check should have ensured that this doesn't fail */
314 WARN_ON(ret < 0);
315 } else {
316 unsigned long flags;
317 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
318 set_scanout_locked(plane, state->fb);
319 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
320 }
0deed25b
SV		 321}
322
ed851963
RC		 323static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
324 .prepare_fb = mdp5_plane_prepare_fb,
325 .cleanup_fb = mdp5_plane_cleanup_fb,
326 .atomic_check = mdp5_plane_atomic_check,
327 .atomic_update = mdp5_plane_atomic_update,
328};
329
330static void set_scanout_locked(struct drm_plane *plane,
0deed25b
SV		 331 struct drm_framebuffer *fb)
332{
333 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
ed851963
RC		 334 struct mdp5_kms *mdp5_kms = get_kms(plane);
335 enum mdp5_pipe pipe = mdp5_plane->pipe;
06c0dd96 336
ed851963
RC		 337 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
338 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
339 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
0deed25b 340
ed851963
RC		 341 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
342 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
343 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
344
345 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
346 msm_framebuffer_iova(fb, mdp5_kms->id, 0));
347 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
348 msm_framebuffer_iova(fb, mdp5_kms->id, 1));
349 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
350 msm_framebuffer_iova(fb, mdp5_kms->id, 2));
351 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
755c814a 352 msm_framebuffer_iova(fb, mdp5_kms->id, 3));
06c0dd96
RC		 353
354 plane->fb = fb;
355}
356
f8d9b515
SV		 357/* Note: mdp5_plane->pipe_lock must be locked */
358static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
359{
360 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
361 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
362
363 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
364}
365
366/* Note: mdp5_plane->pipe_lock must be locked */
367static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
368 struct csc_cfg *csc)
369{
370 uint32_t i, mode = 0; /* RGB, no CSC */
371 uint32_t *matrix;
372
373 if (unlikely(!csc))
374 return;
375
376 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
377 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
378 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
379 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
380 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
381 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
382
383 matrix = csc->matrix;
384 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
385 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
386 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
387 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
388 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
389 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
390 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
391 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
392 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
393 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
394 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
395 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
396 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
397 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
398
399 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
400 uint32_t *pre_clamp = csc->pre_clamp;
401 uint32_t *post_clamp = csc->post_clamp;
402
403 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
404 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
405 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
406
407 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
408 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
409 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
410
411 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
412 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
413
414 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
415 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
416 }
417}
418
419#define PHASE_STEP_SHIFT 21
420#define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
421
422static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
423{
424 uint32_t unit;
425
426 if (src == 0 || dst == 0)
427 return -EINVAL;
428
429 /*
430 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
431 * where 2^21 represents the unity "1" in fixed-point hardware design.
432 * This leaves 5 bits for the integer part (downscale case):
433 * -> maximum downscale ratio = 0b1_1111 = 31
434 */
435 if (src > (dst * DOWN_SCALE_RATIO_MAX))
436 return -EOVERFLOW;
437
438 unit = 1 << PHASE_STEP_SHIFT;
439 *out_phase = mult_frac(unit, src, dst);
440
441 return 0;
442}
443
444static int calc_scalex_steps(uint32_t pixel_format, uint32_t src, uint32_t dest,
445 uint32_t phasex_steps[2])
446{
447 uint32_t phasex_step;
448 unsigned int hsub;
449 int ret;
450
451 ret = calc_phase_step(src, dest, &phasex_step);
452 if (ret)
453 return ret;
454
455 hsub = drm_format_horz_chroma_subsampling(pixel_format);
456
457 phasex_steps[0] = phasex_step;
458 phasex_steps[1] = phasex_step / hsub;
459
460 return 0;
461}
462
463static int calc_scaley_steps(uint32_t pixel_format, uint32_t src, uint32_t dest,
464 uint32_t phasey_steps[2])
465{
466 uint32_t phasey_step;
467 unsigned int vsub;
468 int ret;
469
470 ret = calc_phase_step(src, dest, &phasey_step);
471 if (ret)
472 return ret;
473
474 vsub = drm_format_vert_chroma_subsampling(pixel_format);
475
476 phasey_steps[0] = phasey_step;
477 phasey_steps[1] = phasey_step / vsub;
478
479 return 0;
480}
481
482static uint32_t get_scalex_config(uint32_t src, uint32_t dest)
483{
484 uint32_t filter;
485
486 filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
487
2d3584eb
RC		 488 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
489 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(filter) |
490 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(filter) |
491 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(filter);
f8d9b515
SV		 492}
493
494static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
495{
496 uint32_t filter;
497
498 filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
499
2d3584eb
RC		 500 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
501 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(filter) |
502 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(filter) |
503 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(filter);
f8d9b515
SV		 504}
505
ed851963 506static int mdp5_plane_mode_set(struct drm_plane *plane,
06c0dd96
RC		 507 struct drm_crtc *crtc, struct drm_framebuffer *fb,
508 int crtc_x, int crtc_y,
509 unsigned int crtc_w, unsigned int crtc_h,
510 uint32_t src_x, uint32_t src_y,
511 uint32_t src_w, uint32_t src_h)
512{
513 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
514 struct mdp5_kms *mdp5_kms = get_kms(plane);
f8d9b515 515 struct device *dev = mdp5_kms->dev->dev;
06c0dd96
RC		 516 enum mdp5_pipe pipe = mdp5_plane->pipe;
517 const struct mdp_format *format;
518 uint32_t nplanes, config = 0;
f8d9b515
SV		 519 /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */
520 uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,};
06c0dd96 521 uint32_t hdecm = 0, vdecm = 0;
f8d9b515 522 uint32_t pix_format;
0deed25b 523 unsigned long flags;
bfcdfb0e 524 int ret;
06c0dd96
RC		 525
526 nplanes = drm_format_num_planes(fb->pixel_format);
527
528 /* bad formats should already be rejected: */
529 if (WARN_ON(nplanes > pipe2nclients(pipe)))
530 return -EINVAL;
531
f8d9b515
SV		 532 format = to_mdp_format(msm_framebuffer_format(fb));
533 pix_format = format->base.pixel_format;
534
06c0dd96
RC		 535 /* src values are in Q16 fixed point, convert to integer: */
536 src_x = src_x >> 16;
537 src_y = src_y >> 16;
538 src_w = src_w >> 16;
539 src_h = src_h >> 16;
540
541 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
542 fb->base.id, src_x, src_y, src_w, src_h,
543 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
544
bfcdfb0e 545 /* Request some memory from the SMP: */
42238da8 546 ret = mdp5_smp_request(mdp5_kms->smp,
bfcdfb0e
SV		 547 mdp5_plane->pipe, fb->pixel_format, src_w);
548 if (ret)
549 return ret;
06c0dd96
RC		 550
551 /*
552 * Currently we update the hw for allocations/requests immediately,
553 * but once atomic modeset/pageflip is in place, the allocation
554 * would move into atomic->check_plane_state(), while updating the
555 * hw would remain here:
556 */
42238da8 557 mdp5_smp_configure(mdp5_kms->smp, pipe);
06c0dd96 558
f8d9b515
SV		 559 /* SCALE is used to both scale and up-sample chroma components */
560
561 if ((src_w != crtc_w) || MDP_FORMAT_IS_YUV(format)) {
562 /* TODO calc hdecm */
563 ret = calc_scalex_steps(pix_format, src_w, crtc_w, phasex_step);
564 if (ret) {
565 dev_err(dev, "X scaling (%d -> %d) failed: %d\n",
566 src_w, crtc_w, ret);
567 return ret;
568 }
569 config |= get_scalex_config(src_w, crtc_w);
06c0dd96
RC		 570 }
571
f8d9b515
SV		 572 if ((src_h != crtc_h) || MDP_FORMAT_IS_YUV(format)) {
573 /* TODO calc vdecm */
574 ret = calc_scaley_steps(pix_format, src_h, crtc_h, phasey_step);
575 if (ret) {
576 dev_err(dev, "Y scaling (%d -> %d) failed: %d\n",
577 src_h, crtc_h, ret);
578 return ret;
579 }
580 config |= get_scaley_config(src_h, crtc_h);
06c0dd96
RC		 581 }
582
0deed25b
SV		 583 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
584
06c0dd96 585 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
de31ea69
HL		 586 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(fb->width) |
587 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(fb->height));
06c0dd96
RC		 588
589 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
590 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
591 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
592
593 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
594 MDP5_PIPE_SRC_XY_X(src_x) |
595 MDP5_PIPE_SRC_XY_Y(src_y));
596
597 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
598 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
599 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
600
601 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
602 MDP5_PIPE_OUT_XY_X(crtc_x) |
603 MDP5_PIPE_OUT_XY_Y(crtc_y));
604
06c0dd96
RC		 605 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
606 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
607 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
608 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
609 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
610 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
611 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
612 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
613 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
2d3584eb 614 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
f8d9b515 615 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
06c0dd96
RC		 616
617 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
618 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
619 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
620 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
621 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
622
623 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
624 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
625
626 /* not using secure mode: */
627 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
628
f8d9b515
SV		 629 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
630 phasex_step[0]);
631 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
632 phasey_step[0]);
633 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
634 phasex_step[1]);
635 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
636 phasey_step[1]);
06c0dd96
RC		 637 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
638 MDP5_PIPE_DECIMATION_VERT(vdecm) |
639 MDP5_PIPE_DECIMATION_HORZ(hdecm));
f8d9b515
SV		 640 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
641
642 if (MDP_FORMAT_IS_YUV(format))
643 csc_enable(mdp5_kms, pipe,
644 mdp_get_default_csc_cfg(CSC_YUV2RGB));
645 else
646 csc_disable(mdp5_kms, pipe);
06c0dd96 647
ed851963 648 set_scanout_locked(plane, fb);
0deed25b
SV		 649
650 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
651
0deed25b 652 return ret;
06c0dd96
RC		 653}
654
655void mdp5_plane_complete_flip(struct drm_plane *plane)
656{
657 struct mdp5_kms *mdp5_kms = get_kms(plane);
ed851963
RC		 658 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
659 enum mdp5_pipe pipe = mdp5_plane->pipe;
660
661 DBG("%s: complete flip", mdp5_plane->name);
06c0dd96 662
42238da8 663 mdp5_smp_commit(mdp5_kms->smp, pipe);
ed851963
RC		 664
665 to_mdp5_plane_state(plane->state)->pending = false;
06c0dd96
RC		 666}
667
668enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
669{
670 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
671 return mdp5_plane->pipe;
672}
673
0deed25b
SV		 674uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
675{
676 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
677
678 return mdp5_plane->flush_mask;
679}
680
657c63f0
WX		 681/* called after vsync in thread context */
682void mdp5_plane_complete_commit(struct drm_plane *plane,
683 struct drm_plane_state *state)
684{
685 struct mdp5_kms *mdp5_kms = get_kms(plane);
686 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
687 enum mdp5_pipe pipe = mdp5_plane->pipe;
688
689 if (!plane_enabled(plane->state)) {
690 DBG("%s: free SMP", mdp5_plane->name);
691 mdp5_smp_release(mdp5_kms->smp, pipe);
692 }
693}
694
06c0dd96
RC		 695/* initialize plane */
696struct drm_plane *mdp5_plane_init(struct drm_device *dev,
0deed25b 697 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset)
06c0dd96
RC		 698{
699 struct drm_plane *plane = NULL;
700 struct mdp5_plane *mdp5_plane;
701 int ret;
2d82d188 702 enum drm_plane_type type;
06c0dd96
RC		 703
704 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
705 if (!mdp5_plane) {
706 ret = -ENOMEM;
707 goto fail;
708 }
709
710 plane = &mdp5_plane->base;
711
712 mdp5_plane->pipe = pipe;
713 mdp5_plane->name = pipe2name(pipe);
714
715 mdp5_plane->nformats = mdp5_get_formats(pipe, mdp5_plane->formats,
716 ARRAY_SIZE(mdp5_plane->formats));
717
0deed25b
SV		 718 mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe);
719 mdp5_plane->reg_offset = reg_offset;
720 spin_lock_init(&mdp5_plane->pipe_lock);
721
2d82d188 722 type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
ed851963 723 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
2d82d188
MR		 724 mdp5_plane->formats, mdp5_plane->nformats,
725 type);
ed851963
RC		 726 if (ret)
727 goto fail;
728
729 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
06c0dd96
RC		 730
731 mdp5_plane_install_properties(plane, &plane->base);
732
733 return plane;
734
735fail:
736 if (plane)
737 mdp5_plane_destroy(plane);
738
739 return ERR_PTR(ret);
740}
Linux kernel - Deliverables
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