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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
7198e6b0 | 19 | #include "msm_gpu.h" |
dd2da6e3 | 20 | #include "msm_kms.h" |
c8afe684 | 21 | |
c8afe684 RC |
22 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
23 | { | |
24 | struct msm_drm_private *priv = dev->dev_private; | |
25 | if (priv->fbdev) | |
26 | drm_fb_helper_hotplug_event(priv->fbdev); | |
27 | } | |
28 | ||
29 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
30 | .fb_create = msm_framebuffer_create, | |
31 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 32 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 33 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
34 | }; |
35 | ||
871d812a | 36 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
37 | { |
38 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 39 | int idx = priv->num_mmus++; |
c8afe684 | 40 | |
871d812a | 41 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
42 | return -EINVAL; |
43 | ||
871d812a | 44 | priv->mmus[idx] = mmu; |
c8afe684 RC |
45 | |
46 | return idx; | |
47 | } | |
48 | ||
c8afe684 RC |
49 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
50 | static bool reglog = false; | |
51 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
52 | module_param(reglog, bool, 0600); | |
53 | #else | |
54 | #define reglog 0 | |
55 | #endif | |
56 | ||
e90dfec7 RC |
57 | #ifdef CONFIG_DRM_MSM_FBDEV |
58 | static bool fbdev = true; | |
59 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
60 | module_param(fbdev, bool, 0600); | |
61 | #endif | |
62 | ||
3a10ba8c | 63 | static char *vram = "16m"; |
871d812a RC |
64 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU"); |
65 | module_param(vram, charp, 0); | |
66 | ||
060530f1 RC |
67 | /* |
68 | * Util/helpers: | |
69 | */ | |
70 | ||
c8afe684 RC |
71 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
72 | const char *dbgname) | |
73 | { | |
74 | struct resource *res; | |
75 | unsigned long size; | |
76 | void __iomem *ptr; | |
77 | ||
78 | if (name) | |
79 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
80 | else | |
81 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
82 | ||
83 | if (!res) { | |
84 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
85 | return ERR_PTR(-EINVAL); | |
86 | } | |
87 | ||
88 | size = resource_size(res); | |
89 | ||
90 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
91 | if (!ptr) { | |
92 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
93 | return ERR_PTR(-ENOMEM); | |
94 | } | |
95 | ||
96 | if (reglog) | |
97 | printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size); | |
98 | ||
99 | return ptr; | |
100 | } | |
101 | ||
102 | void msm_writel(u32 data, void __iomem *addr) | |
103 | { | |
104 | if (reglog) | |
105 | printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data); | |
106 | writel(data, addr); | |
107 | } | |
108 | ||
109 | u32 msm_readl(const void __iomem *addr) | |
110 | { | |
111 | u32 val = readl(addr); | |
112 | if (reglog) | |
113 | printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val); | |
114 | return val; | |
115 | } | |
116 | ||
117 | /* | |
118 | * DRM operations: | |
119 | */ | |
120 | ||
121 | static int msm_unload(struct drm_device *dev) | |
122 | { | |
123 | struct msm_drm_private *priv = dev->dev_private; | |
124 | struct msm_kms *kms = priv->kms; | |
7198e6b0 | 125 | struct msm_gpu *gpu = priv->gpu; |
c8afe684 RC |
126 | |
127 | drm_kms_helper_poll_fini(dev); | |
128 | drm_mode_config_cleanup(dev); | |
129 | drm_vblank_cleanup(dev); | |
130 | ||
131 | pm_runtime_get_sync(dev->dev); | |
132 | drm_irq_uninstall(dev); | |
133 | pm_runtime_put_sync(dev->dev); | |
134 | ||
135 | flush_workqueue(priv->wq); | |
136 | destroy_workqueue(priv->wq); | |
137 | ||
138 | if (kms) { | |
139 | pm_runtime_disable(dev->dev); | |
140 | kms->funcs->destroy(kms); | |
141 | } | |
142 | ||
7198e6b0 RC |
143 | if (gpu) { |
144 | mutex_lock(&dev->struct_mutex); | |
145 | gpu->funcs->pm_suspend(gpu); | |
146 | gpu->funcs->destroy(gpu); | |
147 | mutex_unlock(&dev->struct_mutex); | |
148 | } | |
c8afe684 | 149 | |
871d812a RC |
150 | if (priv->vram.paddr) { |
151 | DEFINE_DMA_ATTRS(attrs); | |
152 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
153 | drm_mm_takedown(&priv->vram.mm); | |
154 | dma_free_attrs(dev->dev, priv->vram.size, NULL, | |
155 | priv->vram.paddr, &attrs); | |
156 | } | |
157 | ||
060530f1 RC |
158 | component_unbind_all(dev->dev, dev); |
159 | ||
c8afe684 RC |
160 | dev->dev_private = NULL; |
161 | ||
162 | kfree(priv); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
06c0dd96 RC |
167 | static int get_mdp_ver(struct platform_device *pdev) |
168 | { | |
169 | #ifdef CONFIG_OF | |
370a4d8a | 170 | static const struct of_device_id match_types[] = { { |
06c0dd96 RC |
171 | .compatible = "qcom,mdss_mdp", |
172 | .data = (void *)5, | |
173 | }, { | |
174 | /* end node */ | |
175 | } }; | |
176 | struct device *dev = &pdev->dev; | |
177 | const struct of_device_id *match; | |
178 | match = of_match_node(match_types, dev->of_node); | |
179 | if (match) | |
180 | return (int)match->data; | |
181 | #endif | |
182 | return 4; | |
183 | } | |
184 | ||
c8afe684 RC |
185 | static int msm_load(struct drm_device *dev, unsigned long flags) |
186 | { | |
187 | struct platform_device *pdev = dev->platformdev; | |
188 | struct msm_drm_private *priv; | |
189 | struct msm_kms *kms; | |
190 | int ret; | |
191 | ||
192 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
193 | if (!priv) { | |
194 | dev_err(dev->dev, "failed to allocate private data\n"); | |
195 | return -ENOMEM; | |
196 | } | |
197 | ||
198 | dev->dev_private = priv; | |
199 | ||
200 | priv->wq = alloc_ordered_workqueue("msm", 0); | |
7198e6b0 | 201 | init_waitqueue_head(&priv->fence_event); |
f86afecf | 202 | init_waitqueue_head(&priv->pending_crtcs_event); |
c8afe684 RC |
203 | |
204 | INIT_LIST_HEAD(&priv->inactive_list); | |
edd4fc63 | 205 | INIT_LIST_HEAD(&priv->fence_cbs); |
c8afe684 RC |
206 | |
207 | drm_mode_config_init(dev); | |
208 | ||
871d812a RC |
209 | /* if we have no IOMMU, then we need to use carveout allocator. |
210 | * Grab the entire CMA chunk carved out in early startup in | |
211 | * mach-msm: | |
212 | */ | |
213 | if (!iommu_present(&platform_bus_type)) { | |
214 | DEFINE_DMA_ATTRS(attrs); | |
215 | unsigned long size; | |
216 | void *p; | |
217 | ||
218 | DBG("using %s VRAM carveout", vram); | |
219 | size = memparse(vram, NULL); | |
220 | priv->vram.size = size; | |
221 | ||
222 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
223 | ||
224 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
225 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
226 | ||
227 | /* note that for no-kernel-mapping, the vaddr returned | |
228 | * is bogus, but non-null if allocation succeeded: | |
229 | */ | |
230 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 231 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
232 | if (!p) { |
233 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
234 | priv->vram.paddr = 0; | |
235 | ret = -ENOMEM; | |
236 | goto fail; | |
237 | } | |
238 | ||
239 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
240 | (uint32_t)priv->vram.paddr, | |
241 | (uint32_t)(priv->vram.paddr + size)); | |
242 | } | |
243 | ||
060530f1 RC |
244 | platform_set_drvdata(pdev, dev); |
245 | ||
246 | /* Bind all our sub-components: */ | |
247 | ret = component_bind_all(dev->dev, dev); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
06c0dd96 RC |
251 | switch (get_mdp_ver(pdev)) { |
252 | case 4: | |
253 | kms = mdp4_kms_init(dev); | |
254 | break; | |
255 | case 5: | |
256 | kms = mdp5_kms_init(dev); | |
257 | break; | |
258 | default: | |
259 | kms = ERR_PTR(-ENODEV); | |
260 | break; | |
261 | } | |
262 | ||
c8afe684 RC |
263 | if (IS_ERR(kms)) { |
264 | /* | |
265 | * NOTE: once we have GPU support, having no kms should not | |
266 | * be considered fatal.. ideally we would still support gpu | |
267 | * and (for example) use dmabuf/prime to share buffers with | |
268 | * imx drm driver on iMX5 | |
269 | */ | |
270 | dev_err(dev->dev, "failed to load kms\n"); | |
e4826a94 | 271 | ret = PTR_ERR(kms); |
c8afe684 RC |
272 | goto fail; |
273 | } | |
274 | ||
275 | priv->kms = kms; | |
276 | ||
277 | if (kms) { | |
278 | pm_runtime_enable(dev->dev); | |
279 | ret = kms->funcs->hw_init(kms); | |
280 | if (ret) { | |
281 | dev_err(dev->dev, "kms hw init failed: %d\n", ret); | |
282 | goto fail; | |
283 | } | |
284 | } | |
285 | ||
286 | dev->mode_config.min_width = 0; | |
287 | dev->mode_config.min_height = 0; | |
288 | dev->mode_config.max_width = 2048; | |
289 | dev->mode_config.max_height = 2048; | |
290 | dev->mode_config.funcs = &mode_config_funcs; | |
291 | ||
d65bd0e4 | 292 | ret = drm_vblank_init(dev, priv->num_crtcs); |
c8afe684 RC |
293 | if (ret < 0) { |
294 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
295 | goto fail; | |
296 | } | |
297 | ||
298 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 299 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
c8afe684 RC |
300 | pm_runtime_put_sync(dev->dev); |
301 | if (ret < 0) { | |
302 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
303 | goto fail; | |
304 | } | |
305 | ||
cf3a7e4c RC |
306 | drm_mode_config_reset(dev); |
307 | ||
c8afe684 | 308 | #ifdef CONFIG_DRM_MSM_FBDEV |
e90dfec7 RC |
309 | if (fbdev) |
310 | priv->fbdev = msm_fbdev_init(dev); | |
c8afe684 RC |
311 | #endif |
312 | ||
a7d3c950 RC |
313 | ret = msm_debugfs_late_init(dev); |
314 | if (ret) | |
315 | goto fail; | |
316 | ||
c8afe684 RC |
317 | drm_kms_helper_poll_init(dev); |
318 | ||
319 | return 0; | |
320 | ||
321 | fail: | |
322 | msm_unload(dev); | |
323 | return ret; | |
324 | } | |
325 | ||
7198e6b0 RC |
326 | static void load_gpu(struct drm_device *dev) |
327 | { | |
a1ad3523 | 328 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 329 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 330 | |
a1ad3523 RC |
331 | mutex_lock(&init_lock); |
332 | ||
e2550b7a RC |
333 | if (!priv->gpu) |
334 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 335 | |
a1ad3523 | 336 | mutex_unlock(&init_lock); |
7198e6b0 RC |
337 | } |
338 | ||
339 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
340 | { | |
341 | struct msm_file_private *ctx; | |
342 | ||
343 | /* For now, load gpu on open.. to avoid the requirement of having | |
344 | * firmware in the initrd. | |
345 | */ | |
346 | load_gpu(dev); | |
347 | ||
348 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
349 | if (!ctx) | |
350 | return -ENOMEM; | |
351 | ||
352 | file->driver_priv = ctx; | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
c8afe684 RC |
357 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
358 | { | |
359 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 360 | struct msm_file_private *ctx = file->driver_priv; |
c8afe684 | 361 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 362 | |
c8afe684 RC |
363 | if (kms) |
364 | kms->funcs->preclose(kms, file); | |
7198e6b0 RC |
365 | |
366 | mutex_lock(&dev->struct_mutex); | |
367 | if (ctx == priv->lastctx) | |
368 | priv->lastctx = NULL; | |
369 | mutex_unlock(&dev->struct_mutex); | |
370 | ||
371 | kfree(ctx); | |
c8afe684 RC |
372 | } |
373 | ||
374 | static void msm_lastclose(struct drm_device *dev) | |
375 | { | |
376 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
377 | if (priv->fbdev) |
378 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
379 | } |
380 | ||
e9f0d76f | 381 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
382 | { |
383 | struct drm_device *dev = arg; | |
384 | struct msm_drm_private *priv = dev->dev_private; | |
385 | struct msm_kms *kms = priv->kms; | |
386 | BUG_ON(!kms); | |
387 | return kms->funcs->irq(kms); | |
388 | } | |
389 | ||
390 | static void msm_irq_preinstall(struct drm_device *dev) | |
391 | { | |
392 | struct msm_drm_private *priv = dev->dev_private; | |
393 | struct msm_kms *kms = priv->kms; | |
394 | BUG_ON(!kms); | |
395 | kms->funcs->irq_preinstall(kms); | |
396 | } | |
397 | ||
398 | static int msm_irq_postinstall(struct drm_device *dev) | |
399 | { | |
400 | struct msm_drm_private *priv = dev->dev_private; | |
401 | struct msm_kms *kms = priv->kms; | |
402 | BUG_ON(!kms); | |
403 | return kms->funcs->irq_postinstall(kms); | |
404 | } | |
405 | ||
406 | static void msm_irq_uninstall(struct drm_device *dev) | |
407 | { | |
408 | struct msm_drm_private *priv = dev->dev_private; | |
409 | struct msm_kms *kms = priv->kms; | |
410 | BUG_ON(!kms); | |
411 | kms->funcs->irq_uninstall(kms); | |
412 | } | |
413 | ||
414 | static int msm_enable_vblank(struct drm_device *dev, int crtc_id) | |
415 | { | |
416 | struct msm_drm_private *priv = dev->dev_private; | |
417 | struct msm_kms *kms = priv->kms; | |
418 | if (!kms) | |
419 | return -ENXIO; | |
420 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
421 | return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]); | |
422 | } | |
423 | ||
424 | static void msm_disable_vblank(struct drm_device *dev, int crtc_id) | |
425 | { | |
426 | struct msm_drm_private *priv = dev->dev_private; | |
427 | struct msm_kms *kms = priv->kms; | |
428 | if (!kms) | |
429 | return; | |
430 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
431 | kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]); | |
432 | } | |
433 | ||
434 | /* | |
435 | * DRM debugfs: | |
436 | */ | |
437 | ||
438 | #ifdef CONFIG_DEBUG_FS | |
7198e6b0 RC |
439 | static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) |
440 | { | |
441 | struct msm_drm_private *priv = dev->dev_private; | |
442 | struct msm_gpu *gpu = priv->gpu; | |
443 | ||
444 | if (gpu) { | |
445 | seq_printf(m, "%s Status:\n", gpu->name); | |
446 | gpu->funcs->show(gpu, m); | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
c8afe684 RC |
452 | static int msm_gem_show(struct drm_device *dev, struct seq_file *m) |
453 | { | |
454 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
455 | struct msm_gpu *gpu = priv->gpu; |
456 | ||
457 | if (gpu) { | |
458 | seq_printf(m, "Active Objects (%s):\n", gpu->name); | |
459 | msm_gem_describe_objects(&gpu->active_list, m); | |
460 | } | |
c8afe684 | 461 | |
7198e6b0 | 462 | seq_printf(m, "Inactive Objects:\n"); |
c8afe684 RC |
463 | msm_gem_describe_objects(&priv->inactive_list, m); |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static int msm_mm_show(struct drm_device *dev, struct seq_file *m) | |
469 | { | |
b04a5906 | 470 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
c8afe684 RC |
471 | } |
472 | ||
473 | static int msm_fb_show(struct drm_device *dev, struct seq_file *m) | |
474 | { | |
475 | struct msm_drm_private *priv = dev->dev_private; | |
476 | struct drm_framebuffer *fb, *fbdev_fb = NULL; | |
477 | ||
478 | if (priv->fbdev) { | |
479 | seq_printf(m, "fbcon "); | |
480 | fbdev_fb = priv->fbdev->fb; | |
481 | msm_framebuffer_describe(fbdev_fb, m); | |
482 | } | |
483 | ||
484 | mutex_lock(&dev->mode_config.fb_lock); | |
485 | list_for_each_entry(fb, &dev->mode_config.fb_list, head) { | |
486 | if (fb == fbdev_fb) | |
487 | continue; | |
488 | ||
489 | seq_printf(m, "user "); | |
490 | msm_framebuffer_describe(fb, m); | |
491 | } | |
492 | mutex_unlock(&dev->mode_config.fb_lock); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | static int show_locked(struct seq_file *m, void *arg) | |
498 | { | |
499 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
500 | struct drm_device *dev = node->minor->dev; | |
501 | int (*show)(struct drm_device *dev, struct seq_file *m) = | |
502 | node->info_ent->data; | |
503 | int ret; | |
504 | ||
505 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | ret = show(dev, m); | |
510 | ||
511 | mutex_unlock(&dev->struct_mutex); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
516 | static struct drm_info_list msm_debugfs_list[] = { | |
7198e6b0 | 517 | {"gpu", show_locked, 0, msm_gpu_show}, |
c8afe684 RC |
518 | {"gem", show_locked, 0, msm_gem_show}, |
519 | { "mm", show_locked, 0, msm_mm_show }, | |
520 | { "fb", show_locked, 0, msm_fb_show }, | |
521 | }; | |
522 | ||
a7d3c950 RC |
523 | static int late_init_minor(struct drm_minor *minor) |
524 | { | |
525 | int ret; | |
526 | ||
527 | if (!minor) | |
528 | return 0; | |
529 | ||
530 | ret = msm_rd_debugfs_init(minor); | |
531 | if (ret) { | |
532 | dev_err(minor->dev->dev, "could not install rd debugfs\n"); | |
533 | return ret; | |
534 | } | |
535 | ||
70c70f09 RC |
536 | ret = msm_perf_debugfs_init(minor); |
537 | if (ret) { | |
538 | dev_err(minor->dev->dev, "could not install perf debugfs\n"); | |
539 | return ret; | |
540 | } | |
541 | ||
a7d3c950 RC |
542 | return 0; |
543 | } | |
544 | ||
545 | int msm_debugfs_late_init(struct drm_device *dev) | |
546 | { | |
547 | int ret; | |
548 | ret = late_init_minor(dev->primary); | |
549 | if (ret) | |
550 | return ret; | |
551 | ret = late_init_minor(dev->render); | |
552 | if (ret) | |
553 | return ret; | |
554 | ret = late_init_minor(dev->control); | |
555 | return ret; | |
556 | } | |
557 | ||
c8afe684 RC |
558 | static int msm_debugfs_init(struct drm_minor *minor) |
559 | { | |
560 | struct drm_device *dev = minor->dev; | |
561 | int ret; | |
562 | ||
563 | ret = drm_debugfs_create_files(msm_debugfs_list, | |
564 | ARRAY_SIZE(msm_debugfs_list), | |
565 | minor->debugfs_root, minor); | |
566 | ||
567 | if (ret) { | |
568 | dev_err(dev->dev, "could not install msm_debugfs_list\n"); | |
569 | return ret; | |
570 | } | |
571 | ||
a7d3c950 | 572 | return 0; |
c8afe684 RC |
573 | } |
574 | ||
575 | static void msm_debugfs_cleanup(struct drm_minor *minor) | |
576 | { | |
577 | drm_debugfs_remove_files(msm_debugfs_list, | |
578 | ARRAY_SIZE(msm_debugfs_list), minor); | |
a7d3c950 RC |
579 | if (!minor->dev->dev_private) |
580 | return; | |
581 | msm_rd_debugfs_cleanup(minor); | |
70c70f09 | 582 | msm_perf_debugfs_cleanup(minor); |
c8afe684 RC |
583 | } |
584 | #endif | |
585 | ||
7198e6b0 RC |
586 | /* |
587 | * Fences: | |
588 | */ | |
589 | ||
590 | int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, | |
591 | struct timespec *timeout) | |
592 | { | |
593 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
594 | int ret; |
595 | ||
f816f272 RC |
596 | if (!priv->gpu) |
597 | return 0; | |
598 | ||
599 | if (fence > priv->gpu->submitted_fence) { | |
600 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
601 | fence, priv->gpu->submitted_fence); | |
602 | return -EINVAL; | |
603 | } | |
604 | ||
605 | if (!timeout) { | |
606 | /* no-wait: */ | |
607 | ret = fence_completed(dev, fence) ? 0 : -EBUSY; | |
608 | } else { | |
609 | unsigned long timeout_jiffies = timespec_to_jiffies(timeout); | |
610 | unsigned long start_jiffies = jiffies; | |
611 | unsigned long remaining_jiffies; | |
612 | ||
613 | if (time_after(start_jiffies, timeout_jiffies)) | |
614 | remaining_jiffies = 0; | |
615 | else | |
616 | remaining_jiffies = timeout_jiffies - start_jiffies; | |
617 | ||
618 | ret = wait_event_interruptible_timeout(priv->fence_event, | |
619 | fence_completed(dev, fence), | |
620 | remaining_jiffies); | |
621 | ||
622 | if (ret == 0) { | |
623 | DBG("timeout waiting for fence: %u (completed: %u)", | |
624 | fence, priv->completed_fence); | |
625 | ret = -ETIMEDOUT; | |
626 | } else if (ret != -ERESTARTSYS) { | |
627 | ret = 0; | |
628 | } | |
7198e6b0 RC |
629 | } |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
69193e50 RC |
634 | int msm_queue_fence_cb(struct drm_device *dev, |
635 | struct msm_fence_cb *cb, uint32_t fence) | |
636 | { | |
637 | struct msm_drm_private *priv = dev->dev_private; | |
638 | int ret = 0; | |
639 | ||
640 | mutex_lock(&dev->struct_mutex); | |
641 | if (!list_empty(&cb->work.entry)) { | |
642 | ret = -EINVAL; | |
643 | } else if (fence > priv->completed_fence) { | |
644 | cb->fence = fence; | |
645 | list_add_tail(&cb->work.entry, &priv->fence_cbs); | |
646 | } else { | |
647 | queue_work(priv->wq, &cb->work); | |
648 | } | |
649 | mutex_unlock(&dev->struct_mutex); | |
650 | ||
651 | return ret; | |
652 | } | |
653 | ||
edd4fc63 | 654 | /* called from workqueue */ |
7198e6b0 RC |
655 | void msm_update_fence(struct drm_device *dev, uint32_t fence) |
656 | { | |
657 | struct msm_drm_private *priv = dev->dev_private; | |
658 | ||
edd4fc63 RC |
659 | mutex_lock(&dev->struct_mutex); |
660 | priv->completed_fence = max(fence, priv->completed_fence); | |
661 | ||
662 | while (!list_empty(&priv->fence_cbs)) { | |
663 | struct msm_fence_cb *cb; | |
664 | ||
665 | cb = list_first_entry(&priv->fence_cbs, | |
666 | struct msm_fence_cb, work.entry); | |
667 | ||
668 | if (cb->fence > priv->completed_fence) | |
669 | break; | |
670 | ||
671 | list_del_init(&cb->work.entry); | |
672 | queue_work(priv->wq, &cb->work); | |
7198e6b0 | 673 | } |
edd4fc63 RC |
674 | |
675 | mutex_unlock(&dev->struct_mutex); | |
676 | ||
677 | wake_up_all(&priv->fence_event); | |
678 | } | |
679 | ||
680 | void __msm_fence_worker(struct work_struct *work) | |
681 | { | |
682 | struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work); | |
683 | cb->func(cb); | |
7198e6b0 RC |
684 | } |
685 | ||
686 | /* | |
687 | * DRM ioctls: | |
688 | */ | |
689 | ||
690 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
691 | struct drm_file *file) | |
692 | { | |
693 | struct msm_drm_private *priv = dev->dev_private; | |
694 | struct drm_msm_param *args = data; | |
695 | struct msm_gpu *gpu; | |
696 | ||
697 | /* for now, we just have 3d pipe.. eventually this would need to | |
698 | * be more clever to dispatch to appropriate gpu module: | |
699 | */ | |
700 | if (args->pipe != MSM_PIPE_3D0) | |
701 | return -EINVAL; | |
702 | ||
703 | gpu = priv->gpu; | |
704 | ||
705 | if (!gpu) | |
706 | return -ENXIO; | |
707 | ||
708 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
709 | } | |
710 | ||
711 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
712 | struct drm_file *file) | |
713 | { | |
714 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
715 | |
716 | if (args->flags & ~MSM_BO_FLAGS) { | |
717 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
718 | return -EINVAL; | |
719 | } | |
720 | ||
7198e6b0 RC |
721 | return msm_gem_new_handle(dev, file, args->size, |
722 | args->flags, &args->handle); | |
723 | } | |
724 | ||
725 | #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec }) | |
726 | ||
727 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
728 | struct drm_file *file) | |
729 | { | |
730 | struct drm_msm_gem_cpu_prep *args = data; | |
731 | struct drm_gem_object *obj; | |
732 | int ret; | |
733 | ||
93ddb0d3 RC |
734 | if (args->op & ~MSM_PREP_FLAGS) { |
735 | DRM_ERROR("invalid op: %08x\n", args->op); | |
736 | return -EINVAL; | |
737 | } | |
738 | ||
7198e6b0 RC |
739 | obj = drm_gem_object_lookup(dev, file, args->handle); |
740 | if (!obj) | |
741 | return -ENOENT; | |
742 | ||
743 | ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout)); | |
744 | ||
745 | drm_gem_object_unreference_unlocked(obj); | |
746 | ||
747 | return ret; | |
748 | } | |
749 | ||
750 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
751 | struct drm_file *file) | |
752 | { | |
753 | struct drm_msm_gem_cpu_fini *args = data; | |
754 | struct drm_gem_object *obj; | |
755 | int ret; | |
756 | ||
757 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
758 | if (!obj) | |
759 | return -ENOENT; | |
760 | ||
761 | ret = msm_gem_cpu_fini(obj); | |
762 | ||
763 | drm_gem_object_unreference_unlocked(obj); | |
764 | ||
765 | return ret; | |
766 | } | |
767 | ||
768 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
769 | struct drm_file *file) | |
770 | { | |
771 | struct drm_msm_gem_info *args = data; | |
772 | struct drm_gem_object *obj; | |
773 | int ret = 0; | |
774 | ||
775 | if (args->pad) | |
776 | return -EINVAL; | |
777 | ||
778 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
779 | if (!obj) | |
780 | return -ENOENT; | |
781 | ||
782 | args->offset = msm_gem_mmap_offset(obj); | |
783 | ||
784 | drm_gem_object_unreference_unlocked(obj); | |
785 | ||
786 | return ret; | |
787 | } | |
788 | ||
789 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
790 | struct drm_file *file) | |
791 | { | |
792 | struct drm_msm_wait_fence *args = data; | |
93ddb0d3 RC |
793 | |
794 | if (args->pad) { | |
795 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | return msm_wait_fence_interruptable(dev, args->fence, | |
800 | &TS(args->timeout)); | |
7198e6b0 RC |
801 | } |
802 | ||
803 | static const struct drm_ioctl_desc msm_ioctls[] = { | |
b4b15c86 RC |
804 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
805 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
806 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
807 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
808 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
809 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
810 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
7198e6b0 RC |
811 | }; |
812 | ||
c8afe684 RC |
813 | static const struct vm_operations_struct vm_ops = { |
814 | .fault = msm_gem_fault, | |
815 | .open = drm_gem_vm_open, | |
816 | .close = drm_gem_vm_close, | |
817 | }; | |
818 | ||
819 | static const struct file_operations fops = { | |
820 | .owner = THIS_MODULE, | |
821 | .open = drm_open, | |
822 | .release = drm_release, | |
823 | .unlocked_ioctl = drm_ioctl, | |
824 | #ifdef CONFIG_COMPAT | |
825 | .compat_ioctl = drm_compat_ioctl, | |
826 | #endif | |
827 | .poll = drm_poll, | |
828 | .read = drm_read, | |
829 | .llseek = no_llseek, | |
830 | .mmap = msm_gem_mmap, | |
831 | }; | |
832 | ||
833 | static struct drm_driver msm_driver = { | |
05b84911 RC |
834 | .driver_features = DRIVER_HAVE_IRQ | |
835 | DRIVER_GEM | | |
836 | DRIVER_PRIME | | |
b4b15c86 | 837 | DRIVER_RENDER | |
05b84911 | 838 | DRIVER_MODESET, |
c8afe684 RC |
839 | .load = msm_load, |
840 | .unload = msm_unload, | |
7198e6b0 | 841 | .open = msm_open, |
c8afe684 RC |
842 | .preclose = msm_preclose, |
843 | .lastclose = msm_lastclose, | |
915b4d11 | 844 | .set_busid = drm_platform_set_busid, |
c8afe684 RC |
845 | .irq_handler = msm_irq, |
846 | .irq_preinstall = msm_irq_preinstall, | |
847 | .irq_postinstall = msm_irq_postinstall, | |
848 | .irq_uninstall = msm_irq_uninstall, | |
849 | .get_vblank_counter = drm_vblank_count, | |
850 | .enable_vblank = msm_enable_vblank, | |
851 | .disable_vblank = msm_disable_vblank, | |
852 | .gem_free_object = msm_gem_free_object, | |
853 | .gem_vm_ops = &vm_ops, | |
854 | .dumb_create = msm_gem_dumb_create, | |
855 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 856 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
857 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
858 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
859 | .gem_prime_export = drm_gem_prime_export, | |
860 | .gem_prime_import = drm_gem_prime_import, | |
861 | .gem_prime_pin = msm_gem_prime_pin, | |
862 | .gem_prime_unpin = msm_gem_prime_unpin, | |
863 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
864 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
865 | .gem_prime_vmap = msm_gem_prime_vmap, | |
866 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 867 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
868 | #ifdef CONFIG_DEBUG_FS |
869 | .debugfs_init = msm_debugfs_init, | |
870 | .debugfs_cleanup = msm_debugfs_cleanup, | |
871 | #endif | |
7198e6b0 RC |
872 | .ioctls = msm_ioctls, |
873 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
874 | .fops = &fops, |
875 | .name = "msm", | |
876 | .desc = "MSM Snapdragon DRM", | |
877 | .date = "20130625", | |
878 | .major = 1, | |
879 | .minor = 0, | |
880 | }; | |
881 | ||
882 | #ifdef CONFIG_PM_SLEEP | |
883 | static int msm_pm_suspend(struct device *dev) | |
884 | { | |
885 | struct drm_device *ddev = dev_get_drvdata(dev); | |
886 | ||
887 | drm_kms_helper_poll_disable(ddev); | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static int msm_pm_resume(struct device *dev) | |
893 | { | |
894 | struct drm_device *ddev = dev_get_drvdata(dev); | |
895 | ||
896 | drm_kms_helper_poll_enable(ddev); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | #endif | |
901 | ||
902 | static const struct dev_pm_ops msm_pm_ops = { | |
903 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
904 | }; | |
905 | ||
060530f1 RC |
906 | /* |
907 | * Componentized driver support: | |
908 | */ | |
909 | ||
910 | #ifdef CONFIG_OF | |
911 | /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx | |
912 | * (or probably any other).. so probably some room for some helpers | |
913 | */ | |
914 | static int compare_of(struct device *dev, void *data) | |
915 | { | |
916 | return dev->of_node == data; | |
917 | } | |
41e69778 RC |
918 | |
919 | static int add_components(struct device *dev, struct component_match **matchptr, | |
920 | const char *name) | |
921 | { | |
922 | struct device_node *np = dev->of_node; | |
923 | unsigned i; | |
924 | ||
925 | for (i = 0; ; i++) { | |
926 | struct device_node *node; | |
927 | ||
928 | node = of_parse_phandle(np, name, i); | |
929 | if (!node) | |
930 | break; | |
931 | ||
932 | component_match_add(dev, matchptr, compare_of, node); | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
84448288 RK |
937 | #else |
938 | static int compare_dev(struct device *dev, void *data) | |
939 | { | |
940 | return dev == data; | |
941 | } | |
942 | #endif | |
943 | ||
944 | static int msm_drm_bind(struct device *dev) | |
945 | { | |
946 | return drm_platform_init(&msm_driver, to_platform_device(dev)); | |
947 | } | |
948 | ||
949 | static void msm_drm_unbind(struct device *dev) | |
950 | { | |
951 | drm_put_dev(platform_get_drvdata(to_platform_device(dev))); | |
952 | } | |
953 | ||
954 | static const struct component_master_ops msm_drm_ops = { | |
955 | .bind = msm_drm_bind, | |
956 | .unbind = msm_drm_unbind, | |
957 | }; | |
958 | ||
959 | /* | |
960 | * Platform driver: | |
961 | */ | |
060530f1 | 962 | |
84448288 | 963 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 964 | { |
84448288 RK |
965 | struct component_match *match = NULL; |
966 | #ifdef CONFIG_OF | |
41e69778 RC |
967 | add_components(&pdev->dev, &match, "connectors"); |
968 | add_components(&pdev->dev, &match, "gpus"); | |
060530f1 | 969 | #else |
060530f1 RC |
970 | /* For non-DT case, it kinda sucks. We don't actually have a way |
971 | * to know whether or not we are waiting for certain devices (or if | |
972 | * they are simply not present). But for non-DT we only need to | |
973 | * care about apq8064/apq8060/etc (all mdp4/a3xx): | |
974 | */ | |
975 | static const char *devnames[] = { | |
976 | "hdmi_msm.0", "kgsl-3d0.0", | |
977 | }; | |
978 | int i; | |
979 | ||
980 | DBG("Adding components.."); | |
981 | ||
982 | for (i = 0; i < ARRAY_SIZE(devnames); i++) { | |
983 | struct device *dev; | |
060530f1 RC |
984 | |
985 | dev = bus_find_device_by_name(&platform_bus_type, | |
986 | NULL, devnames[i]); | |
987 | if (!dev) { | |
12313c2a | 988 | dev_info(&pdev->dev, "still waiting for %s\n", devnames[i]); |
060530f1 RC |
989 | return -EPROBE_DEFER; |
990 | } | |
991 | ||
84448288 | 992 | component_match_add(&pdev->dev, &match, compare_dev, dev); |
060530f1 | 993 | } |
060530f1 RC |
994 | #endif |
995 | ||
871d812a | 996 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 997 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
998 | } |
999 | ||
1000 | static int msm_pdev_remove(struct platform_device *pdev) | |
1001 | { | |
060530f1 | 1002 | component_master_del(&pdev->dev, &msm_drm_ops); |
c8afe684 RC |
1003 | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static const struct platform_device_id msm_id[] = { | |
1008 | { "mdp", 0 }, | |
1009 | { } | |
1010 | }; | |
1011 | ||
06c0dd96 | 1012 | static const struct of_device_id dt_match[] = { |
41e69778 RC |
1013 | { .compatible = "qcom,mdp" }, /* mdp4 */ |
1014 | { .compatible = "qcom,mdss_mdp" }, /* mdp5 */ | |
06c0dd96 RC |
1015 | {} |
1016 | }; | |
1017 | MODULE_DEVICE_TABLE(of, dt_match); | |
1018 | ||
c8afe684 RC |
1019 | static struct platform_driver msm_platform_driver = { |
1020 | .probe = msm_pdev_probe, | |
1021 | .remove = msm_pdev_remove, | |
1022 | .driver = { | |
c8afe684 | 1023 | .name = "msm", |
06c0dd96 | 1024 | .of_match_table = dt_match, |
c8afe684 RC |
1025 | .pm = &msm_pm_ops, |
1026 | }, | |
1027 | .id_table = msm_id, | |
1028 | }; | |
1029 | ||
1030 | static int __init msm_drm_register(void) | |
1031 | { | |
1032 | DBG("init"); | |
00453981 | 1033 | msm_edp_register(); |
c8afe684 | 1034 | hdmi_register(); |
bfd28b13 | 1035 | adreno_register(); |
c8afe684 RC |
1036 | return platform_driver_register(&msm_platform_driver); |
1037 | } | |
1038 | ||
1039 | static void __exit msm_drm_unregister(void) | |
1040 | { | |
1041 | DBG("fini"); | |
1042 | platform_driver_unregister(&msm_platform_driver); | |
1043 | hdmi_unregister(); | |
bfd28b13 | 1044 | adreno_unregister(); |
00453981 | 1045 | msm_edp_unregister(); |
c8afe684 RC |
1046 | } |
1047 | ||
1048 | module_init(msm_drm_register); | |
1049 | module_exit(msm_drm_unregister); | |
1050 | ||
1051 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1052 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1053 | MODULE_LICENSE("GPL"); |