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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
7198e6b0 | 19 | #include "msm_gpu.h" |
dd2da6e3 | 20 | #include "msm_kms.h" |
c8afe684 | 21 | |
c8afe684 RC |
22 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
23 | { | |
a2ca7789 | 24 | #ifdef CONFIG_DRM_MSM_FBDEV |
c8afe684 RC |
25 | struct msm_drm_private *priv = dev->dev_private; |
26 | if (priv->fbdev) | |
27 | drm_fb_helper_hotplug_event(priv->fbdev); | |
a2ca7789 | 28 | #endif |
c8afe684 RC |
29 | } |
30 | ||
31 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
32 | .fb_create = msm_framebuffer_create, | |
33 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 34 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 35 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
36 | }; |
37 | ||
871d812a | 38 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
39 | { |
40 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 41 | int idx = priv->num_mmus++; |
c8afe684 | 42 | |
871d812a | 43 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
44 | return -EINVAL; |
45 | ||
871d812a | 46 | priv->mmus[idx] = mmu; |
c8afe684 RC |
47 | |
48 | return idx; | |
49 | } | |
50 | ||
c8afe684 RC |
51 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
52 | static bool reglog = false; | |
53 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
54 | module_param(reglog, bool, 0600); | |
55 | #else | |
56 | #define reglog 0 | |
57 | #endif | |
58 | ||
e90dfec7 RC |
59 | #ifdef CONFIG_DRM_MSM_FBDEV |
60 | static bool fbdev = true; | |
61 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
62 | module_param(fbdev, bool, 0600); | |
63 | #endif | |
64 | ||
3a10ba8c | 65 | static char *vram = "16m"; |
871d812a RC |
66 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU"); |
67 | module_param(vram, charp, 0); | |
68 | ||
060530f1 RC |
69 | /* |
70 | * Util/helpers: | |
71 | */ | |
72 | ||
c8afe684 RC |
73 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
74 | const char *dbgname) | |
75 | { | |
76 | struct resource *res; | |
77 | unsigned long size; | |
78 | void __iomem *ptr; | |
79 | ||
80 | if (name) | |
81 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
82 | else | |
83 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84 | ||
85 | if (!res) { | |
86 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
87 | return ERR_PTR(-EINVAL); | |
88 | } | |
89 | ||
90 | size = resource_size(res); | |
91 | ||
92 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
93 | if (!ptr) { | |
94 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
95 | return ERR_PTR(-ENOMEM); | |
96 | } | |
97 | ||
98 | if (reglog) | |
fc99f97a | 99 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
100 | |
101 | return ptr; | |
102 | } | |
103 | ||
104 | void msm_writel(u32 data, void __iomem *addr) | |
105 | { | |
106 | if (reglog) | |
fc99f97a | 107 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
108 | writel(data, addr); |
109 | } | |
110 | ||
111 | u32 msm_readl(const void __iomem *addr) | |
112 | { | |
113 | u32 val = readl(addr); | |
114 | if (reglog) | |
fc99f97a | 115 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
c8afe684 RC |
116 | return val; |
117 | } | |
118 | ||
119 | /* | |
120 | * DRM operations: | |
121 | */ | |
122 | ||
123 | static int msm_unload(struct drm_device *dev) | |
124 | { | |
125 | struct msm_drm_private *priv = dev->dev_private; | |
126 | struct msm_kms *kms = priv->kms; | |
7198e6b0 | 127 | struct msm_gpu *gpu = priv->gpu; |
c8afe684 RC |
128 | |
129 | drm_kms_helper_poll_fini(dev); | |
130 | drm_mode_config_cleanup(dev); | |
131 | drm_vblank_cleanup(dev); | |
132 | ||
133 | pm_runtime_get_sync(dev->dev); | |
134 | drm_irq_uninstall(dev); | |
135 | pm_runtime_put_sync(dev->dev); | |
136 | ||
137 | flush_workqueue(priv->wq); | |
138 | destroy_workqueue(priv->wq); | |
139 | ||
140 | if (kms) { | |
141 | pm_runtime_disable(dev->dev); | |
142 | kms->funcs->destroy(kms); | |
143 | } | |
144 | ||
7198e6b0 RC |
145 | if (gpu) { |
146 | mutex_lock(&dev->struct_mutex); | |
147 | gpu->funcs->pm_suspend(gpu); | |
7198e6b0 | 148 | mutex_unlock(&dev->struct_mutex); |
774449eb | 149 | gpu->funcs->destroy(gpu); |
7198e6b0 | 150 | } |
c8afe684 | 151 | |
871d812a RC |
152 | if (priv->vram.paddr) { |
153 | DEFINE_DMA_ATTRS(attrs); | |
154 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
155 | drm_mm_takedown(&priv->vram.mm); | |
156 | dma_free_attrs(dev->dev, priv->vram.size, NULL, | |
157 | priv->vram.paddr, &attrs); | |
158 | } | |
159 | ||
060530f1 RC |
160 | component_unbind_all(dev->dev, dev); |
161 | ||
c8afe684 RC |
162 | dev->dev_private = NULL; |
163 | ||
164 | kfree(priv); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
06c0dd96 RC |
169 | static int get_mdp_ver(struct platform_device *pdev) |
170 | { | |
171 | #ifdef CONFIG_OF | |
370a4d8a | 172 | static const struct of_device_id match_types[] = { { |
06c0dd96 RC |
173 | .compatible = "qcom,mdss_mdp", |
174 | .data = (void *)5, | |
175 | }, { | |
176 | /* end node */ | |
177 | } }; | |
178 | struct device *dev = &pdev->dev; | |
179 | const struct of_device_id *match; | |
180 | match = of_match_node(match_types, dev->of_node); | |
181 | if (match) | |
fc99f97a | 182 | return (int)(unsigned long)match->data; |
06c0dd96 RC |
183 | #endif |
184 | return 4; | |
185 | } | |
186 | ||
072f1f91 RC |
187 | #include <linux/of_address.h> |
188 | ||
5bf9c0b6 | 189 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 190 | { |
5bf9c0b6 | 191 | struct msm_drm_private *priv = dev->dev_private; |
072f1f91 RC |
192 | unsigned long size = 0; |
193 | int ret = 0; | |
194 | ||
195 | #ifdef CONFIG_OF | |
196 | /* In the device-tree world, we could have a 'memory-region' | |
197 | * phandle, which gives us a link to our "vram". Allocating | |
198 | * is all nicely abstracted behind the dma api, but we need | |
199 | * to know the entire size to allocate it all in one go. There | |
200 | * are two cases: | |
201 | * 1) device with no IOMMU, in which case we need exclusive | |
202 | * access to a VRAM carveout big enough for all gpu | |
203 | * buffers | |
204 | * 2) device with IOMMU, but where the bootloader puts up | |
205 | * a splash screen. In this case, the VRAM carveout | |
206 | * need only be large enough for fbdev fb. But we need | |
207 | * exclusive access to the buffer to avoid the kernel | |
208 | * using those pages for other purposes (which appears | |
209 | * as corruption on screen before we have a chance to | |
210 | * load and do initial modeset) | |
211 | */ | |
212 | struct device_node *node; | |
213 | ||
214 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
215 | if (node) { | |
216 | struct resource r; | |
217 | ret = of_address_to_resource(node, 0, &r); | |
218 | if (ret) | |
219 | return ret; | |
220 | size = r.end - r.start; | |
fc99f97a | 221 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
072f1f91 RC |
222 | } else |
223 | #endif | |
c8afe684 | 224 | |
871d812a RC |
225 | /* if we have no IOMMU, then we need to use carveout allocator. |
226 | * Grab the entire CMA chunk carved out in early startup in | |
227 | * mach-msm: | |
228 | */ | |
229 | if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
230 | DRM_INFO("using %s VRAM carveout\n", vram); |
231 | size = memparse(vram, NULL); | |
232 | } | |
233 | ||
234 | if (size) { | |
871d812a | 235 | DEFINE_DMA_ATTRS(attrs); |
871d812a RC |
236 | void *p; |
237 | ||
871d812a RC |
238 | priv->vram.size = size; |
239 | ||
240 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
241 | ||
242 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
243 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
244 | ||
245 | /* note that for no-kernel-mapping, the vaddr returned | |
246 | * is bogus, but non-null if allocation succeeded: | |
247 | */ | |
248 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 249 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
250 | if (!p) { |
251 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
252 | priv->vram.paddr = 0; | |
5bf9c0b6 | 253 | return -ENOMEM; |
871d812a RC |
254 | } |
255 | ||
256 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
257 | (uint32_t)priv->vram.paddr, | |
258 | (uint32_t)(priv->vram.paddr + size)); | |
259 | } | |
260 | ||
072f1f91 | 261 | return ret; |
5bf9c0b6 RC |
262 | } |
263 | ||
264 | static int msm_load(struct drm_device *dev, unsigned long flags) | |
265 | { | |
266 | struct platform_device *pdev = dev->platformdev; | |
267 | struct msm_drm_private *priv; | |
268 | struct msm_kms *kms; | |
269 | int ret; | |
270 | ||
271 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
272 | if (!priv) { | |
273 | dev_err(dev->dev, "failed to allocate private data\n"); | |
274 | return -ENOMEM; | |
275 | } | |
276 | ||
277 | dev->dev_private = priv; | |
278 | ||
279 | priv->wq = alloc_ordered_workqueue("msm", 0); | |
280 | init_waitqueue_head(&priv->fence_event); | |
281 | init_waitqueue_head(&priv->pending_crtcs_event); | |
282 | ||
283 | INIT_LIST_HEAD(&priv->inactive_list); | |
284 | INIT_LIST_HEAD(&priv->fence_cbs); | |
285 | ||
286 | drm_mode_config_init(dev); | |
287 | ||
060530f1 RC |
288 | platform_set_drvdata(pdev, dev); |
289 | ||
290 | /* Bind all our sub-components: */ | |
291 | ret = component_bind_all(dev->dev, dev); | |
292 | if (ret) | |
293 | return ret; | |
294 | ||
13f15565 RC |
295 | ret = msm_init_vram(dev); |
296 | if (ret) | |
297 | goto fail; | |
298 | ||
06c0dd96 RC |
299 | switch (get_mdp_ver(pdev)) { |
300 | case 4: | |
301 | kms = mdp4_kms_init(dev); | |
302 | break; | |
303 | case 5: | |
304 | kms = mdp5_kms_init(dev); | |
305 | break; | |
306 | default: | |
307 | kms = ERR_PTR(-ENODEV); | |
308 | break; | |
309 | } | |
310 | ||
c8afe684 RC |
311 | if (IS_ERR(kms)) { |
312 | /* | |
313 | * NOTE: once we have GPU support, having no kms should not | |
314 | * be considered fatal.. ideally we would still support gpu | |
315 | * and (for example) use dmabuf/prime to share buffers with | |
316 | * imx drm driver on iMX5 | |
317 | */ | |
318 | dev_err(dev->dev, "failed to load kms\n"); | |
e4826a94 | 319 | ret = PTR_ERR(kms); |
c8afe684 RC |
320 | goto fail; |
321 | } | |
322 | ||
323 | priv->kms = kms; | |
324 | ||
325 | if (kms) { | |
326 | pm_runtime_enable(dev->dev); | |
327 | ret = kms->funcs->hw_init(kms); | |
328 | if (ret) { | |
329 | dev_err(dev->dev, "kms hw init failed: %d\n", ret); | |
330 | goto fail; | |
331 | } | |
332 | } | |
333 | ||
334 | dev->mode_config.min_width = 0; | |
335 | dev->mode_config.min_height = 0; | |
336 | dev->mode_config.max_width = 2048; | |
337 | dev->mode_config.max_height = 2048; | |
338 | dev->mode_config.funcs = &mode_config_funcs; | |
339 | ||
d65bd0e4 | 340 | ret = drm_vblank_init(dev, priv->num_crtcs); |
c8afe684 RC |
341 | if (ret < 0) { |
342 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
343 | goto fail; | |
344 | } | |
345 | ||
346 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 347 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
c8afe684 RC |
348 | pm_runtime_put_sync(dev->dev); |
349 | if (ret < 0) { | |
350 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
351 | goto fail; | |
352 | } | |
353 | ||
cf3a7e4c RC |
354 | drm_mode_config_reset(dev); |
355 | ||
c8afe684 | 356 | #ifdef CONFIG_DRM_MSM_FBDEV |
e90dfec7 RC |
357 | if (fbdev) |
358 | priv->fbdev = msm_fbdev_init(dev); | |
c8afe684 RC |
359 | #endif |
360 | ||
a7d3c950 RC |
361 | ret = msm_debugfs_late_init(dev); |
362 | if (ret) | |
363 | goto fail; | |
364 | ||
c8afe684 RC |
365 | drm_kms_helper_poll_init(dev); |
366 | ||
367 | return 0; | |
368 | ||
369 | fail: | |
370 | msm_unload(dev); | |
371 | return ret; | |
372 | } | |
373 | ||
7198e6b0 RC |
374 | static void load_gpu(struct drm_device *dev) |
375 | { | |
a1ad3523 | 376 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 377 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 378 | |
a1ad3523 RC |
379 | mutex_lock(&init_lock); |
380 | ||
e2550b7a RC |
381 | if (!priv->gpu) |
382 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 383 | |
a1ad3523 | 384 | mutex_unlock(&init_lock); |
7198e6b0 RC |
385 | } |
386 | ||
387 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
388 | { | |
389 | struct msm_file_private *ctx; | |
390 | ||
391 | /* For now, load gpu on open.. to avoid the requirement of having | |
392 | * firmware in the initrd. | |
393 | */ | |
394 | load_gpu(dev); | |
395 | ||
396 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
397 | if (!ctx) | |
398 | return -ENOMEM; | |
399 | ||
400 | file->driver_priv = ctx; | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
c8afe684 RC |
405 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
406 | { | |
407 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 408 | struct msm_file_private *ctx = file->driver_priv; |
c8afe684 | 409 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 410 | |
c8afe684 RC |
411 | if (kms) |
412 | kms->funcs->preclose(kms, file); | |
7198e6b0 RC |
413 | |
414 | mutex_lock(&dev->struct_mutex); | |
415 | if (ctx == priv->lastctx) | |
416 | priv->lastctx = NULL; | |
417 | mutex_unlock(&dev->struct_mutex); | |
418 | ||
419 | kfree(ctx); | |
c8afe684 RC |
420 | } |
421 | ||
422 | static void msm_lastclose(struct drm_device *dev) | |
423 | { | |
a2ca7789 | 424 | #ifdef CONFIG_DRM_MSM_FBDEV |
c8afe684 | 425 | struct msm_drm_private *priv = dev->dev_private; |
5ea1f752 RC |
426 | if (priv->fbdev) |
427 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
a2ca7789 | 428 | #endif |
c8afe684 RC |
429 | } |
430 | ||
e9f0d76f | 431 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
432 | { |
433 | struct drm_device *dev = arg; | |
434 | struct msm_drm_private *priv = dev->dev_private; | |
435 | struct msm_kms *kms = priv->kms; | |
436 | BUG_ON(!kms); | |
437 | return kms->funcs->irq(kms); | |
438 | } | |
439 | ||
440 | static void msm_irq_preinstall(struct drm_device *dev) | |
441 | { | |
442 | struct msm_drm_private *priv = dev->dev_private; | |
443 | struct msm_kms *kms = priv->kms; | |
444 | BUG_ON(!kms); | |
445 | kms->funcs->irq_preinstall(kms); | |
446 | } | |
447 | ||
448 | static int msm_irq_postinstall(struct drm_device *dev) | |
449 | { | |
450 | struct msm_drm_private *priv = dev->dev_private; | |
451 | struct msm_kms *kms = priv->kms; | |
452 | BUG_ON(!kms); | |
453 | return kms->funcs->irq_postinstall(kms); | |
454 | } | |
455 | ||
456 | static void msm_irq_uninstall(struct drm_device *dev) | |
457 | { | |
458 | struct msm_drm_private *priv = dev->dev_private; | |
459 | struct msm_kms *kms = priv->kms; | |
460 | BUG_ON(!kms); | |
461 | kms->funcs->irq_uninstall(kms); | |
462 | } | |
463 | ||
464 | static int msm_enable_vblank(struct drm_device *dev, int crtc_id) | |
465 | { | |
466 | struct msm_drm_private *priv = dev->dev_private; | |
467 | struct msm_kms *kms = priv->kms; | |
468 | if (!kms) | |
469 | return -ENXIO; | |
470 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
471 | return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]); | |
472 | } | |
473 | ||
474 | static void msm_disable_vblank(struct drm_device *dev, int crtc_id) | |
475 | { | |
476 | struct msm_drm_private *priv = dev->dev_private; | |
477 | struct msm_kms *kms = priv->kms; | |
478 | if (!kms) | |
479 | return; | |
480 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
481 | kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]); | |
482 | } | |
483 | ||
484 | /* | |
485 | * DRM debugfs: | |
486 | */ | |
487 | ||
488 | #ifdef CONFIG_DEBUG_FS | |
7198e6b0 RC |
489 | static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) |
490 | { | |
491 | struct msm_drm_private *priv = dev->dev_private; | |
492 | struct msm_gpu *gpu = priv->gpu; | |
493 | ||
494 | if (gpu) { | |
495 | seq_printf(m, "%s Status:\n", gpu->name); | |
496 | gpu->funcs->show(gpu, m); | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
c8afe684 RC |
502 | static int msm_gem_show(struct drm_device *dev, struct seq_file *m) |
503 | { | |
504 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
505 | struct msm_gpu *gpu = priv->gpu; |
506 | ||
507 | if (gpu) { | |
508 | seq_printf(m, "Active Objects (%s):\n", gpu->name); | |
509 | msm_gem_describe_objects(&gpu->active_list, m); | |
510 | } | |
c8afe684 | 511 | |
7198e6b0 | 512 | seq_printf(m, "Inactive Objects:\n"); |
c8afe684 RC |
513 | msm_gem_describe_objects(&priv->inactive_list, m); |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static int msm_mm_show(struct drm_device *dev, struct seq_file *m) | |
519 | { | |
b04a5906 | 520 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
c8afe684 RC |
521 | } |
522 | ||
523 | static int msm_fb_show(struct drm_device *dev, struct seq_file *m) | |
524 | { | |
525 | struct msm_drm_private *priv = dev->dev_private; | |
526 | struct drm_framebuffer *fb, *fbdev_fb = NULL; | |
527 | ||
528 | if (priv->fbdev) { | |
529 | seq_printf(m, "fbcon "); | |
530 | fbdev_fb = priv->fbdev->fb; | |
531 | msm_framebuffer_describe(fbdev_fb, m); | |
532 | } | |
533 | ||
534 | mutex_lock(&dev->mode_config.fb_lock); | |
535 | list_for_each_entry(fb, &dev->mode_config.fb_list, head) { | |
536 | if (fb == fbdev_fb) | |
537 | continue; | |
538 | ||
539 | seq_printf(m, "user "); | |
540 | msm_framebuffer_describe(fb, m); | |
541 | } | |
542 | mutex_unlock(&dev->mode_config.fb_lock); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static int show_locked(struct seq_file *m, void *arg) | |
548 | { | |
549 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
550 | struct drm_device *dev = node->minor->dev; | |
551 | int (*show)(struct drm_device *dev, struct seq_file *m) = | |
552 | node->info_ent->data; | |
553 | int ret; | |
554 | ||
555 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
556 | if (ret) | |
557 | return ret; | |
558 | ||
559 | ret = show(dev, m); | |
560 | ||
561 | mutex_unlock(&dev->struct_mutex); | |
562 | ||
563 | return ret; | |
564 | } | |
565 | ||
566 | static struct drm_info_list msm_debugfs_list[] = { | |
7198e6b0 | 567 | {"gpu", show_locked, 0, msm_gpu_show}, |
c8afe684 RC |
568 | {"gem", show_locked, 0, msm_gem_show}, |
569 | { "mm", show_locked, 0, msm_mm_show }, | |
570 | { "fb", show_locked, 0, msm_fb_show }, | |
571 | }; | |
572 | ||
a7d3c950 RC |
573 | static int late_init_minor(struct drm_minor *minor) |
574 | { | |
575 | int ret; | |
576 | ||
577 | if (!minor) | |
578 | return 0; | |
579 | ||
580 | ret = msm_rd_debugfs_init(minor); | |
581 | if (ret) { | |
582 | dev_err(minor->dev->dev, "could not install rd debugfs\n"); | |
583 | return ret; | |
584 | } | |
585 | ||
70c70f09 RC |
586 | ret = msm_perf_debugfs_init(minor); |
587 | if (ret) { | |
588 | dev_err(minor->dev->dev, "could not install perf debugfs\n"); | |
589 | return ret; | |
590 | } | |
591 | ||
a7d3c950 RC |
592 | return 0; |
593 | } | |
594 | ||
595 | int msm_debugfs_late_init(struct drm_device *dev) | |
596 | { | |
597 | int ret; | |
598 | ret = late_init_minor(dev->primary); | |
599 | if (ret) | |
600 | return ret; | |
601 | ret = late_init_minor(dev->render); | |
602 | if (ret) | |
603 | return ret; | |
604 | ret = late_init_minor(dev->control); | |
605 | return ret; | |
606 | } | |
607 | ||
c8afe684 RC |
608 | static int msm_debugfs_init(struct drm_minor *minor) |
609 | { | |
610 | struct drm_device *dev = minor->dev; | |
611 | int ret; | |
612 | ||
613 | ret = drm_debugfs_create_files(msm_debugfs_list, | |
614 | ARRAY_SIZE(msm_debugfs_list), | |
615 | minor->debugfs_root, minor); | |
616 | ||
617 | if (ret) { | |
618 | dev_err(dev->dev, "could not install msm_debugfs_list\n"); | |
619 | return ret; | |
620 | } | |
621 | ||
a7d3c950 | 622 | return 0; |
c8afe684 RC |
623 | } |
624 | ||
625 | static void msm_debugfs_cleanup(struct drm_minor *minor) | |
626 | { | |
627 | drm_debugfs_remove_files(msm_debugfs_list, | |
628 | ARRAY_SIZE(msm_debugfs_list), minor); | |
a7d3c950 RC |
629 | if (!minor->dev->dev_private) |
630 | return; | |
631 | msm_rd_debugfs_cleanup(minor); | |
70c70f09 | 632 | msm_perf_debugfs_cleanup(minor); |
c8afe684 RC |
633 | } |
634 | #endif | |
635 | ||
7198e6b0 RC |
636 | /* |
637 | * Fences: | |
638 | */ | |
639 | ||
99fc1bc4 WX |
640 | int msm_wait_fence(struct drm_device *dev, uint32_t fence, |
641 | ktime_t *timeout , bool interruptible) | |
7198e6b0 RC |
642 | { |
643 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
644 | int ret; |
645 | ||
f816f272 RC |
646 | if (!priv->gpu) |
647 | return 0; | |
648 | ||
649 | if (fence > priv->gpu->submitted_fence) { | |
650 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
651 | fence, priv->gpu->submitted_fence); | |
652 | return -EINVAL; | |
653 | } | |
654 | ||
655 | if (!timeout) { | |
656 | /* no-wait: */ | |
657 | ret = fence_completed(dev, fence) ? 0 : -EBUSY; | |
658 | } else { | |
56c2da83 | 659 | ktime_t now = ktime_get(); |
f816f272 RC |
660 | unsigned long remaining_jiffies; |
661 | ||
56c2da83 | 662 | if (ktime_compare(*timeout, now) < 0) { |
f816f272 | 663 | remaining_jiffies = 0; |
56c2da83 RC |
664 | } else { |
665 | ktime_t rem = ktime_sub(*timeout, now); | |
666 | struct timespec ts = ktime_to_timespec(rem); | |
667 | remaining_jiffies = timespec_to_jiffies(&ts); | |
668 | } | |
f816f272 | 669 | |
99fc1bc4 WX |
670 | if (interruptible) |
671 | ret = wait_event_interruptible_timeout(priv->fence_event, | |
672 | fence_completed(dev, fence), | |
673 | remaining_jiffies); | |
674 | else | |
675 | ret = wait_event_timeout(priv->fence_event, | |
f816f272 RC |
676 | fence_completed(dev, fence), |
677 | remaining_jiffies); | |
678 | ||
679 | if (ret == 0) { | |
680 | DBG("timeout waiting for fence: %u (completed: %u)", | |
681 | fence, priv->completed_fence); | |
682 | ret = -ETIMEDOUT; | |
683 | } else if (ret != -ERESTARTSYS) { | |
684 | ret = 0; | |
685 | } | |
7198e6b0 RC |
686 | } |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
69193e50 RC |
691 | int msm_queue_fence_cb(struct drm_device *dev, |
692 | struct msm_fence_cb *cb, uint32_t fence) | |
693 | { | |
694 | struct msm_drm_private *priv = dev->dev_private; | |
695 | int ret = 0; | |
696 | ||
697 | mutex_lock(&dev->struct_mutex); | |
698 | if (!list_empty(&cb->work.entry)) { | |
699 | ret = -EINVAL; | |
700 | } else if (fence > priv->completed_fence) { | |
701 | cb->fence = fence; | |
702 | list_add_tail(&cb->work.entry, &priv->fence_cbs); | |
703 | } else { | |
704 | queue_work(priv->wq, &cb->work); | |
705 | } | |
706 | mutex_unlock(&dev->struct_mutex); | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
edd4fc63 | 711 | /* called from workqueue */ |
7198e6b0 RC |
712 | void msm_update_fence(struct drm_device *dev, uint32_t fence) |
713 | { | |
714 | struct msm_drm_private *priv = dev->dev_private; | |
715 | ||
edd4fc63 RC |
716 | mutex_lock(&dev->struct_mutex); |
717 | priv->completed_fence = max(fence, priv->completed_fence); | |
718 | ||
719 | while (!list_empty(&priv->fence_cbs)) { | |
720 | struct msm_fence_cb *cb; | |
721 | ||
722 | cb = list_first_entry(&priv->fence_cbs, | |
723 | struct msm_fence_cb, work.entry); | |
724 | ||
725 | if (cb->fence > priv->completed_fence) | |
726 | break; | |
727 | ||
728 | list_del_init(&cb->work.entry); | |
729 | queue_work(priv->wq, &cb->work); | |
7198e6b0 | 730 | } |
edd4fc63 RC |
731 | |
732 | mutex_unlock(&dev->struct_mutex); | |
733 | ||
734 | wake_up_all(&priv->fence_event); | |
735 | } | |
736 | ||
737 | void __msm_fence_worker(struct work_struct *work) | |
738 | { | |
739 | struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work); | |
740 | cb->func(cb); | |
7198e6b0 RC |
741 | } |
742 | ||
743 | /* | |
744 | * DRM ioctls: | |
745 | */ | |
746 | ||
747 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
748 | struct drm_file *file) | |
749 | { | |
750 | struct msm_drm_private *priv = dev->dev_private; | |
751 | struct drm_msm_param *args = data; | |
752 | struct msm_gpu *gpu; | |
753 | ||
754 | /* for now, we just have 3d pipe.. eventually this would need to | |
755 | * be more clever to dispatch to appropriate gpu module: | |
756 | */ | |
757 | if (args->pipe != MSM_PIPE_3D0) | |
758 | return -EINVAL; | |
759 | ||
760 | gpu = priv->gpu; | |
761 | ||
762 | if (!gpu) | |
763 | return -ENXIO; | |
764 | ||
765 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
766 | } | |
767 | ||
768 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
769 | struct drm_file *file) | |
770 | { | |
771 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
772 | |
773 | if (args->flags & ~MSM_BO_FLAGS) { | |
774 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
775 | return -EINVAL; | |
776 | } | |
777 | ||
7198e6b0 RC |
778 | return msm_gem_new_handle(dev, file, args->size, |
779 | args->flags, &args->handle); | |
780 | } | |
781 | ||
56c2da83 RC |
782 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
783 | { | |
784 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
785 | } | |
7198e6b0 RC |
786 | |
787 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
788 | struct drm_file *file) | |
789 | { | |
790 | struct drm_msm_gem_cpu_prep *args = data; | |
791 | struct drm_gem_object *obj; | |
56c2da83 | 792 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
793 | int ret; |
794 | ||
93ddb0d3 RC |
795 | if (args->op & ~MSM_PREP_FLAGS) { |
796 | DRM_ERROR("invalid op: %08x\n", args->op); | |
797 | return -EINVAL; | |
798 | } | |
799 | ||
7198e6b0 RC |
800 | obj = drm_gem_object_lookup(dev, file, args->handle); |
801 | if (!obj) | |
802 | return -ENOENT; | |
803 | ||
56c2da83 | 804 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
805 | |
806 | drm_gem_object_unreference_unlocked(obj); | |
807 | ||
808 | return ret; | |
809 | } | |
810 | ||
811 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
812 | struct drm_file *file) | |
813 | { | |
814 | struct drm_msm_gem_cpu_fini *args = data; | |
815 | struct drm_gem_object *obj; | |
816 | int ret; | |
817 | ||
818 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
819 | if (!obj) | |
820 | return -ENOENT; | |
821 | ||
822 | ret = msm_gem_cpu_fini(obj); | |
823 | ||
824 | drm_gem_object_unreference_unlocked(obj); | |
825 | ||
826 | return ret; | |
827 | } | |
828 | ||
829 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
830 | struct drm_file *file) | |
831 | { | |
832 | struct drm_msm_gem_info *args = data; | |
833 | struct drm_gem_object *obj; | |
834 | int ret = 0; | |
835 | ||
836 | if (args->pad) | |
837 | return -EINVAL; | |
838 | ||
839 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
840 | if (!obj) | |
841 | return -ENOENT; | |
842 | ||
843 | args->offset = msm_gem_mmap_offset(obj); | |
844 | ||
845 | drm_gem_object_unreference_unlocked(obj); | |
846 | ||
847 | return ret; | |
848 | } | |
849 | ||
850 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
851 | struct drm_file *file) | |
852 | { | |
853 | struct drm_msm_wait_fence *args = data; | |
56c2da83 | 854 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
855 | |
856 | if (args->pad) { | |
857 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
99fc1bc4 | 861 | return msm_wait_fence(dev, args->fence, &timeout, true); |
7198e6b0 RC |
862 | } |
863 | ||
864 | static const struct drm_ioctl_desc msm_ioctls[] = { | |
b4b15c86 RC |
865 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
866 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
867 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
868 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
869 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
870 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
871 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
7198e6b0 RC |
872 | }; |
873 | ||
c8afe684 RC |
874 | static const struct vm_operations_struct vm_ops = { |
875 | .fault = msm_gem_fault, | |
876 | .open = drm_gem_vm_open, | |
877 | .close = drm_gem_vm_close, | |
878 | }; | |
879 | ||
880 | static const struct file_operations fops = { | |
881 | .owner = THIS_MODULE, | |
882 | .open = drm_open, | |
883 | .release = drm_release, | |
884 | .unlocked_ioctl = drm_ioctl, | |
885 | #ifdef CONFIG_COMPAT | |
886 | .compat_ioctl = drm_compat_ioctl, | |
887 | #endif | |
888 | .poll = drm_poll, | |
889 | .read = drm_read, | |
890 | .llseek = no_llseek, | |
891 | .mmap = msm_gem_mmap, | |
892 | }; | |
893 | ||
894 | static struct drm_driver msm_driver = { | |
05b84911 RC |
895 | .driver_features = DRIVER_HAVE_IRQ | |
896 | DRIVER_GEM | | |
897 | DRIVER_PRIME | | |
b4b15c86 | 898 | DRIVER_RENDER | |
a5436e1d | 899 | DRIVER_ATOMIC | |
05b84911 | 900 | DRIVER_MODESET, |
c8afe684 RC |
901 | .load = msm_load, |
902 | .unload = msm_unload, | |
7198e6b0 | 903 | .open = msm_open, |
c8afe684 RC |
904 | .preclose = msm_preclose, |
905 | .lastclose = msm_lastclose, | |
915b4d11 | 906 | .set_busid = drm_platform_set_busid, |
c8afe684 RC |
907 | .irq_handler = msm_irq, |
908 | .irq_preinstall = msm_irq_preinstall, | |
909 | .irq_postinstall = msm_irq_postinstall, | |
910 | .irq_uninstall = msm_irq_uninstall, | |
911 | .get_vblank_counter = drm_vblank_count, | |
912 | .enable_vblank = msm_enable_vblank, | |
913 | .disable_vblank = msm_disable_vblank, | |
914 | .gem_free_object = msm_gem_free_object, | |
915 | .gem_vm_ops = &vm_ops, | |
916 | .dumb_create = msm_gem_dumb_create, | |
917 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 918 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
919 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
920 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
921 | .gem_prime_export = drm_gem_prime_export, | |
922 | .gem_prime_import = drm_gem_prime_import, | |
923 | .gem_prime_pin = msm_gem_prime_pin, | |
924 | .gem_prime_unpin = msm_gem_prime_unpin, | |
925 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
926 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
927 | .gem_prime_vmap = msm_gem_prime_vmap, | |
928 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 929 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
930 | #ifdef CONFIG_DEBUG_FS |
931 | .debugfs_init = msm_debugfs_init, | |
932 | .debugfs_cleanup = msm_debugfs_cleanup, | |
933 | #endif | |
7198e6b0 RC |
934 | .ioctls = msm_ioctls, |
935 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
936 | .fops = &fops, |
937 | .name = "msm", | |
938 | .desc = "MSM Snapdragon DRM", | |
939 | .date = "20130625", | |
940 | .major = 1, | |
941 | .minor = 0, | |
942 | }; | |
943 | ||
944 | #ifdef CONFIG_PM_SLEEP | |
945 | static int msm_pm_suspend(struct device *dev) | |
946 | { | |
947 | struct drm_device *ddev = dev_get_drvdata(dev); | |
948 | ||
949 | drm_kms_helper_poll_disable(ddev); | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static int msm_pm_resume(struct device *dev) | |
955 | { | |
956 | struct drm_device *ddev = dev_get_drvdata(dev); | |
957 | ||
958 | drm_kms_helper_poll_enable(ddev); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | #endif | |
963 | ||
964 | static const struct dev_pm_ops msm_pm_ops = { | |
965 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
966 | }; | |
967 | ||
060530f1 RC |
968 | /* |
969 | * Componentized driver support: | |
970 | */ | |
971 | ||
972 | #ifdef CONFIG_OF | |
973 | /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx | |
974 | * (or probably any other).. so probably some room for some helpers | |
975 | */ | |
976 | static int compare_of(struct device *dev, void *data) | |
977 | { | |
978 | return dev->of_node == data; | |
979 | } | |
41e69778 RC |
980 | |
981 | static int add_components(struct device *dev, struct component_match **matchptr, | |
982 | const char *name) | |
983 | { | |
984 | struct device_node *np = dev->of_node; | |
985 | unsigned i; | |
986 | ||
987 | for (i = 0; ; i++) { | |
988 | struct device_node *node; | |
989 | ||
990 | node = of_parse_phandle(np, name, i); | |
991 | if (!node) | |
992 | break; | |
993 | ||
994 | component_match_add(dev, matchptr, compare_of, node); | |
995 | } | |
996 | ||
997 | return 0; | |
998 | } | |
84448288 RK |
999 | #else |
1000 | static int compare_dev(struct device *dev, void *data) | |
1001 | { | |
1002 | return dev == data; | |
1003 | } | |
1004 | #endif | |
1005 | ||
1006 | static int msm_drm_bind(struct device *dev) | |
1007 | { | |
1008 | return drm_platform_init(&msm_driver, to_platform_device(dev)); | |
1009 | } | |
1010 | ||
1011 | static void msm_drm_unbind(struct device *dev) | |
1012 | { | |
1013 | drm_put_dev(platform_get_drvdata(to_platform_device(dev))); | |
1014 | } | |
1015 | ||
1016 | static const struct component_master_ops msm_drm_ops = { | |
1017 | .bind = msm_drm_bind, | |
1018 | .unbind = msm_drm_unbind, | |
1019 | }; | |
1020 | ||
1021 | /* | |
1022 | * Platform driver: | |
1023 | */ | |
060530f1 | 1024 | |
84448288 | 1025 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1026 | { |
84448288 RK |
1027 | struct component_match *match = NULL; |
1028 | #ifdef CONFIG_OF | |
41e69778 RC |
1029 | add_components(&pdev->dev, &match, "connectors"); |
1030 | add_components(&pdev->dev, &match, "gpus"); | |
060530f1 | 1031 | #else |
060530f1 RC |
1032 | /* For non-DT case, it kinda sucks. We don't actually have a way |
1033 | * to know whether or not we are waiting for certain devices (or if | |
1034 | * they are simply not present). But for non-DT we only need to | |
1035 | * care about apq8064/apq8060/etc (all mdp4/a3xx): | |
1036 | */ | |
1037 | static const char *devnames[] = { | |
1038 | "hdmi_msm.0", "kgsl-3d0.0", | |
1039 | }; | |
1040 | int i; | |
1041 | ||
1042 | DBG("Adding components.."); | |
1043 | ||
1044 | for (i = 0; i < ARRAY_SIZE(devnames); i++) { | |
1045 | struct device *dev; | |
060530f1 RC |
1046 | |
1047 | dev = bus_find_device_by_name(&platform_bus_type, | |
1048 | NULL, devnames[i]); | |
1049 | if (!dev) { | |
12313c2a | 1050 | dev_info(&pdev->dev, "still waiting for %s\n", devnames[i]); |
060530f1 RC |
1051 | return -EPROBE_DEFER; |
1052 | } | |
1053 | ||
84448288 | 1054 | component_match_add(&pdev->dev, &match, compare_dev, dev); |
060530f1 | 1055 | } |
060530f1 RC |
1056 | #endif |
1057 | ||
871d812a | 1058 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 1059 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1060 | } |
1061 | ||
1062 | static int msm_pdev_remove(struct platform_device *pdev) | |
1063 | { | |
060530f1 | 1064 | component_master_del(&pdev->dev, &msm_drm_ops); |
c8afe684 RC |
1065 | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static const struct platform_device_id msm_id[] = { | |
1070 | { "mdp", 0 }, | |
1071 | { } | |
1072 | }; | |
1073 | ||
06c0dd96 | 1074 | static const struct of_device_id dt_match[] = { |
41e69778 RC |
1075 | { .compatible = "qcom,mdp" }, /* mdp4 */ |
1076 | { .compatible = "qcom,mdss_mdp" }, /* mdp5 */ | |
06c0dd96 RC |
1077 | {} |
1078 | }; | |
1079 | MODULE_DEVICE_TABLE(of, dt_match); | |
1080 | ||
c8afe684 RC |
1081 | static struct platform_driver msm_platform_driver = { |
1082 | .probe = msm_pdev_probe, | |
1083 | .remove = msm_pdev_remove, | |
1084 | .driver = { | |
c8afe684 | 1085 | .name = "msm", |
06c0dd96 | 1086 | .of_match_table = dt_match, |
c8afe684 RC |
1087 | .pm = &msm_pm_ops, |
1088 | }, | |
1089 | .id_table = msm_id, | |
1090 | }; | |
1091 | ||
1092 | static int __init msm_drm_register(void) | |
1093 | { | |
1094 | DBG("init"); | |
d5af49c9 | 1095 | msm_dsi_register(); |
00453981 | 1096 | msm_edp_register(); |
c8afe684 | 1097 | hdmi_register(); |
bfd28b13 | 1098 | adreno_register(); |
c8afe684 RC |
1099 | return platform_driver_register(&msm_platform_driver); |
1100 | } | |
1101 | ||
1102 | static void __exit msm_drm_unregister(void) | |
1103 | { | |
1104 | DBG("fini"); | |
1105 | platform_driver_unregister(&msm_platform_driver); | |
1106 | hdmi_unregister(); | |
bfd28b13 | 1107 | adreno_unregister(); |
00453981 | 1108 | msm_edp_unregister(); |
d5af49c9 | 1109 | msm_dsi_unregister(); |
c8afe684 RC |
1110 | } |
1111 | ||
1112 | module_init(msm_drm_register); | |
1113 | module_exit(msm_drm_unregister); | |
1114 | ||
1115 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1116 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1117 | MODULE_LICENSE("GPL"); |