Commit | Line | Data |
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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
edcd60ce | 19 | #include "msm_debugfs.h" |
fde5de6c | 20 | #include "msm_fence.h" |
7198e6b0 | 21 | #include "msm_gpu.h" |
dd2da6e3 | 22 | #include "msm_kms.h" |
c8afe684 | 23 | |
a8d854c1 RC |
24 | |
25 | /* | |
26 | * MSM driver version: | |
27 | * - 1.0.0 - initial interface | |
28 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers | |
29 | */ | |
30 | #define MSM_VERSION_MAJOR 1 | |
31 | #define MSM_VERSION_MINOR 1 | |
32 | #define MSM_VERSION_PATCHLEVEL 0 | |
33 | ||
c8afe684 RC |
34 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
35 | { | |
36 | struct msm_drm_private *priv = dev->dev_private; | |
37 | if (priv->fbdev) | |
38 | drm_fb_helper_hotplug_event(priv->fbdev); | |
39 | } | |
40 | ||
41 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
42 | .fb_create = msm_framebuffer_create, | |
43 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 44 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 45 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
46 | }; |
47 | ||
871d812a | 48 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
49 | { |
50 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 51 | int idx = priv->num_mmus++; |
c8afe684 | 52 | |
871d812a | 53 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
54 | return -EINVAL; |
55 | ||
871d812a | 56 | priv->mmus[idx] = mmu; |
c8afe684 RC |
57 | |
58 | return idx; | |
59 | } | |
60 | ||
c8afe684 RC |
61 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
62 | static bool reglog = false; | |
63 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
64 | module_param(reglog, bool, 0600); | |
65 | #else | |
66 | #define reglog 0 | |
67 | #endif | |
68 | ||
a9ee34b7 | 69 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
70 | static bool fbdev = true; |
71 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
72 | module_param(fbdev, bool, 0600); | |
73 | #endif | |
74 | ||
3a10ba8c | 75 | static char *vram = "16m"; |
4313c744 | 76 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
871d812a RC |
77 | module_param(vram, charp, 0); |
78 | ||
060530f1 RC |
79 | /* |
80 | * Util/helpers: | |
81 | */ | |
82 | ||
c8afe684 RC |
83 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
84 | const char *dbgname) | |
85 | { | |
86 | struct resource *res; | |
87 | unsigned long size; | |
88 | void __iomem *ptr; | |
89 | ||
90 | if (name) | |
91 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
92 | else | |
93 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
94 | ||
95 | if (!res) { | |
96 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
97 | return ERR_PTR(-EINVAL); | |
98 | } | |
99 | ||
100 | size = resource_size(res); | |
101 | ||
102 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
103 | if (!ptr) { | |
104 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
105 | return ERR_PTR(-ENOMEM); | |
106 | } | |
107 | ||
108 | if (reglog) | |
fc99f97a | 109 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
110 | |
111 | return ptr; | |
112 | } | |
113 | ||
114 | void msm_writel(u32 data, void __iomem *addr) | |
115 | { | |
116 | if (reglog) | |
fc99f97a | 117 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
118 | writel(data, addr); |
119 | } | |
120 | ||
121 | u32 msm_readl(const void __iomem *addr) | |
122 | { | |
123 | u32 val = readl(addr); | |
124 | if (reglog) | |
fc99f97a | 125 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
c8afe684 RC |
126 | return val; |
127 | } | |
128 | ||
78b1d470 HL |
129 | struct vblank_event { |
130 | struct list_head node; | |
131 | int crtc_id; | |
132 | bool enable; | |
133 | }; | |
134 | ||
135 | static void vblank_ctrl_worker(struct work_struct *work) | |
136 | { | |
137 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, | |
138 | struct msm_vblank_ctrl, work); | |
139 | struct msm_drm_private *priv = container_of(vbl_ctrl, | |
140 | struct msm_drm_private, vblank_ctrl); | |
141 | struct msm_kms *kms = priv->kms; | |
142 | struct vblank_event *vbl_ev, *tmp; | |
143 | unsigned long flags; | |
144 | ||
145 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
146 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
147 | list_del(&vbl_ev->node); | |
148 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
149 | ||
150 | if (vbl_ev->enable) | |
151 | kms->funcs->enable_vblank(kms, | |
152 | priv->crtcs[vbl_ev->crtc_id]); | |
153 | else | |
154 | kms->funcs->disable_vblank(kms, | |
155 | priv->crtcs[vbl_ev->crtc_id]); | |
156 | ||
157 | kfree(vbl_ev); | |
158 | ||
159 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
160 | } | |
161 | ||
162 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
163 | } | |
164 | ||
165 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
166 | int crtc_id, bool enable) | |
167 | { | |
168 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; | |
169 | struct vblank_event *vbl_ev; | |
170 | unsigned long flags; | |
171 | ||
172 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); | |
173 | if (!vbl_ev) | |
174 | return -ENOMEM; | |
175 | ||
176 | vbl_ev->crtc_id = crtc_id; | |
177 | vbl_ev->enable = enable; | |
178 | ||
179 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
180 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); | |
181 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
182 | ||
183 | queue_work(priv->wq, &vbl_ctrl->work); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
2b669875 | 188 | static int msm_drm_uninit(struct device *dev) |
c8afe684 | 189 | { |
2b669875 AT |
190 | struct platform_device *pdev = to_platform_device(dev); |
191 | struct drm_device *ddev = platform_get_drvdata(pdev); | |
192 | struct msm_drm_private *priv = ddev->dev_private; | |
c8afe684 | 193 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 194 | struct msm_gpu *gpu = priv->gpu; |
78b1d470 HL |
195 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
196 | struct vblank_event *vbl_ev, *tmp; | |
197 | ||
198 | /* We must cancel and cleanup any pending vblank enable/disable | |
199 | * work before drm_irq_uninstall() to avoid work re-enabling an | |
200 | * irq after uninstall has disabled it. | |
201 | */ | |
202 | cancel_work_sync(&vbl_ctrl->work); | |
203 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
204 | list_del(&vbl_ev->node); | |
205 | kfree(vbl_ev); | |
206 | } | |
c8afe684 | 207 | |
68209390 RC |
208 | msm_gem_shrinker_cleanup(ddev); |
209 | ||
2b669875 AT |
210 | drm_kms_helper_poll_fini(ddev); |
211 | ||
2b669875 | 212 | drm_dev_unregister(ddev); |
8208ed93 | 213 | |
1aaa57f5 AT |
214 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
215 | if (fbdev && priv->fbdev) | |
2b669875 | 216 | msm_fbdev_free(ddev); |
1aaa57f5 | 217 | #endif |
2b669875 | 218 | drm_mode_config_cleanup(ddev); |
c8afe684 | 219 | |
2b669875 AT |
220 | pm_runtime_get_sync(dev); |
221 | drm_irq_uninstall(ddev); | |
222 | pm_runtime_put_sync(dev); | |
c8afe684 RC |
223 | |
224 | flush_workqueue(priv->wq); | |
225 | destroy_workqueue(priv->wq); | |
226 | ||
ba00c3f2 RC |
227 | flush_workqueue(priv->atomic_wq); |
228 | destroy_workqueue(priv->atomic_wq); | |
229 | ||
cd792726 | 230 | if (kms) |
c8afe684 | 231 | kms->funcs->destroy(kms); |
c8afe684 | 232 | |
7198e6b0 | 233 | if (gpu) { |
2b669875 | 234 | mutex_lock(&ddev->struct_mutex); |
7198e6b0 | 235 | gpu->funcs->pm_suspend(gpu); |
2b669875 | 236 | mutex_unlock(&ddev->struct_mutex); |
774449eb | 237 | gpu->funcs->destroy(gpu); |
7198e6b0 | 238 | } |
c8afe684 | 239 | |
871d812a | 240 | if (priv->vram.paddr) { |
00085f1e | 241 | unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
871d812a | 242 | drm_mm_takedown(&priv->vram.mm); |
2b669875 | 243 | dma_free_attrs(dev, priv->vram.size, NULL, |
00085f1e | 244 | priv->vram.paddr, attrs); |
871d812a RC |
245 | } |
246 | ||
2b669875 | 247 | component_unbind_all(dev, ddev); |
060530f1 | 248 | |
0a6030d2 AT |
249 | msm_mdss_destroy(ddev); |
250 | ||
2b669875 AT |
251 | ddev->dev_private = NULL; |
252 | drm_dev_unref(ddev); | |
c8afe684 RC |
253 | |
254 | kfree(priv); | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
06c0dd96 RC |
259 | static int get_mdp_ver(struct platform_device *pdev) |
260 | { | |
06c0dd96 | 261 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
262 | |
263 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
264 | } |
265 | ||
072f1f91 RC |
266 | #include <linux/of_address.h> |
267 | ||
5bf9c0b6 | 268 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 269 | { |
5bf9c0b6 | 270 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 271 | struct device_node *node; |
072f1f91 RC |
272 | unsigned long size = 0; |
273 | int ret = 0; | |
274 | ||
072f1f91 RC |
275 | /* In the device-tree world, we could have a 'memory-region' |
276 | * phandle, which gives us a link to our "vram". Allocating | |
277 | * is all nicely abstracted behind the dma api, but we need | |
278 | * to know the entire size to allocate it all in one go. There | |
279 | * are two cases: | |
280 | * 1) device with no IOMMU, in which case we need exclusive | |
281 | * access to a VRAM carveout big enough for all gpu | |
282 | * buffers | |
283 | * 2) device with IOMMU, but where the bootloader puts up | |
284 | * a splash screen. In this case, the VRAM carveout | |
285 | * need only be large enough for fbdev fb. But we need | |
286 | * exclusive access to the buffer to avoid the kernel | |
287 | * using those pages for other purposes (which appears | |
288 | * as corruption on screen before we have a chance to | |
289 | * load and do initial modeset) | |
290 | */ | |
072f1f91 RC |
291 | |
292 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
293 | if (node) { | |
294 | struct resource r; | |
295 | ret = of_address_to_resource(node, 0, &r); | |
2ca41c17 | 296 | of_node_put(node); |
072f1f91 RC |
297 | if (ret) |
298 | return ret; | |
299 | size = r.end - r.start; | |
fc99f97a | 300 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 301 | |
e9fbdaf2 AT |
302 | /* if we have no IOMMU, then we need to use carveout allocator. |
303 | * Grab the entire CMA chunk carved out in early startup in | |
304 | * mach-msm: | |
305 | */ | |
306 | } else if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
307 | DRM_INFO("using %s VRAM carveout\n", vram); |
308 | size = memparse(vram, NULL); | |
309 | } | |
310 | ||
311 | if (size) { | |
00085f1e | 312 | unsigned long attrs = 0; |
871d812a RC |
313 | void *p; |
314 | ||
871d812a RC |
315 | priv->vram.size = size; |
316 | ||
317 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
318 | ||
00085f1e KK |
319 | attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
320 | attrs |= DMA_ATTR_WRITE_COMBINE; | |
871d812a RC |
321 | |
322 | /* note that for no-kernel-mapping, the vaddr returned | |
323 | * is bogus, but non-null if allocation succeeded: | |
324 | */ | |
325 | p = dma_alloc_attrs(dev->dev, size, | |
00085f1e | 326 | &priv->vram.paddr, GFP_KERNEL, attrs); |
871d812a RC |
327 | if (!p) { |
328 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
329 | priv->vram.paddr = 0; | |
5bf9c0b6 | 330 | return -ENOMEM; |
871d812a RC |
331 | } |
332 | ||
333 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
334 | (uint32_t)priv->vram.paddr, | |
335 | (uint32_t)(priv->vram.paddr + size)); | |
336 | } | |
337 | ||
072f1f91 | 338 | return ret; |
5bf9c0b6 RC |
339 | } |
340 | ||
2b669875 | 341 | static int msm_drm_init(struct device *dev, struct drm_driver *drv) |
5bf9c0b6 | 342 | { |
2b669875 AT |
343 | struct platform_device *pdev = to_platform_device(dev); |
344 | struct drm_device *ddev; | |
5bf9c0b6 RC |
345 | struct msm_drm_private *priv; |
346 | struct msm_kms *kms; | |
347 | int ret; | |
348 | ||
2b669875 AT |
349 | ddev = drm_dev_alloc(drv, dev); |
350 | if (!ddev) { | |
351 | dev_err(dev, "failed to allocate drm_device\n"); | |
352 | return -ENOMEM; | |
353 | } | |
354 | ||
355 | platform_set_drvdata(pdev, ddev); | |
356 | ddev->platformdev = pdev; | |
357 | ||
5bf9c0b6 RC |
358 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
359 | if (!priv) { | |
2b669875 | 360 | drm_dev_unref(ddev); |
5bf9c0b6 RC |
361 | return -ENOMEM; |
362 | } | |
363 | ||
2b669875 | 364 | ddev->dev_private = priv; |
68209390 | 365 | priv->dev = ddev; |
5bf9c0b6 | 366 | |
0a6030d2 AT |
367 | ret = msm_mdss_init(ddev); |
368 | if (ret) { | |
369 | kfree(priv); | |
370 | drm_dev_unref(ddev); | |
371 | return ret; | |
372 | } | |
373 | ||
5bf9c0b6 | 374 | priv->wq = alloc_ordered_workqueue("msm", 0); |
ba00c3f2 | 375 | priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0); |
5bf9c0b6 RC |
376 | init_waitqueue_head(&priv->pending_crtcs_event); |
377 | ||
378 | INIT_LIST_HEAD(&priv->inactive_list); | |
78b1d470 HL |
379 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
380 | INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); | |
381 | spin_lock_init(&priv->vblank_ctrl.lock); | |
5bf9c0b6 | 382 | |
2b669875 | 383 | drm_mode_config_init(ddev); |
060530f1 RC |
384 | |
385 | /* Bind all our sub-components: */ | |
2b669875 AT |
386 | ret = component_bind_all(dev, ddev); |
387 | if (ret) { | |
0a6030d2 | 388 | msm_mdss_destroy(ddev); |
2b669875 AT |
389 | kfree(priv); |
390 | drm_dev_unref(ddev); | |
060530f1 | 391 | return ret; |
2b669875 | 392 | } |
060530f1 | 393 | |
2b669875 | 394 | ret = msm_init_vram(ddev); |
13f15565 RC |
395 | if (ret) |
396 | goto fail; | |
397 | ||
68209390 RC |
398 | msm_gem_shrinker_init(ddev); |
399 | ||
06c0dd96 RC |
400 | switch (get_mdp_ver(pdev)) { |
401 | case 4: | |
2b669875 | 402 | kms = mdp4_kms_init(ddev); |
0a6030d2 | 403 | priv->kms = kms; |
06c0dd96 RC |
404 | break; |
405 | case 5: | |
392ae6e0 | 406 | kms = mdp5_kms_init(ddev); |
06c0dd96 RC |
407 | break; |
408 | default: | |
409 | kms = ERR_PTR(-ENODEV); | |
410 | break; | |
411 | } | |
412 | ||
c8afe684 RC |
413 | if (IS_ERR(kms)) { |
414 | /* | |
415 | * NOTE: once we have GPU support, having no kms should not | |
416 | * be considered fatal.. ideally we would still support gpu | |
417 | * and (for example) use dmabuf/prime to share buffers with | |
418 | * imx drm driver on iMX5 | |
419 | */ | |
2b669875 | 420 | dev_err(dev, "failed to load kms\n"); |
e4826a94 | 421 | ret = PTR_ERR(kms); |
c8afe684 RC |
422 | goto fail; |
423 | } | |
424 | ||
c8afe684 | 425 | if (kms) { |
c8afe684 RC |
426 | ret = kms->funcs->hw_init(kms); |
427 | if (ret) { | |
2b669875 | 428 | dev_err(dev, "kms hw init failed: %d\n", ret); |
c8afe684 RC |
429 | goto fail; |
430 | } | |
431 | } | |
432 | ||
2b669875 | 433 | ddev->mode_config.funcs = &mode_config_funcs; |
c8afe684 | 434 | |
2b669875 | 435 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
c8afe684 | 436 | if (ret < 0) { |
2b669875 | 437 | dev_err(dev, "failed to initialize vblank\n"); |
c8afe684 RC |
438 | goto fail; |
439 | } | |
440 | ||
a2b3a557 AT |
441 | if (kms) { |
442 | pm_runtime_get_sync(dev); | |
443 | ret = drm_irq_install(ddev, kms->irq); | |
444 | pm_runtime_put_sync(dev); | |
445 | if (ret < 0) { | |
446 | dev_err(dev, "failed to install IRQ handler\n"); | |
447 | goto fail; | |
448 | } | |
c8afe684 RC |
449 | } |
450 | ||
2b669875 AT |
451 | ret = drm_dev_register(ddev, 0); |
452 | if (ret) | |
453 | goto fail; | |
454 | ||
2b669875 | 455 | drm_mode_config_reset(ddev); |
cf3a7e4c | 456 | |
a9ee34b7 | 457 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 | 458 | if (fbdev) |
2b669875 | 459 | priv->fbdev = msm_fbdev_init(ddev); |
c8afe684 RC |
460 | #endif |
461 | ||
2b669875 | 462 | ret = msm_debugfs_late_init(ddev); |
a7d3c950 RC |
463 | if (ret) |
464 | goto fail; | |
465 | ||
2b669875 | 466 | drm_kms_helper_poll_init(ddev); |
c8afe684 RC |
467 | |
468 | return 0; | |
469 | ||
470 | fail: | |
2b669875 | 471 | msm_drm_uninit(dev); |
c8afe684 RC |
472 | return ret; |
473 | } | |
474 | ||
2b669875 AT |
475 | /* |
476 | * DRM operations: | |
477 | */ | |
478 | ||
7198e6b0 RC |
479 | static void load_gpu(struct drm_device *dev) |
480 | { | |
a1ad3523 | 481 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 482 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 483 | |
a1ad3523 RC |
484 | mutex_lock(&init_lock); |
485 | ||
e2550b7a RC |
486 | if (!priv->gpu) |
487 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 488 | |
a1ad3523 | 489 | mutex_unlock(&init_lock); |
7198e6b0 RC |
490 | } |
491 | ||
492 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
493 | { | |
494 | struct msm_file_private *ctx; | |
495 | ||
496 | /* For now, load gpu on open.. to avoid the requirement of having | |
497 | * firmware in the initrd. | |
498 | */ | |
499 | load_gpu(dev); | |
500 | ||
501 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
502 | if (!ctx) | |
503 | return -ENOMEM; | |
504 | ||
505 | file->driver_priv = ctx; | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
c8afe684 RC |
510 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
511 | { | |
512 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 513 | struct msm_file_private *ctx = file->driver_priv; |
7198e6b0 | 514 | |
7198e6b0 RC |
515 | mutex_lock(&dev->struct_mutex); |
516 | if (ctx == priv->lastctx) | |
517 | priv->lastctx = NULL; | |
518 | mutex_unlock(&dev->struct_mutex); | |
519 | ||
520 | kfree(ctx); | |
c8afe684 RC |
521 | } |
522 | ||
523 | static void msm_lastclose(struct drm_device *dev) | |
524 | { | |
525 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
526 | if (priv->fbdev) |
527 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
528 | } |
529 | ||
e9f0d76f | 530 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
531 | { |
532 | struct drm_device *dev = arg; | |
533 | struct msm_drm_private *priv = dev->dev_private; | |
534 | struct msm_kms *kms = priv->kms; | |
535 | BUG_ON(!kms); | |
536 | return kms->funcs->irq(kms); | |
537 | } | |
538 | ||
539 | static void msm_irq_preinstall(struct drm_device *dev) | |
540 | { | |
541 | struct msm_drm_private *priv = dev->dev_private; | |
542 | struct msm_kms *kms = priv->kms; | |
543 | BUG_ON(!kms); | |
544 | kms->funcs->irq_preinstall(kms); | |
545 | } | |
546 | ||
547 | static int msm_irq_postinstall(struct drm_device *dev) | |
548 | { | |
549 | struct msm_drm_private *priv = dev->dev_private; | |
550 | struct msm_kms *kms = priv->kms; | |
551 | BUG_ON(!kms); | |
552 | return kms->funcs->irq_postinstall(kms); | |
553 | } | |
554 | ||
555 | static void msm_irq_uninstall(struct drm_device *dev) | |
556 | { | |
557 | struct msm_drm_private *priv = dev->dev_private; | |
558 | struct msm_kms *kms = priv->kms; | |
559 | BUG_ON(!kms); | |
560 | kms->funcs->irq_uninstall(kms); | |
561 | } | |
562 | ||
88e72717 | 563 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
564 | { |
565 | struct msm_drm_private *priv = dev->dev_private; | |
566 | struct msm_kms *kms = priv->kms; | |
567 | if (!kms) | |
568 | return -ENXIO; | |
88e72717 TR |
569 | DBG("dev=%p, crtc=%u", dev, pipe); |
570 | return vblank_ctrl_queue_work(priv, pipe, true); | |
c8afe684 RC |
571 | } |
572 | ||
88e72717 | 573 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
574 | { |
575 | struct msm_drm_private *priv = dev->dev_private; | |
576 | struct msm_kms *kms = priv->kms; | |
577 | if (!kms) | |
578 | return; | |
88e72717 TR |
579 | DBG("dev=%p, crtc=%u", dev, pipe); |
580 | vblank_ctrl_queue_work(priv, pipe, false); | |
c8afe684 RC |
581 | } |
582 | ||
7198e6b0 RC |
583 | /* |
584 | * DRM ioctls: | |
585 | */ | |
586 | ||
587 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
588 | struct drm_file *file) | |
589 | { | |
590 | struct msm_drm_private *priv = dev->dev_private; | |
591 | struct drm_msm_param *args = data; | |
592 | struct msm_gpu *gpu; | |
593 | ||
594 | /* for now, we just have 3d pipe.. eventually this would need to | |
595 | * be more clever to dispatch to appropriate gpu module: | |
596 | */ | |
597 | if (args->pipe != MSM_PIPE_3D0) | |
598 | return -EINVAL; | |
599 | ||
600 | gpu = priv->gpu; | |
601 | ||
602 | if (!gpu) | |
603 | return -ENXIO; | |
604 | ||
605 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
606 | } | |
607 | ||
608 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
609 | struct drm_file *file) | |
610 | { | |
611 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
612 | |
613 | if (args->flags & ~MSM_BO_FLAGS) { | |
614 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
7198e6b0 RC |
618 | return msm_gem_new_handle(dev, file, args->size, |
619 | args->flags, &args->handle); | |
620 | } | |
621 | ||
56c2da83 RC |
622 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
623 | { | |
624 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
625 | } | |
7198e6b0 RC |
626 | |
627 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
628 | struct drm_file *file) | |
629 | { | |
630 | struct drm_msm_gem_cpu_prep *args = data; | |
631 | struct drm_gem_object *obj; | |
56c2da83 | 632 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
633 | int ret; |
634 | ||
93ddb0d3 RC |
635 | if (args->op & ~MSM_PREP_FLAGS) { |
636 | DRM_ERROR("invalid op: %08x\n", args->op); | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
a8ad0bd8 | 640 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
641 | if (!obj) |
642 | return -ENOENT; | |
643 | ||
56c2da83 | 644 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
645 | |
646 | drm_gem_object_unreference_unlocked(obj); | |
647 | ||
648 | return ret; | |
649 | } | |
650 | ||
651 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
652 | struct drm_file *file) | |
653 | { | |
654 | struct drm_msm_gem_cpu_fini *args = data; | |
655 | struct drm_gem_object *obj; | |
656 | int ret; | |
657 | ||
a8ad0bd8 | 658 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
659 | if (!obj) |
660 | return -ENOENT; | |
661 | ||
662 | ret = msm_gem_cpu_fini(obj); | |
663 | ||
664 | drm_gem_object_unreference_unlocked(obj); | |
665 | ||
666 | return ret; | |
667 | } | |
668 | ||
669 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
670 | struct drm_file *file) | |
671 | { | |
672 | struct drm_msm_gem_info *args = data; | |
673 | struct drm_gem_object *obj; | |
674 | int ret = 0; | |
675 | ||
676 | if (args->pad) | |
677 | return -EINVAL; | |
678 | ||
a8ad0bd8 | 679 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
680 | if (!obj) |
681 | return -ENOENT; | |
682 | ||
683 | args->offset = msm_gem_mmap_offset(obj); | |
684 | ||
685 | drm_gem_object_unreference_unlocked(obj); | |
686 | ||
687 | return ret; | |
688 | } | |
689 | ||
690 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
691 | struct drm_file *file) | |
692 | { | |
ca762a8a | 693 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 694 | struct drm_msm_wait_fence *args = data; |
56c2da83 | 695 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
696 | |
697 | if (args->pad) { | |
698 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
ca762a8a RC |
702 | if (!priv->gpu) |
703 | return 0; | |
704 | ||
705 | return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true); | |
7198e6b0 RC |
706 | } |
707 | ||
4cd33c48 RC |
708 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
709 | struct drm_file *file) | |
710 | { | |
711 | struct drm_msm_gem_madvise *args = data; | |
712 | struct drm_gem_object *obj; | |
713 | int ret; | |
714 | ||
715 | switch (args->madv) { | |
716 | case MSM_MADV_DONTNEED: | |
717 | case MSM_MADV_WILLNEED: | |
718 | break; | |
719 | default: | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
723 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
727 | obj = drm_gem_object_lookup(file, args->handle); | |
728 | if (!obj) { | |
729 | ret = -ENOENT; | |
730 | goto unlock; | |
731 | } | |
732 | ||
733 | ret = msm_gem_madvise(obj, args->madv); | |
734 | if (ret >= 0) { | |
735 | args->retained = ret; | |
736 | ret = 0; | |
737 | } | |
738 | ||
739 | drm_gem_object_unreference(obj); | |
740 | ||
741 | unlock: | |
742 | mutex_unlock(&dev->struct_mutex); | |
743 | return ret; | |
744 | } | |
745 | ||
7198e6b0 | 746 | static const struct drm_ioctl_desc msm_ioctls[] = { |
f8c47144 DV |
747 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
748 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
749 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
750 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
751 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
752 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), | |
753 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), | |
4cd33c48 | 754 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW), |
7198e6b0 RC |
755 | }; |
756 | ||
c8afe684 RC |
757 | static const struct vm_operations_struct vm_ops = { |
758 | .fault = msm_gem_fault, | |
759 | .open = drm_gem_vm_open, | |
760 | .close = drm_gem_vm_close, | |
761 | }; | |
762 | ||
763 | static const struct file_operations fops = { | |
764 | .owner = THIS_MODULE, | |
765 | .open = drm_open, | |
766 | .release = drm_release, | |
767 | .unlocked_ioctl = drm_ioctl, | |
768 | #ifdef CONFIG_COMPAT | |
769 | .compat_ioctl = drm_compat_ioctl, | |
770 | #endif | |
771 | .poll = drm_poll, | |
772 | .read = drm_read, | |
773 | .llseek = no_llseek, | |
774 | .mmap = msm_gem_mmap, | |
775 | }; | |
776 | ||
777 | static struct drm_driver msm_driver = { | |
05b84911 RC |
778 | .driver_features = DRIVER_HAVE_IRQ | |
779 | DRIVER_GEM | | |
780 | DRIVER_PRIME | | |
b4b15c86 | 781 | DRIVER_RENDER | |
a5436e1d | 782 | DRIVER_ATOMIC | |
05b84911 | 783 | DRIVER_MODESET, |
7198e6b0 | 784 | .open = msm_open, |
c8afe684 RC |
785 | .preclose = msm_preclose, |
786 | .lastclose = msm_lastclose, | |
787 | .irq_handler = msm_irq, | |
788 | .irq_preinstall = msm_irq_preinstall, | |
789 | .irq_postinstall = msm_irq_postinstall, | |
790 | .irq_uninstall = msm_irq_uninstall, | |
b44f8408 | 791 | .get_vblank_counter = drm_vblank_no_hw_counter, |
c8afe684 RC |
792 | .enable_vblank = msm_enable_vblank, |
793 | .disable_vblank = msm_disable_vblank, | |
794 | .gem_free_object = msm_gem_free_object, | |
795 | .gem_vm_ops = &vm_ops, | |
796 | .dumb_create = msm_gem_dumb_create, | |
797 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 798 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
799 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
800 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
801 | .gem_prime_export = drm_gem_prime_export, | |
802 | .gem_prime_import = drm_gem_prime_import, | |
803 | .gem_prime_pin = msm_gem_prime_pin, | |
804 | .gem_prime_unpin = msm_gem_prime_unpin, | |
805 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
806 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
807 | .gem_prime_vmap = msm_gem_prime_vmap, | |
808 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 809 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
810 | #ifdef CONFIG_DEBUG_FS |
811 | .debugfs_init = msm_debugfs_init, | |
812 | .debugfs_cleanup = msm_debugfs_cleanup, | |
813 | #endif | |
7198e6b0 RC |
814 | .ioctls = msm_ioctls, |
815 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
816 | .fops = &fops, |
817 | .name = "msm", | |
818 | .desc = "MSM Snapdragon DRM", | |
819 | .date = "20130625", | |
a8d854c1 RC |
820 | .major = MSM_VERSION_MAJOR, |
821 | .minor = MSM_VERSION_MINOR, | |
822 | .patchlevel = MSM_VERSION_PATCHLEVEL, | |
c8afe684 RC |
823 | }; |
824 | ||
825 | #ifdef CONFIG_PM_SLEEP | |
826 | static int msm_pm_suspend(struct device *dev) | |
827 | { | |
828 | struct drm_device *ddev = dev_get_drvdata(dev); | |
829 | ||
830 | drm_kms_helper_poll_disable(ddev); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | static int msm_pm_resume(struct device *dev) | |
836 | { | |
837 | struct drm_device *ddev = dev_get_drvdata(dev); | |
838 | ||
839 | drm_kms_helper_poll_enable(ddev); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | #endif | |
844 | ||
845 | static const struct dev_pm_ops msm_pm_ops = { | |
846 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
847 | }; | |
848 | ||
060530f1 RC |
849 | /* |
850 | * Componentized driver support: | |
851 | */ | |
852 | ||
e9fbdaf2 AT |
853 | /* |
854 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
855 | * so probably some room for some helpers | |
060530f1 RC |
856 | */ |
857 | static int compare_of(struct device *dev, void *data) | |
858 | { | |
859 | return dev->of_node == data; | |
860 | } | |
41e69778 | 861 | |
812070eb AT |
862 | /* |
863 | * Identify what components need to be added by parsing what remote-endpoints | |
864 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there | |
865 | * is no external component that we need to add since LVDS is within MDP4 | |
866 | * itself. | |
867 | */ | |
868 | static int add_components_mdp(struct device *mdp_dev, | |
869 | struct component_match **matchptr) | |
870 | { | |
871 | struct device_node *np = mdp_dev->of_node; | |
872 | struct device_node *ep_node; | |
54011e26 AT |
873 | struct device *master_dev; |
874 | ||
875 | /* | |
876 | * on MDP4 based platforms, the MDP platform device is the component | |
877 | * master that adds other display interface components to itself. | |
878 | * | |
879 | * on MDP5 based platforms, the MDSS platform device is the component | |
880 | * master that adds MDP5 and other display interface components to | |
881 | * itself. | |
882 | */ | |
883 | if (of_device_is_compatible(np, "qcom,mdp4")) | |
884 | master_dev = mdp_dev; | |
885 | else | |
886 | master_dev = mdp_dev->parent; | |
812070eb AT |
887 | |
888 | for_each_endpoint_of_node(np, ep_node) { | |
889 | struct device_node *intf; | |
890 | struct of_endpoint ep; | |
891 | int ret; | |
892 | ||
893 | ret = of_graph_parse_endpoint(ep_node, &ep); | |
894 | if (ret) { | |
895 | dev_err(mdp_dev, "unable to parse port endpoint\n"); | |
896 | of_node_put(ep_node); | |
897 | return ret; | |
898 | } | |
899 | ||
900 | /* | |
901 | * The LCDC/LVDS port on MDP4 is a speacial case where the | |
902 | * remote-endpoint isn't a component that we need to add | |
903 | */ | |
904 | if (of_device_is_compatible(np, "qcom,mdp4") && | |
905 | ep.port == 0) { | |
906 | of_node_put(ep_node); | |
907 | continue; | |
908 | } | |
909 | ||
910 | /* | |
911 | * It's okay if some of the ports don't have a remote endpoint | |
912 | * specified. It just means that the port isn't connected to | |
913 | * any external interface. | |
914 | */ | |
915 | intf = of_graph_get_remote_port_parent(ep_node); | |
916 | if (!intf) { | |
917 | of_node_put(ep_node); | |
918 | continue; | |
919 | } | |
920 | ||
54011e26 | 921 | component_match_add(master_dev, matchptr, compare_of, intf); |
812070eb AT |
922 | |
923 | of_node_put(intf); | |
924 | of_node_put(ep_node); | |
925 | } | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
54011e26 AT |
930 | static int compare_name_mdp(struct device *dev, void *data) |
931 | { | |
932 | return (strstr(dev_name(dev), "mdp") != NULL); | |
933 | } | |
934 | ||
7d526fcf AT |
935 | static int add_display_components(struct device *dev, |
936 | struct component_match **matchptr) | |
937 | { | |
54011e26 AT |
938 | struct device *mdp_dev; |
939 | int ret; | |
940 | ||
941 | /* | |
942 | * MDP5 based devices don't have a flat hierarchy. There is a top level | |
943 | * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the | |
944 | * children devices, find the MDP5 node, and then add the interfaces | |
945 | * to our components list. | |
946 | */ | |
947 | if (of_device_is_compatible(dev->of_node, "qcom,mdss")) { | |
948 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); | |
949 | if (ret) { | |
950 | dev_err(dev, "failed to populate children devices\n"); | |
951 | return ret; | |
952 | } | |
953 | ||
954 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); | |
955 | if (!mdp_dev) { | |
956 | dev_err(dev, "failed to find MDSS MDP node\n"); | |
957 | of_platform_depopulate(dev); | |
958 | return -ENODEV; | |
959 | } | |
960 | ||
961 | put_device(mdp_dev); | |
962 | ||
963 | /* add the MDP component itself */ | |
964 | component_match_add(dev, matchptr, compare_of, | |
965 | mdp_dev->of_node); | |
966 | } else { | |
967 | /* MDP4 */ | |
968 | mdp_dev = dev; | |
969 | } | |
970 | ||
971 | ret = add_components_mdp(mdp_dev, matchptr); | |
972 | if (ret) | |
973 | of_platform_depopulate(dev); | |
974 | ||
975 | return ret; | |
7d526fcf AT |
976 | } |
977 | ||
dc3ea265 AT |
978 | /* |
979 | * We don't know what's the best binding to link the gpu with the drm device. | |
980 | * Fow now, we just hunt for all the possible gpus that we support, and add them | |
981 | * as components. | |
982 | */ | |
983 | static const struct of_device_id msm_gpu_match[] = { | |
984 | { .compatible = "qcom,adreno-3xx" }, | |
985 | { .compatible = "qcom,kgsl-3d0" }, | |
986 | { }, | |
987 | }; | |
988 | ||
7d526fcf AT |
989 | static int add_gpu_components(struct device *dev, |
990 | struct component_match **matchptr) | |
991 | { | |
dc3ea265 AT |
992 | struct device_node *np; |
993 | ||
994 | np = of_find_matching_node(NULL, msm_gpu_match); | |
995 | if (!np) | |
996 | return 0; | |
997 | ||
998 | component_match_add(dev, matchptr, compare_of, np); | |
999 | ||
1000 | of_node_put(np); | |
1001 | ||
1002 | return 0; | |
7d526fcf AT |
1003 | } |
1004 | ||
84448288 RK |
1005 | static int msm_drm_bind(struct device *dev) |
1006 | { | |
2b669875 | 1007 | return msm_drm_init(dev, &msm_driver); |
84448288 RK |
1008 | } |
1009 | ||
1010 | static void msm_drm_unbind(struct device *dev) | |
1011 | { | |
2b669875 | 1012 | msm_drm_uninit(dev); |
84448288 RK |
1013 | } |
1014 | ||
1015 | static const struct component_master_ops msm_drm_ops = { | |
1016 | .bind = msm_drm_bind, | |
1017 | .unbind = msm_drm_unbind, | |
1018 | }; | |
1019 | ||
1020 | /* | |
1021 | * Platform driver: | |
1022 | */ | |
060530f1 | 1023 | |
84448288 | 1024 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1025 | { |
84448288 | 1026 | struct component_match *match = NULL; |
7d526fcf AT |
1027 | int ret; |
1028 | ||
1029 | ret = add_display_components(&pdev->dev, &match); | |
1030 | if (ret) | |
1031 | return ret; | |
e9fbdaf2 | 1032 | |
7d526fcf AT |
1033 | ret = add_gpu_components(&pdev->dev, &match); |
1034 | if (ret) | |
1035 | return ret; | |
060530f1 | 1036 | |
871d812a | 1037 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 1038 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1039 | } |
1040 | ||
1041 | static int msm_pdev_remove(struct platform_device *pdev) | |
1042 | { | |
060530f1 | 1043 | component_master_del(&pdev->dev, &msm_drm_ops); |
54011e26 | 1044 | of_platform_depopulate(&pdev->dev); |
c8afe684 RC |
1045 | |
1046 | return 0; | |
1047 | } | |
1048 | ||
06c0dd96 | 1049 | static const struct of_device_id dt_match[] = { |
96a611b5 AT |
1050 | { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */ |
1051 | { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */ | |
06c0dd96 RC |
1052 | {} |
1053 | }; | |
1054 | MODULE_DEVICE_TABLE(of, dt_match); | |
1055 | ||
c8afe684 RC |
1056 | static struct platform_driver msm_platform_driver = { |
1057 | .probe = msm_pdev_probe, | |
1058 | .remove = msm_pdev_remove, | |
1059 | .driver = { | |
c8afe684 | 1060 | .name = "msm", |
06c0dd96 | 1061 | .of_match_table = dt_match, |
c8afe684 RC |
1062 | .pm = &msm_pm_ops, |
1063 | }, | |
c8afe684 RC |
1064 | }; |
1065 | ||
1066 | static int __init msm_drm_register(void) | |
1067 | { | |
1068 | DBG("init"); | |
1dd0a0b1 | 1069 | msm_mdp_register(); |
d5af49c9 | 1070 | msm_dsi_register(); |
00453981 | 1071 | msm_edp_register(); |
fcda50c8 | 1072 | msm_hdmi_register(); |
bfd28b13 | 1073 | adreno_register(); |
c8afe684 RC |
1074 | return platform_driver_register(&msm_platform_driver); |
1075 | } | |
1076 | ||
1077 | static void __exit msm_drm_unregister(void) | |
1078 | { | |
1079 | DBG("fini"); | |
1080 | platform_driver_unregister(&msm_platform_driver); | |
fcda50c8 | 1081 | msm_hdmi_unregister(); |
bfd28b13 | 1082 | adreno_unregister(); |
00453981 | 1083 | msm_edp_unregister(); |
d5af49c9 | 1084 | msm_dsi_unregister(); |
1dd0a0b1 | 1085 | msm_mdp_unregister(); |
c8afe684 RC |
1086 | } |
1087 | ||
1088 | module_init(msm_drm_register); | |
1089 | module_exit(msm_drm_unregister); | |
1090 | ||
1091 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1092 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1093 | MODULE_LICENSE("GPL"); |