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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
7198e6b0 | 19 | #include "msm_gpu.h" |
dd2da6e3 | 20 | #include "msm_kms.h" |
c8afe684 | 21 | |
c8afe684 RC |
22 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
23 | { | |
24 | struct msm_drm_private *priv = dev->dev_private; | |
25 | if (priv->fbdev) | |
26 | drm_fb_helper_hotplug_event(priv->fbdev); | |
27 | } | |
28 | ||
29 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
30 | .fb_create = msm_framebuffer_create, | |
31 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 32 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 33 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
34 | }; |
35 | ||
871d812a | 36 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
37 | { |
38 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 39 | int idx = priv->num_mmus++; |
c8afe684 | 40 | |
871d812a | 41 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
42 | return -EINVAL; |
43 | ||
871d812a | 44 | priv->mmus[idx] = mmu; |
c8afe684 RC |
45 | |
46 | return idx; | |
47 | } | |
48 | ||
c8afe684 RC |
49 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
50 | static bool reglog = false; | |
51 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
52 | module_param(reglog, bool, 0600); | |
53 | #else | |
54 | #define reglog 0 | |
55 | #endif | |
56 | ||
a9ee34b7 | 57 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
58 | static bool fbdev = true; |
59 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
60 | module_param(fbdev, bool, 0600); | |
61 | #endif | |
62 | ||
3a10ba8c | 63 | static char *vram = "16m"; |
4313c744 | 64 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
871d812a RC |
65 | module_param(vram, charp, 0); |
66 | ||
060530f1 RC |
67 | /* |
68 | * Util/helpers: | |
69 | */ | |
70 | ||
c8afe684 RC |
71 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
72 | const char *dbgname) | |
73 | { | |
74 | struct resource *res; | |
75 | unsigned long size; | |
76 | void __iomem *ptr; | |
77 | ||
78 | if (name) | |
79 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
80 | else | |
81 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
82 | ||
83 | if (!res) { | |
84 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
85 | return ERR_PTR(-EINVAL); | |
86 | } | |
87 | ||
88 | size = resource_size(res); | |
89 | ||
90 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
91 | if (!ptr) { | |
92 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
93 | return ERR_PTR(-ENOMEM); | |
94 | } | |
95 | ||
96 | if (reglog) | |
fc99f97a | 97 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
98 | |
99 | return ptr; | |
100 | } | |
101 | ||
102 | void msm_writel(u32 data, void __iomem *addr) | |
103 | { | |
104 | if (reglog) | |
fc99f97a | 105 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
106 | writel(data, addr); |
107 | } | |
108 | ||
109 | u32 msm_readl(const void __iomem *addr) | |
110 | { | |
111 | u32 val = readl(addr); | |
112 | if (reglog) | |
fc99f97a | 113 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
c8afe684 RC |
114 | return val; |
115 | } | |
116 | ||
78b1d470 HL |
117 | struct vblank_event { |
118 | struct list_head node; | |
119 | int crtc_id; | |
120 | bool enable; | |
121 | }; | |
122 | ||
123 | static void vblank_ctrl_worker(struct work_struct *work) | |
124 | { | |
125 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, | |
126 | struct msm_vblank_ctrl, work); | |
127 | struct msm_drm_private *priv = container_of(vbl_ctrl, | |
128 | struct msm_drm_private, vblank_ctrl); | |
129 | struct msm_kms *kms = priv->kms; | |
130 | struct vblank_event *vbl_ev, *tmp; | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
134 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
135 | list_del(&vbl_ev->node); | |
136 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
137 | ||
138 | if (vbl_ev->enable) | |
139 | kms->funcs->enable_vblank(kms, | |
140 | priv->crtcs[vbl_ev->crtc_id]); | |
141 | else | |
142 | kms->funcs->disable_vblank(kms, | |
143 | priv->crtcs[vbl_ev->crtc_id]); | |
144 | ||
145 | kfree(vbl_ev); | |
146 | ||
147 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
148 | } | |
149 | ||
150 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
151 | } | |
152 | ||
153 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
154 | int crtc_id, bool enable) | |
155 | { | |
156 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; | |
157 | struct vblank_event *vbl_ev; | |
158 | unsigned long flags; | |
159 | ||
160 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); | |
161 | if (!vbl_ev) | |
162 | return -ENOMEM; | |
163 | ||
164 | vbl_ev->crtc_id = crtc_id; | |
165 | vbl_ev->enable = enable; | |
166 | ||
167 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
168 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); | |
169 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
170 | ||
171 | queue_work(priv->wq, &vbl_ctrl->work); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
c8afe684 RC |
176 | /* |
177 | * DRM operations: | |
178 | */ | |
179 | ||
180 | static int msm_unload(struct drm_device *dev) | |
181 | { | |
182 | struct msm_drm_private *priv = dev->dev_private; | |
183 | struct msm_kms *kms = priv->kms; | |
7198e6b0 | 184 | struct msm_gpu *gpu = priv->gpu; |
78b1d470 HL |
185 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
186 | struct vblank_event *vbl_ev, *tmp; | |
187 | ||
188 | /* We must cancel and cleanup any pending vblank enable/disable | |
189 | * work before drm_irq_uninstall() to avoid work re-enabling an | |
190 | * irq after uninstall has disabled it. | |
191 | */ | |
192 | cancel_work_sync(&vbl_ctrl->work); | |
193 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
194 | list_del(&vbl_ev->node); | |
195 | kfree(vbl_ev); | |
196 | } | |
c8afe684 RC |
197 | |
198 | drm_kms_helper_poll_fini(dev); | |
1aaa57f5 AT |
199 | |
200 | #ifdef CONFIG_DRM_FBDEV_EMULATION | |
201 | if (fbdev && priv->fbdev) | |
202 | msm_fbdev_free(dev); | |
203 | #endif | |
c8afe684 RC |
204 | drm_mode_config_cleanup(dev); |
205 | drm_vblank_cleanup(dev); | |
206 | ||
207 | pm_runtime_get_sync(dev->dev); | |
208 | drm_irq_uninstall(dev); | |
209 | pm_runtime_put_sync(dev->dev); | |
210 | ||
211 | flush_workqueue(priv->wq); | |
212 | destroy_workqueue(priv->wq); | |
213 | ||
214 | if (kms) { | |
215 | pm_runtime_disable(dev->dev); | |
216 | kms->funcs->destroy(kms); | |
217 | } | |
218 | ||
7198e6b0 RC |
219 | if (gpu) { |
220 | mutex_lock(&dev->struct_mutex); | |
221 | gpu->funcs->pm_suspend(gpu); | |
7198e6b0 | 222 | mutex_unlock(&dev->struct_mutex); |
774449eb | 223 | gpu->funcs->destroy(gpu); |
7198e6b0 | 224 | } |
c8afe684 | 225 | |
871d812a RC |
226 | if (priv->vram.paddr) { |
227 | DEFINE_DMA_ATTRS(attrs); | |
228 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
229 | drm_mm_takedown(&priv->vram.mm); | |
230 | dma_free_attrs(dev->dev, priv->vram.size, NULL, | |
231 | priv->vram.paddr, &attrs); | |
232 | } | |
233 | ||
060530f1 RC |
234 | component_unbind_all(dev->dev, dev); |
235 | ||
c8afe684 RC |
236 | dev->dev_private = NULL; |
237 | ||
238 | kfree(priv); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
06c0dd96 RC |
243 | static int get_mdp_ver(struct platform_device *pdev) |
244 | { | |
06c0dd96 | 245 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
246 | |
247 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
248 | } |
249 | ||
072f1f91 RC |
250 | #include <linux/of_address.h> |
251 | ||
5bf9c0b6 | 252 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 253 | { |
5bf9c0b6 | 254 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 255 | struct device_node *node; |
072f1f91 RC |
256 | unsigned long size = 0; |
257 | int ret = 0; | |
258 | ||
072f1f91 RC |
259 | /* In the device-tree world, we could have a 'memory-region' |
260 | * phandle, which gives us a link to our "vram". Allocating | |
261 | * is all nicely abstracted behind the dma api, but we need | |
262 | * to know the entire size to allocate it all in one go. There | |
263 | * are two cases: | |
264 | * 1) device with no IOMMU, in which case we need exclusive | |
265 | * access to a VRAM carveout big enough for all gpu | |
266 | * buffers | |
267 | * 2) device with IOMMU, but where the bootloader puts up | |
268 | * a splash screen. In this case, the VRAM carveout | |
269 | * need only be large enough for fbdev fb. But we need | |
270 | * exclusive access to the buffer to avoid the kernel | |
271 | * using those pages for other purposes (which appears | |
272 | * as corruption on screen before we have a chance to | |
273 | * load and do initial modeset) | |
274 | */ | |
072f1f91 RC |
275 | |
276 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
277 | if (node) { | |
278 | struct resource r; | |
279 | ret = of_address_to_resource(node, 0, &r); | |
280 | if (ret) | |
281 | return ret; | |
282 | size = r.end - r.start; | |
fc99f97a | 283 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 284 | |
e9fbdaf2 AT |
285 | /* if we have no IOMMU, then we need to use carveout allocator. |
286 | * Grab the entire CMA chunk carved out in early startup in | |
287 | * mach-msm: | |
288 | */ | |
289 | } else if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
290 | DRM_INFO("using %s VRAM carveout\n", vram); |
291 | size = memparse(vram, NULL); | |
292 | } | |
293 | ||
294 | if (size) { | |
871d812a | 295 | DEFINE_DMA_ATTRS(attrs); |
871d812a RC |
296 | void *p; |
297 | ||
871d812a RC |
298 | priv->vram.size = size; |
299 | ||
300 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
301 | ||
302 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
303 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
304 | ||
305 | /* note that for no-kernel-mapping, the vaddr returned | |
306 | * is bogus, but non-null if allocation succeeded: | |
307 | */ | |
308 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 309 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
310 | if (!p) { |
311 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
312 | priv->vram.paddr = 0; | |
5bf9c0b6 | 313 | return -ENOMEM; |
871d812a RC |
314 | } |
315 | ||
316 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
317 | (uint32_t)priv->vram.paddr, | |
318 | (uint32_t)(priv->vram.paddr + size)); | |
319 | } | |
320 | ||
072f1f91 | 321 | return ret; |
5bf9c0b6 RC |
322 | } |
323 | ||
324 | static int msm_load(struct drm_device *dev, unsigned long flags) | |
325 | { | |
326 | struct platform_device *pdev = dev->platformdev; | |
327 | struct msm_drm_private *priv; | |
328 | struct msm_kms *kms; | |
329 | int ret; | |
330 | ||
331 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
332 | if (!priv) { | |
333 | dev_err(dev->dev, "failed to allocate private data\n"); | |
334 | return -ENOMEM; | |
335 | } | |
336 | ||
337 | dev->dev_private = priv; | |
338 | ||
339 | priv->wq = alloc_ordered_workqueue("msm", 0); | |
340 | init_waitqueue_head(&priv->fence_event); | |
341 | init_waitqueue_head(&priv->pending_crtcs_event); | |
342 | ||
343 | INIT_LIST_HEAD(&priv->inactive_list); | |
344 | INIT_LIST_HEAD(&priv->fence_cbs); | |
78b1d470 HL |
345 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
346 | INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); | |
347 | spin_lock_init(&priv->vblank_ctrl.lock); | |
5bf9c0b6 RC |
348 | |
349 | drm_mode_config_init(dev); | |
350 | ||
060530f1 RC |
351 | platform_set_drvdata(pdev, dev); |
352 | ||
353 | /* Bind all our sub-components: */ | |
354 | ret = component_bind_all(dev->dev, dev); | |
355 | if (ret) | |
356 | return ret; | |
357 | ||
13f15565 RC |
358 | ret = msm_init_vram(dev); |
359 | if (ret) | |
360 | goto fail; | |
361 | ||
06c0dd96 RC |
362 | switch (get_mdp_ver(pdev)) { |
363 | case 4: | |
364 | kms = mdp4_kms_init(dev); | |
365 | break; | |
366 | case 5: | |
367 | kms = mdp5_kms_init(dev); | |
368 | break; | |
369 | default: | |
370 | kms = ERR_PTR(-ENODEV); | |
371 | break; | |
372 | } | |
373 | ||
c8afe684 RC |
374 | if (IS_ERR(kms)) { |
375 | /* | |
376 | * NOTE: once we have GPU support, having no kms should not | |
377 | * be considered fatal.. ideally we would still support gpu | |
378 | * and (for example) use dmabuf/prime to share buffers with | |
379 | * imx drm driver on iMX5 | |
380 | */ | |
381 | dev_err(dev->dev, "failed to load kms\n"); | |
e4826a94 | 382 | ret = PTR_ERR(kms); |
c8afe684 RC |
383 | goto fail; |
384 | } | |
385 | ||
386 | priv->kms = kms; | |
387 | ||
388 | if (kms) { | |
389 | pm_runtime_enable(dev->dev); | |
390 | ret = kms->funcs->hw_init(kms); | |
391 | if (ret) { | |
392 | dev_err(dev->dev, "kms hw init failed: %d\n", ret); | |
393 | goto fail; | |
394 | } | |
395 | } | |
396 | ||
c8afe684 RC |
397 | dev->mode_config.funcs = &mode_config_funcs; |
398 | ||
d65bd0e4 | 399 | ret = drm_vblank_init(dev, priv->num_crtcs); |
c8afe684 RC |
400 | if (ret < 0) { |
401 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
402 | goto fail; | |
403 | } | |
404 | ||
405 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 406 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
c8afe684 RC |
407 | pm_runtime_put_sync(dev->dev); |
408 | if (ret < 0) { | |
409 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
410 | goto fail; | |
411 | } | |
412 | ||
cf3a7e4c RC |
413 | drm_mode_config_reset(dev); |
414 | ||
a9ee34b7 | 415 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
416 | if (fbdev) |
417 | priv->fbdev = msm_fbdev_init(dev); | |
c8afe684 RC |
418 | #endif |
419 | ||
a7d3c950 RC |
420 | ret = msm_debugfs_late_init(dev); |
421 | if (ret) | |
422 | goto fail; | |
423 | ||
c8afe684 RC |
424 | drm_kms_helper_poll_init(dev); |
425 | ||
426 | return 0; | |
427 | ||
428 | fail: | |
429 | msm_unload(dev); | |
430 | return ret; | |
431 | } | |
432 | ||
7198e6b0 RC |
433 | static void load_gpu(struct drm_device *dev) |
434 | { | |
a1ad3523 | 435 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 436 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 437 | |
a1ad3523 RC |
438 | mutex_lock(&init_lock); |
439 | ||
e2550b7a RC |
440 | if (!priv->gpu) |
441 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 442 | |
a1ad3523 | 443 | mutex_unlock(&init_lock); |
7198e6b0 RC |
444 | } |
445 | ||
446 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
447 | { | |
448 | struct msm_file_private *ctx; | |
449 | ||
450 | /* For now, load gpu on open.. to avoid the requirement of having | |
451 | * firmware in the initrd. | |
452 | */ | |
453 | load_gpu(dev); | |
454 | ||
455 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
456 | if (!ctx) | |
457 | return -ENOMEM; | |
458 | ||
459 | file->driver_priv = ctx; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
c8afe684 RC |
464 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
465 | { | |
466 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 467 | struct msm_file_private *ctx = file->driver_priv; |
c8afe684 | 468 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 469 | |
7198e6b0 RC |
470 | mutex_lock(&dev->struct_mutex); |
471 | if (ctx == priv->lastctx) | |
472 | priv->lastctx = NULL; | |
473 | mutex_unlock(&dev->struct_mutex); | |
474 | ||
475 | kfree(ctx); | |
c8afe684 RC |
476 | } |
477 | ||
478 | static void msm_lastclose(struct drm_device *dev) | |
479 | { | |
480 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
481 | if (priv->fbdev) |
482 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
483 | } |
484 | ||
e9f0d76f | 485 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
486 | { |
487 | struct drm_device *dev = arg; | |
488 | struct msm_drm_private *priv = dev->dev_private; | |
489 | struct msm_kms *kms = priv->kms; | |
490 | BUG_ON(!kms); | |
491 | return kms->funcs->irq(kms); | |
492 | } | |
493 | ||
494 | static void msm_irq_preinstall(struct drm_device *dev) | |
495 | { | |
496 | struct msm_drm_private *priv = dev->dev_private; | |
497 | struct msm_kms *kms = priv->kms; | |
498 | BUG_ON(!kms); | |
499 | kms->funcs->irq_preinstall(kms); | |
500 | } | |
501 | ||
502 | static int msm_irq_postinstall(struct drm_device *dev) | |
503 | { | |
504 | struct msm_drm_private *priv = dev->dev_private; | |
505 | struct msm_kms *kms = priv->kms; | |
506 | BUG_ON(!kms); | |
507 | return kms->funcs->irq_postinstall(kms); | |
508 | } | |
509 | ||
510 | static void msm_irq_uninstall(struct drm_device *dev) | |
511 | { | |
512 | struct msm_drm_private *priv = dev->dev_private; | |
513 | struct msm_kms *kms = priv->kms; | |
514 | BUG_ON(!kms); | |
515 | kms->funcs->irq_uninstall(kms); | |
516 | } | |
517 | ||
88e72717 | 518 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
519 | { |
520 | struct msm_drm_private *priv = dev->dev_private; | |
521 | struct msm_kms *kms = priv->kms; | |
522 | if (!kms) | |
523 | return -ENXIO; | |
88e72717 TR |
524 | DBG("dev=%p, crtc=%u", dev, pipe); |
525 | return vblank_ctrl_queue_work(priv, pipe, true); | |
c8afe684 RC |
526 | } |
527 | ||
88e72717 | 528 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
529 | { |
530 | struct msm_drm_private *priv = dev->dev_private; | |
531 | struct msm_kms *kms = priv->kms; | |
532 | if (!kms) | |
533 | return; | |
88e72717 TR |
534 | DBG("dev=%p, crtc=%u", dev, pipe); |
535 | vblank_ctrl_queue_work(priv, pipe, false); | |
c8afe684 RC |
536 | } |
537 | ||
538 | /* | |
539 | * DRM debugfs: | |
540 | */ | |
541 | ||
542 | #ifdef CONFIG_DEBUG_FS | |
7198e6b0 RC |
543 | static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) |
544 | { | |
545 | struct msm_drm_private *priv = dev->dev_private; | |
546 | struct msm_gpu *gpu = priv->gpu; | |
547 | ||
548 | if (gpu) { | |
549 | seq_printf(m, "%s Status:\n", gpu->name); | |
550 | gpu->funcs->show(gpu, m); | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
c8afe684 RC |
556 | static int msm_gem_show(struct drm_device *dev, struct seq_file *m) |
557 | { | |
558 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
559 | struct msm_gpu *gpu = priv->gpu; |
560 | ||
561 | if (gpu) { | |
562 | seq_printf(m, "Active Objects (%s):\n", gpu->name); | |
563 | msm_gem_describe_objects(&gpu->active_list, m); | |
564 | } | |
c8afe684 | 565 | |
7198e6b0 | 566 | seq_printf(m, "Inactive Objects:\n"); |
c8afe684 RC |
567 | msm_gem_describe_objects(&priv->inactive_list, m); |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | static int msm_mm_show(struct drm_device *dev, struct seq_file *m) | |
573 | { | |
b04a5906 | 574 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
c8afe684 RC |
575 | } |
576 | ||
577 | static int msm_fb_show(struct drm_device *dev, struct seq_file *m) | |
578 | { | |
579 | struct msm_drm_private *priv = dev->dev_private; | |
580 | struct drm_framebuffer *fb, *fbdev_fb = NULL; | |
581 | ||
582 | if (priv->fbdev) { | |
583 | seq_printf(m, "fbcon "); | |
584 | fbdev_fb = priv->fbdev->fb; | |
585 | msm_framebuffer_describe(fbdev_fb, m); | |
586 | } | |
587 | ||
588 | mutex_lock(&dev->mode_config.fb_lock); | |
589 | list_for_each_entry(fb, &dev->mode_config.fb_list, head) { | |
590 | if (fb == fbdev_fb) | |
591 | continue; | |
592 | ||
593 | seq_printf(m, "user "); | |
594 | msm_framebuffer_describe(fb, m); | |
595 | } | |
596 | mutex_unlock(&dev->mode_config.fb_lock); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | static int show_locked(struct seq_file *m, void *arg) | |
602 | { | |
603 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
604 | struct drm_device *dev = node->minor->dev; | |
605 | int (*show)(struct drm_device *dev, struct seq_file *m) = | |
606 | node->info_ent->data; | |
607 | int ret; | |
608 | ||
609 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
610 | if (ret) | |
611 | return ret; | |
612 | ||
613 | ret = show(dev, m); | |
614 | ||
615 | mutex_unlock(&dev->struct_mutex); | |
616 | ||
617 | return ret; | |
618 | } | |
619 | ||
620 | static struct drm_info_list msm_debugfs_list[] = { | |
7198e6b0 | 621 | {"gpu", show_locked, 0, msm_gpu_show}, |
c8afe684 RC |
622 | {"gem", show_locked, 0, msm_gem_show}, |
623 | { "mm", show_locked, 0, msm_mm_show }, | |
624 | { "fb", show_locked, 0, msm_fb_show }, | |
625 | }; | |
626 | ||
a7d3c950 RC |
627 | static int late_init_minor(struct drm_minor *minor) |
628 | { | |
629 | int ret; | |
630 | ||
631 | if (!minor) | |
632 | return 0; | |
633 | ||
634 | ret = msm_rd_debugfs_init(minor); | |
635 | if (ret) { | |
636 | dev_err(minor->dev->dev, "could not install rd debugfs\n"); | |
637 | return ret; | |
638 | } | |
639 | ||
70c70f09 RC |
640 | ret = msm_perf_debugfs_init(minor); |
641 | if (ret) { | |
642 | dev_err(minor->dev->dev, "could not install perf debugfs\n"); | |
643 | return ret; | |
644 | } | |
645 | ||
a7d3c950 RC |
646 | return 0; |
647 | } | |
648 | ||
649 | int msm_debugfs_late_init(struct drm_device *dev) | |
650 | { | |
651 | int ret; | |
652 | ret = late_init_minor(dev->primary); | |
653 | if (ret) | |
654 | return ret; | |
655 | ret = late_init_minor(dev->render); | |
656 | if (ret) | |
657 | return ret; | |
658 | ret = late_init_minor(dev->control); | |
659 | return ret; | |
660 | } | |
661 | ||
c8afe684 RC |
662 | static int msm_debugfs_init(struct drm_minor *minor) |
663 | { | |
664 | struct drm_device *dev = minor->dev; | |
665 | int ret; | |
666 | ||
667 | ret = drm_debugfs_create_files(msm_debugfs_list, | |
668 | ARRAY_SIZE(msm_debugfs_list), | |
669 | minor->debugfs_root, minor); | |
670 | ||
671 | if (ret) { | |
672 | dev_err(dev->dev, "could not install msm_debugfs_list\n"); | |
673 | return ret; | |
674 | } | |
675 | ||
a7d3c950 | 676 | return 0; |
c8afe684 RC |
677 | } |
678 | ||
679 | static void msm_debugfs_cleanup(struct drm_minor *minor) | |
680 | { | |
681 | drm_debugfs_remove_files(msm_debugfs_list, | |
682 | ARRAY_SIZE(msm_debugfs_list), minor); | |
a7d3c950 RC |
683 | if (!minor->dev->dev_private) |
684 | return; | |
685 | msm_rd_debugfs_cleanup(minor); | |
70c70f09 | 686 | msm_perf_debugfs_cleanup(minor); |
c8afe684 RC |
687 | } |
688 | #endif | |
689 | ||
7198e6b0 RC |
690 | /* |
691 | * Fences: | |
692 | */ | |
693 | ||
a9702ca2 WX |
694 | int msm_wait_fence(struct drm_device *dev, uint32_t fence, |
695 | ktime_t *timeout , bool interruptible) | |
7198e6b0 RC |
696 | { |
697 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
698 | int ret; |
699 | ||
f816f272 RC |
700 | if (!priv->gpu) |
701 | return 0; | |
702 | ||
703 | if (fence > priv->gpu->submitted_fence) { | |
704 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
705 | fence, priv->gpu->submitted_fence); | |
706 | return -EINVAL; | |
707 | } | |
708 | ||
709 | if (!timeout) { | |
710 | /* no-wait: */ | |
711 | ret = fence_completed(dev, fence) ? 0 : -EBUSY; | |
712 | } else { | |
56c2da83 | 713 | ktime_t now = ktime_get(); |
f816f272 RC |
714 | unsigned long remaining_jiffies; |
715 | ||
56c2da83 | 716 | if (ktime_compare(*timeout, now) < 0) { |
f816f272 | 717 | remaining_jiffies = 0; |
56c2da83 RC |
718 | } else { |
719 | ktime_t rem = ktime_sub(*timeout, now); | |
720 | struct timespec ts = ktime_to_timespec(rem); | |
721 | remaining_jiffies = timespec_to_jiffies(&ts); | |
722 | } | |
f816f272 | 723 | |
a9702ca2 WX |
724 | if (interruptible) |
725 | ret = wait_event_interruptible_timeout(priv->fence_event, | |
726 | fence_completed(dev, fence), | |
727 | remaining_jiffies); | |
728 | else | |
729 | ret = wait_event_timeout(priv->fence_event, | |
f816f272 RC |
730 | fence_completed(dev, fence), |
731 | remaining_jiffies); | |
732 | ||
733 | if (ret == 0) { | |
734 | DBG("timeout waiting for fence: %u (completed: %u)", | |
735 | fence, priv->completed_fence); | |
736 | ret = -ETIMEDOUT; | |
737 | } else if (ret != -ERESTARTSYS) { | |
738 | ret = 0; | |
739 | } | |
7198e6b0 RC |
740 | } |
741 | ||
742 | return ret; | |
743 | } | |
744 | ||
69193e50 RC |
745 | int msm_queue_fence_cb(struct drm_device *dev, |
746 | struct msm_fence_cb *cb, uint32_t fence) | |
747 | { | |
748 | struct msm_drm_private *priv = dev->dev_private; | |
749 | int ret = 0; | |
750 | ||
751 | mutex_lock(&dev->struct_mutex); | |
752 | if (!list_empty(&cb->work.entry)) { | |
753 | ret = -EINVAL; | |
754 | } else if (fence > priv->completed_fence) { | |
755 | cb->fence = fence; | |
756 | list_add_tail(&cb->work.entry, &priv->fence_cbs); | |
757 | } else { | |
758 | queue_work(priv->wq, &cb->work); | |
759 | } | |
760 | mutex_unlock(&dev->struct_mutex); | |
761 | ||
762 | return ret; | |
763 | } | |
764 | ||
edd4fc63 | 765 | /* called from workqueue */ |
7198e6b0 RC |
766 | void msm_update_fence(struct drm_device *dev, uint32_t fence) |
767 | { | |
768 | struct msm_drm_private *priv = dev->dev_private; | |
769 | ||
edd4fc63 RC |
770 | mutex_lock(&dev->struct_mutex); |
771 | priv->completed_fence = max(fence, priv->completed_fence); | |
772 | ||
773 | while (!list_empty(&priv->fence_cbs)) { | |
774 | struct msm_fence_cb *cb; | |
775 | ||
776 | cb = list_first_entry(&priv->fence_cbs, | |
777 | struct msm_fence_cb, work.entry); | |
778 | ||
779 | if (cb->fence > priv->completed_fence) | |
780 | break; | |
781 | ||
782 | list_del_init(&cb->work.entry); | |
783 | queue_work(priv->wq, &cb->work); | |
7198e6b0 | 784 | } |
edd4fc63 RC |
785 | |
786 | mutex_unlock(&dev->struct_mutex); | |
787 | ||
788 | wake_up_all(&priv->fence_event); | |
789 | } | |
790 | ||
791 | void __msm_fence_worker(struct work_struct *work) | |
792 | { | |
793 | struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work); | |
794 | cb->func(cb); | |
7198e6b0 RC |
795 | } |
796 | ||
797 | /* | |
798 | * DRM ioctls: | |
799 | */ | |
800 | ||
801 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
802 | struct drm_file *file) | |
803 | { | |
804 | struct msm_drm_private *priv = dev->dev_private; | |
805 | struct drm_msm_param *args = data; | |
806 | struct msm_gpu *gpu; | |
807 | ||
808 | /* for now, we just have 3d pipe.. eventually this would need to | |
809 | * be more clever to dispatch to appropriate gpu module: | |
810 | */ | |
811 | if (args->pipe != MSM_PIPE_3D0) | |
812 | return -EINVAL; | |
813 | ||
814 | gpu = priv->gpu; | |
815 | ||
816 | if (!gpu) | |
817 | return -ENXIO; | |
818 | ||
819 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
820 | } | |
821 | ||
822 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
823 | struct drm_file *file) | |
824 | { | |
825 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
826 | |
827 | if (args->flags & ~MSM_BO_FLAGS) { | |
828 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
829 | return -EINVAL; | |
830 | } | |
831 | ||
7198e6b0 RC |
832 | return msm_gem_new_handle(dev, file, args->size, |
833 | args->flags, &args->handle); | |
834 | } | |
835 | ||
56c2da83 RC |
836 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
837 | { | |
838 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
839 | } | |
7198e6b0 RC |
840 | |
841 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
842 | struct drm_file *file) | |
843 | { | |
844 | struct drm_msm_gem_cpu_prep *args = data; | |
845 | struct drm_gem_object *obj; | |
56c2da83 | 846 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
847 | int ret; |
848 | ||
93ddb0d3 RC |
849 | if (args->op & ~MSM_PREP_FLAGS) { |
850 | DRM_ERROR("invalid op: %08x\n", args->op); | |
851 | return -EINVAL; | |
852 | } | |
853 | ||
7198e6b0 RC |
854 | obj = drm_gem_object_lookup(dev, file, args->handle); |
855 | if (!obj) | |
856 | return -ENOENT; | |
857 | ||
56c2da83 | 858 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
859 | |
860 | drm_gem_object_unreference_unlocked(obj); | |
861 | ||
862 | return ret; | |
863 | } | |
864 | ||
865 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
866 | struct drm_file *file) | |
867 | { | |
868 | struct drm_msm_gem_cpu_fini *args = data; | |
869 | struct drm_gem_object *obj; | |
870 | int ret; | |
871 | ||
872 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
873 | if (!obj) | |
874 | return -ENOENT; | |
875 | ||
876 | ret = msm_gem_cpu_fini(obj); | |
877 | ||
878 | drm_gem_object_unreference_unlocked(obj); | |
879 | ||
880 | return ret; | |
881 | } | |
882 | ||
883 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
884 | struct drm_file *file) | |
885 | { | |
886 | struct drm_msm_gem_info *args = data; | |
887 | struct drm_gem_object *obj; | |
888 | int ret = 0; | |
889 | ||
890 | if (args->pad) | |
891 | return -EINVAL; | |
892 | ||
893 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
894 | if (!obj) | |
895 | return -ENOENT; | |
896 | ||
897 | args->offset = msm_gem_mmap_offset(obj); | |
898 | ||
899 | drm_gem_object_unreference_unlocked(obj); | |
900 | ||
901 | return ret; | |
902 | } | |
903 | ||
904 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
905 | struct drm_file *file) | |
906 | { | |
907 | struct drm_msm_wait_fence *args = data; | |
56c2da83 | 908 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
909 | |
910 | if (args->pad) { | |
911 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
a9702ca2 | 915 | return msm_wait_fence(dev, args->fence, &timeout, true); |
7198e6b0 RC |
916 | } |
917 | ||
918 | static const struct drm_ioctl_desc msm_ioctls[] = { | |
f8c47144 DV |
919 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
920 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
921 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
922 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
923 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
924 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), | |
925 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), | |
7198e6b0 RC |
926 | }; |
927 | ||
c8afe684 RC |
928 | static const struct vm_operations_struct vm_ops = { |
929 | .fault = msm_gem_fault, | |
930 | .open = drm_gem_vm_open, | |
931 | .close = drm_gem_vm_close, | |
932 | }; | |
933 | ||
934 | static const struct file_operations fops = { | |
935 | .owner = THIS_MODULE, | |
936 | .open = drm_open, | |
937 | .release = drm_release, | |
938 | .unlocked_ioctl = drm_ioctl, | |
939 | #ifdef CONFIG_COMPAT | |
940 | .compat_ioctl = drm_compat_ioctl, | |
941 | #endif | |
942 | .poll = drm_poll, | |
943 | .read = drm_read, | |
944 | .llseek = no_llseek, | |
945 | .mmap = msm_gem_mmap, | |
946 | }; | |
947 | ||
948 | static struct drm_driver msm_driver = { | |
05b84911 RC |
949 | .driver_features = DRIVER_HAVE_IRQ | |
950 | DRIVER_GEM | | |
951 | DRIVER_PRIME | | |
b4b15c86 | 952 | DRIVER_RENDER | |
a5436e1d | 953 | DRIVER_ATOMIC | |
05b84911 | 954 | DRIVER_MODESET, |
c8afe684 RC |
955 | .load = msm_load, |
956 | .unload = msm_unload, | |
7198e6b0 | 957 | .open = msm_open, |
c8afe684 RC |
958 | .preclose = msm_preclose, |
959 | .lastclose = msm_lastclose, | |
915b4d11 | 960 | .set_busid = drm_platform_set_busid, |
c8afe684 RC |
961 | .irq_handler = msm_irq, |
962 | .irq_preinstall = msm_irq_preinstall, | |
963 | .irq_postinstall = msm_irq_postinstall, | |
964 | .irq_uninstall = msm_irq_uninstall, | |
b44f8408 | 965 | .get_vblank_counter = drm_vblank_no_hw_counter, |
c8afe684 RC |
966 | .enable_vblank = msm_enable_vblank, |
967 | .disable_vblank = msm_disable_vblank, | |
968 | .gem_free_object = msm_gem_free_object, | |
969 | .gem_vm_ops = &vm_ops, | |
970 | .dumb_create = msm_gem_dumb_create, | |
971 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 972 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
973 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
974 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
975 | .gem_prime_export = drm_gem_prime_export, | |
976 | .gem_prime_import = drm_gem_prime_import, | |
977 | .gem_prime_pin = msm_gem_prime_pin, | |
978 | .gem_prime_unpin = msm_gem_prime_unpin, | |
979 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
980 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
981 | .gem_prime_vmap = msm_gem_prime_vmap, | |
982 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 983 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
984 | #ifdef CONFIG_DEBUG_FS |
985 | .debugfs_init = msm_debugfs_init, | |
986 | .debugfs_cleanup = msm_debugfs_cleanup, | |
987 | #endif | |
7198e6b0 RC |
988 | .ioctls = msm_ioctls, |
989 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
990 | .fops = &fops, |
991 | .name = "msm", | |
992 | .desc = "MSM Snapdragon DRM", | |
993 | .date = "20130625", | |
994 | .major = 1, | |
995 | .minor = 0, | |
996 | }; | |
997 | ||
998 | #ifdef CONFIG_PM_SLEEP | |
999 | static int msm_pm_suspend(struct device *dev) | |
1000 | { | |
1001 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1002 | ||
1003 | drm_kms_helper_poll_disable(ddev); | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static int msm_pm_resume(struct device *dev) | |
1009 | { | |
1010 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1011 | ||
1012 | drm_kms_helper_poll_enable(ddev); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | #endif | |
1017 | ||
1018 | static const struct dev_pm_ops msm_pm_ops = { | |
1019 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
1020 | }; | |
1021 | ||
060530f1 RC |
1022 | /* |
1023 | * Componentized driver support: | |
1024 | */ | |
1025 | ||
e9fbdaf2 AT |
1026 | /* |
1027 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
1028 | * so probably some room for some helpers | |
060530f1 RC |
1029 | */ |
1030 | static int compare_of(struct device *dev, void *data) | |
1031 | { | |
1032 | return dev->of_node == data; | |
1033 | } | |
41e69778 RC |
1034 | |
1035 | static int add_components(struct device *dev, struct component_match **matchptr, | |
1036 | const char *name) | |
1037 | { | |
1038 | struct device_node *np = dev->of_node; | |
1039 | unsigned i; | |
1040 | ||
1041 | for (i = 0; ; i++) { | |
1042 | struct device_node *node; | |
1043 | ||
1044 | node = of_parse_phandle(np, name, i); | |
1045 | if (!node) | |
1046 | break; | |
1047 | ||
1048 | component_match_add(dev, matchptr, compare_of, node); | |
1049 | } | |
1050 | ||
1051 | return 0; | |
1052 | } | |
84448288 RK |
1053 | |
1054 | static int msm_drm_bind(struct device *dev) | |
1055 | { | |
1056 | return drm_platform_init(&msm_driver, to_platform_device(dev)); | |
1057 | } | |
1058 | ||
1059 | static void msm_drm_unbind(struct device *dev) | |
1060 | { | |
1061 | drm_put_dev(platform_get_drvdata(to_platform_device(dev))); | |
1062 | } | |
1063 | ||
1064 | static const struct component_master_ops msm_drm_ops = { | |
1065 | .bind = msm_drm_bind, | |
1066 | .unbind = msm_drm_unbind, | |
1067 | }; | |
1068 | ||
1069 | /* | |
1070 | * Platform driver: | |
1071 | */ | |
060530f1 | 1072 | |
84448288 | 1073 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1074 | { |
84448288 | 1075 | struct component_match *match = NULL; |
e9fbdaf2 | 1076 | |
41e69778 RC |
1077 | add_components(&pdev->dev, &match, "connectors"); |
1078 | add_components(&pdev->dev, &match, "gpus"); | |
060530f1 | 1079 | |
871d812a | 1080 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 1081 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1082 | } |
1083 | ||
1084 | static int msm_pdev_remove(struct platform_device *pdev) | |
1085 | { | |
060530f1 | 1086 | component_master_del(&pdev->dev, &msm_drm_ops); |
c8afe684 RC |
1087 | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | static const struct platform_device_id msm_id[] = { | |
1092 | { "mdp", 0 }, | |
1093 | { } | |
1094 | }; | |
1095 | ||
06c0dd96 | 1096 | static const struct of_device_id dt_match[] = { |
d4fc72ed AT |
1097 | { .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */ |
1098 | { .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */ | |
1099 | /* to support downstream DT files */ | |
1100 | { .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */ | |
06c0dd96 RC |
1101 | {} |
1102 | }; | |
1103 | MODULE_DEVICE_TABLE(of, dt_match); | |
1104 | ||
c8afe684 RC |
1105 | static struct platform_driver msm_platform_driver = { |
1106 | .probe = msm_pdev_probe, | |
1107 | .remove = msm_pdev_remove, | |
1108 | .driver = { | |
c8afe684 | 1109 | .name = "msm", |
06c0dd96 | 1110 | .of_match_table = dt_match, |
c8afe684 RC |
1111 | .pm = &msm_pm_ops, |
1112 | }, | |
1113 | .id_table = msm_id, | |
1114 | }; | |
1115 | ||
1116 | static int __init msm_drm_register(void) | |
1117 | { | |
1118 | DBG("init"); | |
d5af49c9 | 1119 | msm_dsi_register(); |
00453981 | 1120 | msm_edp_register(); |
fcda50c8 | 1121 | msm_hdmi_register(); |
bfd28b13 | 1122 | adreno_register(); |
c8afe684 RC |
1123 | return platform_driver_register(&msm_platform_driver); |
1124 | } | |
1125 | ||
1126 | static void __exit msm_drm_unregister(void) | |
1127 | { | |
1128 | DBG("fini"); | |
1129 | platform_driver_unregister(&msm_platform_driver); | |
fcda50c8 | 1130 | msm_hdmi_unregister(); |
bfd28b13 | 1131 | adreno_unregister(); |
00453981 | 1132 | msm_edp_unregister(); |
d5af49c9 | 1133 | msm_dsi_unregister(); |
c8afe684 RC |
1134 | } |
1135 | ||
1136 | module_init(msm_drm_register); | |
1137 | module_exit(msm_drm_unregister); | |
1138 | ||
1139 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1140 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1141 | MODULE_LICENSE("GPL"); |