Commit | Line | Data |
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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
edcd60ce | 19 | #include "msm_debugfs.h" |
fde5de6c | 20 | #include "msm_fence.h" |
7198e6b0 | 21 | #include "msm_gpu.h" |
dd2da6e3 | 22 | #include "msm_kms.h" |
c8afe684 | 23 | |
a8d854c1 RC |
24 | |
25 | /* | |
26 | * MSM driver version: | |
27 | * - 1.0.0 - initial interface | |
28 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers | |
29 | */ | |
30 | #define MSM_VERSION_MAJOR 1 | |
31 | #define MSM_VERSION_MINOR 1 | |
32 | #define MSM_VERSION_PATCHLEVEL 0 | |
33 | ||
c8afe684 RC |
34 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
35 | { | |
36 | struct msm_drm_private *priv = dev->dev_private; | |
37 | if (priv->fbdev) | |
38 | drm_fb_helper_hotplug_event(priv->fbdev); | |
39 | } | |
40 | ||
41 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
42 | .fb_create = msm_framebuffer_create, | |
43 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 44 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 45 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
46 | }; |
47 | ||
871d812a | 48 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
49 | { |
50 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 51 | int idx = priv->num_mmus++; |
c8afe684 | 52 | |
871d812a | 53 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
54 | return -EINVAL; |
55 | ||
871d812a | 56 | priv->mmus[idx] = mmu; |
c8afe684 RC |
57 | |
58 | return idx; | |
59 | } | |
60 | ||
c8afe684 RC |
61 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
62 | static bool reglog = false; | |
63 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
64 | module_param(reglog, bool, 0600); | |
65 | #else | |
66 | #define reglog 0 | |
67 | #endif | |
68 | ||
a9ee34b7 | 69 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
70 | static bool fbdev = true; |
71 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
72 | module_param(fbdev, bool, 0600); | |
73 | #endif | |
74 | ||
3a10ba8c | 75 | static char *vram = "16m"; |
4313c744 | 76 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
871d812a RC |
77 | module_param(vram, charp, 0); |
78 | ||
060530f1 RC |
79 | /* |
80 | * Util/helpers: | |
81 | */ | |
82 | ||
c8afe684 RC |
83 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
84 | const char *dbgname) | |
85 | { | |
86 | struct resource *res; | |
87 | unsigned long size; | |
88 | void __iomem *ptr; | |
89 | ||
90 | if (name) | |
91 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
92 | else | |
93 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
94 | ||
95 | if (!res) { | |
96 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
97 | return ERR_PTR(-EINVAL); | |
98 | } | |
99 | ||
100 | size = resource_size(res); | |
101 | ||
102 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
103 | if (!ptr) { | |
104 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
105 | return ERR_PTR(-ENOMEM); | |
106 | } | |
107 | ||
108 | if (reglog) | |
fc99f97a | 109 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
110 | |
111 | return ptr; | |
112 | } | |
113 | ||
114 | void msm_writel(u32 data, void __iomem *addr) | |
115 | { | |
116 | if (reglog) | |
fc99f97a | 117 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
118 | writel(data, addr); |
119 | } | |
120 | ||
121 | u32 msm_readl(const void __iomem *addr) | |
122 | { | |
123 | u32 val = readl(addr); | |
124 | if (reglog) | |
fc99f97a | 125 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
c8afe684 RC |
126 | return val; |
127 | } | |
128 | ||
78b1d470 HL |
129 | struct vblank_event { |
130 | struct list_head node; | |
131 | int crtc_id; | |
132 | bool enable; | |
133 | }; | |
134 | ||
135 | static void vblank_ctrl_worker(struct work_struct *work) | |
136 | { | |
137 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, | |
138 | struct msm_vblank_ctrl, work); | |
139 | struct msm_drm_private *priv = container_of(vbl_ctrl, | |
140 | struct msm_drm_private, vblank_ctrl); | |
141 | struct msm_kms *kms = priv->kms; | |
142 | struct vblank_event *vbl_ev, *tmp; | |
143 | unsigned long flags; | |
144 | ||
145 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
146 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
147 | list_del(&vbl_ev->node); | |
148 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
149 | ||
150 | if (vbl_ev->enable) | |
151 | kms->funcs->enable_vblank(kms, | |
152 | priv->crtcs[vbl_ev->crtc_id]); | |
153 | else | |
154 | kms->funcs->disable_vblank(kms, | |
155 | priv->crtcs[vbl_ev->crtc_id]); | |
156 | ||
157 | kfree(vbl_ev); | |
158 | ||
159 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
160 | } | |
161 | ||
162 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
163 | } | |
164 | ||
165 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
166 | int crtc_id, bool enable) | |
167 | { | |
168 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; | |
169 | struct vblank_event *vbl_ev; | |
170 | unsigned long flags; | |
171 | ||
172 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); | |
173 | if (!vbl_ev) | |
174 | return -ENOMEM; | |
175 | ||
176 | vbl_ev->crtc_id = crtc_id; | |
177 | vbl_ev->enable = enable; | |
178 | ||
179 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
180 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); | |
181 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
182 | ||
183 | queue_work(priv->wq, &vbl_ctrl->work); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
2b669875 | 188 | static int msm_drm_uninit(struct device *dev) |
c8afe684 | 189 | { |
2b669875 AT |
190 | struct platform_device *pdev = to_platform_device(dev); |
191 | struct drm_device *ddev = platform_get_drvdata(pdev); | |
192 | struct msm_drm_private *priv = ddev->dev_private; | |
c8afe684 | 193 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 194 | struct msm_gpu *gpu = priv->gpu; |
78b1d470 HL |
195 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
196 | struct vblank_event *vbl_ev, *tmp; | |
197 | ||
198 | /* We must cancel and cleanup any pending vblank enable/disable | |
199 | * work before drm_irq_uninstall() to avoid work re-enabling an | |
200 | * irq after uninstall has disabled it. | |
201 | */ | |
202 | cancel_work_sync(&vbl_ctrl->work); | |
203 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
204 | list_del(&vbl_ev->node); | |
205 | kfree(vbl_ev); | |
206 | } | |
c8afe684 | 207 | |
68209390 RC |
208 | msm_gem_shrinker_cleanup(ddev); |
209 | ||
2b669875 AT |
210 | drm_kms_helper_poll_fini(ddev); |
211 | ||
2b669875 | 212 | drm_dev_unregister(ddev); |
8208ed93 | 213 | |
1aaa57f5 AT |
214 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
215 | if (fbdev && priv->fbdev) | |
2b669875 | 216 | msm_fbdev_free(ddev); |
1aaa57f5 | 217 | #endif |
2b669875 | 218 | drm_mode_config_cleanup(ddev); |
c8afe684 | 219 | |
2b669875 AT |
220 | pm_runtime_get_sync(dev); |
221 | drm_irq_uninstall(ddev); | |
222 | pm_runtime_put_sync(dev); | |
c8afe684 RC |
223 | |
224 | flush_workqueue(priv->wq); | |
225 | destroy_workqueue(priv->wq); | |
226 | ||
ba00c3f2 RC |
227 | flush_workqueue(priv->atomic_wq); |
228 | destroy_workqueue(priv->atomic_wq); | |
229 | ||
cd792726 | 230 | if (kms) |
c8afe684 | 231 | kms->funcs->destroy(kms); |
c8afe684 | 232 | |
7198e6b0 | 233 | if (gpu) { |
2b669875 | 234 | mutex_lock(&ddev->struct_mutex); |
7198e6b0 | 235 | gpu->funcs->pm_suspend(gpu); |
2b669875 | 236 | mutex_unlock(&ddev->struct_mutex); |
774449eb | 237 | gpu->funcs->destroy(gpu); |
7198e6b0 | 238 | } |
c8afe684 | 239 | |
871d812a RC |
240 | if (priv->vram.paddr) { |
241 | DEFINE_DMA_ATTRS(attrs); | |
242 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
243 | drm_mm_takedown(&priv->vram.mm); | |
2b669875 AT |
244 | dma_free_attrs(dev, priv->vram.size, NULL, |
245 | priv->vram.paddr, &attrs); | |
871d812a RC |
246 | } |
247 | ||
2b669875 | 248 | component_unbind_all(dev, ddev); |
060530f1 | 249 | |
0a6030d2 AT |
250 | msm_mdss_destroy(ddev); |
251 | ||
2b669875 AT |
252 | ddev->dev_private = NULL; |
253 | drm_dev_unref(ddev); | |
c8afe684 RC |
254 | |
255 | kfree(priv); | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
06c0dd96 RC |
260 | static int get_mdp_ver(struct platform_device *pdev) |
261 | { | |
06c0dd96 | 262 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
263 | |
264 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
265 | } |
266 | ||
072f1f91 RC |
267 | #include <linux/of_address.h> |
268 | ||
5bf9c0b6 | 269 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 270 | { |
5bf9c0b6 | 271 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 272 | struct device_node *node; |
072f1f91 RC |
273 | unsigned long size = 0; |
274 | int ret = 0; | |
275 | ||
072f1f91 RC |
276 | /* In the device-tree world, we could have a 'memory-region' |
277 | * phandle, which gives us a link to our "vram". Allocating | |
278 | * is all nicely abstracted behind the dma api, but we need | |
279 | * to know the entire size to allocate it all in one go. There | |
280 | * are two cases: | |
281 | * 1) device with no IOMMU, in which case we need exclusive | |
282 | * access to a VRAM carveout big enough for all gpu | |
283 | * buffers | |
284 | * 2) device with IOMMU, but where the bootloader puts up | |
285 | * a splash screen. In this case, the VRAM carveout | |
286 | * need only be large enough for fbdev fb. But we need | |
287 | * exclusive access to the buffer to avoid the kernel | |
288 | * using those pages for other purposes (which appears | |
289 | * as corruption on screen before we have a chance to | |
290 | * load and do initial modeset) | |
291 | */ | |
072f1f91 RC |
292 | |
293 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
294 | if (node) { | |
295 | struct resource r; | |
296 | ret = of_address_to_resource(node, 0, &r); | |
2ca41c17 | 297 | of_node_put(node); |
072f1f91 RC |
298 | if (ret) |
299 | return ret; | |
300 | size = r.end - r.start; | |
fc99f97a | 301 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 302 | |
e9fbdaf2 AT |
303 | /* if we have no IOMMU, then we need to use carveout allocator. |
304 | * Grab the entire CMA chunk carved out in early startup in | |
305 | * mach-msm: | |
306 | */ | |
307 | } else if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
308 | DRM_INFO("using %s VRAM carveout\n", vram); |
309 | size = memparse(vram, NULL); | |
310 | } | |
311 | ||
312 | if (size) { | |
871d812a | 313 | DEFINE_DMA_ATTRS(attrs); |
871d812a RC |
314 | void *p; |
315 | ||
871d812a RC |
316 | priv->vram.size = size; |
317 | ||
318 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
319 | ||
320 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
321 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
322 | ||
323 | /* note that for no-kernel-mapping, the vaddr returned | |
324 | * is bogus, but non-null if allocation succeeded: | |
325 | */ | |
326 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 327 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
328 | if (!p) { |
329 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
330 | priv->vram.paddr = 0; | |
5bf9c0b6 | 331 | return -ENOMEM; |
871d812a RC |
332 | } |
333 | ||
334 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
335 | (uint32_t)priv->vram.paddr, | |
336 | (uint32_t)(priv->vram.paddr + size)); | |
337 | } | |
338 | ||
072f1f91 | 339 | return ret; |
5bf9c0b6 RC |
340 | } |
341 | ||
2b669875 | 342 | static int msm_drm_init(struct device *dev, struct drm_driver *drv) |
5bf9c0b6 | 343 | { |
2b669875 AT |
344 | struct platform_device *pdev = to_platform_device(dev); |
345 | struct drm_device *ddev; | |
5bf9c0b6 RC |
346 | struct msm_drm_private *priv; |
347 | struct msm_kms *kms; | |
348 | int ret; | |
349 | ||
2b669875 AT |
350 | ddev = drm_dev_alloc(drv, dev); |
351 | if (!ddev) { | |
352 | dev_err(dev, "failed to allocate drm_device\n"); | |
353 | return -ENOMEM; | |
354 | } | |
355 | ||
356 | platform_set_drvdata(pdev, ddev); | |
357 | ddev->platformdev = pdev; | |
358 | ||
5bf9c0b6 RC |
359 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
360 | if (!priv) { | |
2b669875 | 361 | drm_dev_unref(ddev); |
5bf9c0b6 RC |
362 | return -ENOMEM; |
363 | } | |
364 | ||
2b669875 | 365 | ddev->dev_private = priv; |
68209390 | 366 | priv->dev = ddev; |
5bf9c0b6 | 367 | |
0a6030d2 AT |
368 | ret = msm_mdss_init(ddev); |
369 | if (ret) { | |
370 | kfree(priv); | |
371 | drm_dev_unref(ddev); | |
372 | return ret; | |
373 | } | |
374 | ||
5bf9c0b6 | 375 | priv->wq = alloc_ordered_workqueue("msm", 0); |
ba00c3f2 | 376 | priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0); |
5bf9c0b6 RC |
377 | init_waitqueue_head(&priv->pending_crtcs_event); |
378 | ||
379 | INIT_LIST_HEAD(&priv->inactive_list); | |
78b1d470 HL |
380 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
381 | INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); | |
382 | spin_lock_init(&priv->vblank_ctrl.lock); | |
5bf9c0b6 | 383 | |
2b669875 | 384 | drm_mode_config_init(ddev); |
060530f1 RC |
385 | |
386 | /* Bind all our sub-components: */ | |
2b669875 AT |
387 | ret = component_bind_all(dev, ddev); |
388 | if (ret) { | |
0a6030d2 | 389 | msm_mdss_destroy(ddev); |
2b669875 AT |
390 | kfree(priv); |
391 | drm_dev_unref(ddev); | |
060530f1 | 392 | return ret; |
2b669875 | 393 | } |
060530f1 | 394 | |
2b669875 | 395 | ret = msm_init_vram(ddev); |
13f15565 RC |
396 | if (ret) |
397 | goto fail; | |
398 | ||
68209390 RC |
399 | msm_gem_shrinker_init(ddev); |
400 | ||
06c0dd96 RC |
401 | switch (get_mdp_ver(pdev)) { |
402 | case 4: | |
2b669875 | 403 | kms = mdp4_kms_init(ddev); |
0a6030d2 | 404 | priv->kms = kms; |
06c0dd96 RC |
405 | break; |
406 | case 5: | |
392ae6e0 | 407 | kms = mdp5_kms_init(ddev); |
06c0dd96 RC |
408 | break; |
409 | default: | |
410 | kms = ERR_PTR(-ENODEV); | |
411 | break; | |
412 | } | |
413 | ||
c8afe684 RC |
414 | if (IS_ERR(kms)) { |
415 | /* | |
416 | * NOTE: once we have GPU support, having no kms should not | |
417 | * be considered fatal.. ideally we would still support gpu | |
418 | * and (for example) use dmabuf/prime to share buffers with | |
419 | * imx drm driver on iMX5 | |
420 | */ | |
2b669875 | 421 | dev_err(dev, "failed to load kms\n"); |
e4826a94 | 422 | ret = PTR_ERR(kms); |
c8afe684 RC |
423 | goto fail; |
424 | } | |
425 | ||
c8afe684 | 426 | if (kms) { |
c8afe684 RC |
427 | ret = kms->funcs->hw_init(kms); |
428 | if (ret) { | |
2b669875 | 429 | dev_err(dev, "kms hw init failed: %d\n", ret); |
c8afe684 RC |
430 | goto fail; |
431 | } | |
432 | } | |
433 | ||
2b669875 | 434 | ddev->mode_config.funcs = &mode_config_funcs; |
c8afe684 | 435 | |
2b669875 | 436 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
c8afe684 | 437 | if (ret < 0) { |
2b669875 | 438 | dev_err(dev, "failed to initialize vblank\n"); |
c8afe684 RC |
439 | goto fail; |
440 | } | |
441 | ||
a2b3a557 AT |
442 | if (kms) { |
443 | pm_runtime_get_sync(dev); | |
444 | ret = drm_irq_install(ddev, kms->irq); | |
445 | pm_runtime_put_sync(dev); | |
446 | if (ret < 0) { | |
447 | dev_err(dev, "failed to install IRQ handler\n"); | |
448 | goto fail; | |
449 | } | |
c8afe684 RC |
450 | } |
451 | ||
2b669875 AT |
452 | ret = drm_dev_register(ddev, 0); |
453 | if (ret) | |
454 | goto fail; | |
455 | ||
2b669875 | 456 | drm_mode_config_reset(ddev); |
cf3a7e4c | 457 | |
a9ee34b7 | 458 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 | 459 | if (fbdev) |
2b669875 | 460 | priv->fbdev = msm_fbdev_init(ddev); |
c8afe684 RC |
461 | #endif |
462 | ||
2b669875 | 463 | ret = msm_debugfs_late_init(ddev); |
a7d3c950 RC |
464 | if (ret) |
465 | goto fail; | |
466 | ||
2b669875 | 467 | drm_kms_helper_poll_init(ddev); |
c8afe684 RC |
468 | |
469 | return 0; | |
470 | ||
471 | fail: | |
2b669875 | 472 | msm_drm_uninit(dev); |
c8afe684 RC |
473 | return ret; |
474 | } | |
475 | ||
2b669875 AT |
476 | /* |
477 | * DRM operations: | |
478 | */ | |
479 | ||
7198e6b0 RC |
480 | static void load_gpu(struct drm_device *dev) |
481 | { | |
a1ad3523 | 482 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 483 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 484 | |
a1ad3523 RC |
485 | mutex_lock(&init_lock); |
486 | ||
e2550b7a RC |
487 | if (!priv->gpu) |
488 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 489 | |
a1ad3523 | 490 | mutex_unlock(&init_lock); |
7198e6b0 RC |
491 | } |
492 | ||
493 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
494 | { | |
495 | struct msm_file_private *ctx; | |
496 | ||
497 | /* For now, load gpu on open.. to avoid the requirement of having | |
498 | * firmware in the initrd. | |
499 | */ | |
500 | load_gpu(dev); | |
501 | ||
502 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
503 | if (!ctx) | |
504 | return -ENOMEM; | |
505 | ||
506 | file->driver_priv = ctx; | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
c8afe684 RC |
511 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
512 | { | |
513 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 514 | struct msm_file_private *ctx = file->driver_priv; |
7198e6b0 | 515 | |
7198e6b0 RC |
516 | mutex_lock(&dev->struct_mutex); |
517 | if (ctx == priv->lastctx) | |
518 | priv->lastctx = NULL; | |
519 | mutex_unlock(&dev->struct_mutex); | |
520 | ||
521 | kfree(ctx); | |
c8afe684 RC |
522 | } |
523 | ||
524 | static void msm_lastclose(struct drm_device *dev) | |
525 | { | |
526 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
527 | if (priv->fbdev) |
528 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
529 | } |
530 | ||
e9f0d76f | 531 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
532 | { |
533 | struct drm_device *dev = arg; | |
534 | struct msm_drm_private *priv = dev->dev_private; | |
535 | struct msm_kms *kms = priv->kms; | |
536 | BUG_ON(!kms); | |
537 | return kms->funcs->irq(kms); | |
538 | } | |
539 | ||
540 | static void msm_irq_preinstall(struct drm_device *dev) | |
541 | { | |
542 | struct msm_drm_private *priv = dev->dev_private; | |
543 | struct msm_kms *kms = priv->kms; | |
544 | BUG_ON(!kms); | |
545 | kms->funcs->irq_preinstall(kms); | |
546 | } | |
547 | ||
548 | static int msm_irq_postinstall(struct drm_device *dev) | |
549 | { | |
550 | struct msm_drm_private *priv = dev->dev_private; | |
551 | struct msm_kms *kms = priv->kms; | |
552 | BUG_ON(!kms); | |
553 | return kms->funcs->irq_postinstall(kms); | |
554 | } | |
555 | ||
556 | static void msm_irq_uninstall(struct drm_device *dev) | |
557 | { | |
558 | struct msm_drm_private *priv = dev->dev_private; | |
559 | struct msm_kms *kms = priv->kms; | |
560 | BUG_ON(!kms); | |
561 | kms->funcs->irq_uninstall(kms); | |
562 | } | |
563 | ||
88e72717 | 564 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
565 | { |
566 | struct msm_drm_private *priv = dev->dev_private; | |
567 | struct msm_kms *kms = priv->kms; | |
568 | if (!kms) | |
569 | return -ENXIO; | |
88e72717 TR |
570 | DBG("dev=%p, crtc=%u", dev, pipe); |
571 | return vblank_ctrl_queue_work(priv, pipe, true); | |
c8afe684 RC |
572 | } |
573 | ||
88e72717 | 574 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
575 | { |
576 | struct msm_drm_private *priv = dev->dev_private; | |
577 | struct msm_kms *kms = priv->kms; | |
578 | if (!kms) | |
579 | return; | |
88e72717 TR |
580 | DBG("dev=%p, crtc=%u", dev, pipe); |
581 | vblank_ctrl_queue_work(priv, pipe, false); | |
c8afe684 RC |
582 | } |
583 | ||
7198e6b0 RC |
584 | /* |
585 | * DRM ioctls: | |
586 | */ | |
587 | ||
588 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
589 | struct drm_file *file) | |
590 | { | |
591 | struct msm_drm_private *priv = dev->dev_private; | |
592 | struct drm_msm_param *args = data; | |
593 | struct msm_gpu *gpu; | |
594 | ||
595 | /* for now, we just have 3d pipe.. eventually this would need to | |
596 | * be more clever to dispatch to appropriate gpu module: | |
597 | */ | |
598 | if (args->pipe != MSM_PIPE_3D0) | |
599 | return -EINVAL; | |
600 | ||
601 | gpu = priv->gpu; | |
602 | ||
603 | if (!gpu) | |
604 | return -ENXIO; | |
605 | ||
606 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
607 | } | |
608 | ||
609 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
610 | struct drm_file *file) | |
611 | { | |
612 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
613 | |
614 | if (args->flags & ~MSM_BO_FLAGS) { | |
615 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
7198e6b0 RC |
619 | return msm_gem_new_handle(dev, file, args->size, |
620 | args->flags, &args->handle); | |
621 | } | |
622 | ||
56c2da83 RC |
623 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
624 | { | |
625 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
626 | } | |
7198e6b0 RC |
627 | |
628 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
629 | struct drm_file *file) | |
630 | { | |
631 | struct drm_msm_gem_cpu_prep *args = data; | |
632 | struct drm_gem_object *obj; | |
56c2da83 | 633 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
634 | int ret; |
635 | ||
93ddb0d3 RC |
636 | if (args->op & ~MSM_PREP_FLAGS) { |
637 | DRM_ERROR("invalid op: %08x\n", args->op); | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
a8ad0bd8 | 641 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
642 | if (!obj) |
643 | return -ENOENT; | |
644 | ||
56c2da83 | 645 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
646 | |
647 | drm_gem_object_unreference_unlocked(obj); | |
648 | ||
649 | return ret; | |
650 | } | |
651 | ||
652 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
653 | struct drm_file *file) | |
654 | { | |
655 | struct drm_msm_gem_cpu_fini *args = data; | |
656 | struct drm_gem_object *obj; | |
657 | int ret; | |
658 | ||
a8ad0bd8 | 659 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
660 | if (!obj) |
661 | return -ENOENT; | |
662 | ||
663 | ret = msm_gem_cpu_fini(obj); | |
664 | ||
665 | drm_gem_object_unreference_unlocked(obj); | |
666 | ||
667 | return ret; | |
668 | } | |
669 | ||
670 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
671 | struct drm_file *file) | |
672 | { | |
673 | struct drm_msm_gem_info *args = data; | |
674 | struct drm_gem_object *obj; | |
675 | int ret = 0; | |
676 | ||
677 | if (args->pad) | |
678 | return -EINVAL; | |
679 | ||
a8ad0bd8 | 680 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
681 | if (!obj) |
682 | return -ENOENT; | |
683 | ||
684 | args->offset = msm_gem_mmap_offset(obj); | |
685 | ||
686 | drm_gem_object_unreference_unlocked(obj); | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
692 | struct drm_file *file) | |
693 | { | |
ca762a8a | 694 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 695 | struct drm_msm_wait_fence *args = data; |
56c2da83 | 696 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
697 | |
698 | if (args->pad) { | |
699 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
700 | return -EINVAL; | |
701 | } | |
702 | ||
ca762a8a RC |
703 | if (!priv->gpu) |
704 | return 0; | |
705 | ||
706 | return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true); | |
7198e6b0 RC |
707 | } |
708 | ||
4cd33c48 RC |
709 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
710 | struct drm_file *file) | |
711 | { | |
712 | struct drm_msm_gem_madvise *args = data; | |
713 | struct drm_gem_object *obj; | |
714 | int ret; | |
715 | ||
716 | switch (args->madv) { | |
717 | case MSM_MADV_DONTNEED: | |
718 | case MSM_MADV_WILLNEED: | |
719 | break; | |
720 | default: | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
725 | if (ret) | |
726 | return ret; | |
727 | ||
728 | obj = drm_gem_object_lookup(file, args->handle); | |
729 | if (!obj) { | |
730 | ret = -ENOENT; | |
731 | goto unlock; | |
732 | } | |
733 | ||
734 | ret = msm_gem_madvise(obj, args->madv); | |
735 | if (ret >= 0) { | |
736 | args->retained = ret; | |
737 | ret = 0; | |
738 | } | |
739 | ||
740 | drm_gem_object_unreference(obj); | |
741 | ||
742 | unlock: | |
743 | mutex_unlock(&dev->struct_mutex); | |
744 | return ret; | |
745 | } | |
746 | ||
7198e6b0 | 747 | static const struct drm_ioctl_desc msm_ioctls[] = { |
f8c47144 DV |
748 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
749 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
750 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
751 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
752 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
753 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), | |
754 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), | |
4cd33c48 | 755 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW), |
7198e6b0 RC |
756 | }; |
757 | ||
c8afe684 RC |
758 | static const struct vm_operations_struct vm_ops = { |
759 | .fault = msm_gem_fault, | |
760 | .open = drm_gem_vm_open, | |
761 | .close = drm_gem_vm_close, | |
762 | }; | |
763 | ||
764 | static const struct file_operations fops = { | |
765 | .owner = THIS_MODULE, | |
766 | .open = drm_open, | |
767 | .release = drm_release, | |
768 | .unlocked_ioctl = drm_ioctl, | |
769 | #ifdef CONFIG_COMPAT | |
770 | .compat_ioctl = drm_compat_ioctl, | |
771 | #endif | |
772 | .poll = drm_poll, | |
773 | .read = drm_read, | |
774 | .llseek = no_llseek, | |
775 | .mmap = msm_gem_mmap, | |
776 | }; | |
777 | ||
778 | static struct drm_driver msm_driver = { | |
05b84911 RC |
779 | .driver_features = DRIVER_HAVE_IRQ | |
780 | DRIVER_GEM | | |
781 | DRIVER_PRIME | | |
b4b15c86 | 782 | DRIVER_RENDER | |
a5436e1d | 783 | DRIVER_ATOMIC | |
05b84911 | 784 | DRIVER_MODESET, |
7198e6b0 | 785 | .open = msm_open, |
c8afe684 RC |
786 | .preclose = msm_preclose, |
787 | .lastclose = msm_lastclose, | |
788 | .irq_handler = msm_irq, | |
789 | .irq_preinstall = msm_irq_preinstall, | |
790 | .irq_postinstall = msm_irq_postinstall, | |
791 | .irq_uninstall = msm_irq_uninstall, | |
b44f8408 | 792 | .get_vblank_counter = drm_vblank_no_hw_counter, |
c8afe684 RC |
793 | .enable_vblank = msm_enable_vblank, |
794 | .disable_vblank = msm_disable_vblank, | |
795 | .gem_free_object = msm_gem_free_object, | |
796 | .gem_vm_ops = &vm_ops, | |
797 | .dumb_create = msm_gem_dumb_create, | |
798 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 799 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
800 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
801 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
802 | .gem_prime_export = drm_gem_prime_export, | |
803 | .gem_prime_import = drm_gem_prime_import, | |
804 | .gem_prime_pin = msm_gem_prime_pin, | |
805 | .gem_prime_unpin = msm_gem_prime_unpin, | |
806 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
807 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
808 | .gem_prime_vmap = msm_gem_prime_vmap, | |
809 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 810 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
811 | #ifdef CONFIG_DEBUG_FS |
812 | .debugfs_init = msm_debugfs_init, | |
813 | .debugfs_cleanup = msm_debugfs_cleanup, | |
814 | #endif | |
7198e6b0 RC |
815 | .ioctls = msm_ioctls, |
816 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
817 | .fops = &fops, |
818 | .name = "msm", | |
819 | .desc = "MSM Snapdragon DRM", | |
820 | .date = "20130625", | |
a8d854c1 RC |
821 | .major = MSM_VERSION_MAJOR, |
822 | .minor = MSM_VERSION_MINOR, | |
823 | .patchlevel = MSM_VERSION_PATCHLEVEL, | |
c8afe684 RC |
824 | }; |
825 | ||
826 | #ifdef CONFIG_PM_SLEEP | |
827 | static int msm_pm_suspend(struct device *dev) | |
828 | { | |
829 | struct drm_device *ddev = dev_get_drvdata(dev); | |
830 | ||
831 | drm_kms_helper_poll_disable(ddev); | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | static int msm_pm_resume(struct device *dev) | |
837 | { | |
838 | struct drm_device *ddev = dev_get_drvdata(dev); | |
839 | ||
840 | drm_kms_helper_poll_enable(ddev); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | #endif | |
845 | ||
846 | static const struct dev_pm_ops msm_pm_ops = { | |
847 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
848 | }; | |
849 | ||
060530f1 RC |
850 | /* |
851 | * Componentized driver support: | |
852 | */ | |
853 | ||
e9fbdaf2 AT |
854 | /* |
855 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
856 | * so probably some room for some helpers | |
060530f1 RC |
857 | */ |
858 | static int compare_of(struct device *dev, void *data) | |
859 | { | |
860 | return dev->of_node == data; | |
861 | } | |
41e69778 | 862 | |
812070eb AT |
863 | /* |
864 | * Identify what components need to be added by parsing what remote-endpoints | |
865 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there | |
866 | * is no external component that we need to add since LVDS is within MDP4 | |
867 | * itself. | |
868 | */ | |
869 | static int add_components_mdp(struct device *mdp_dev, | |
870 | struct component_match **matchptr) | |
871 | { | |
872 | struct device_node *np = mdp_dev->of_node; | |
873 | struct device_node *ep_node; | |
54011e26 AT |
874 | struct device *master_dev; |
875 | ||
876 | /* | |
877 | * on MDP4 based platforms, the MDP platform device is the component | |
878 | * master that adds other display interface components to itself. | |
879 | * | |
880 | * on MDP5 based platforms, the MDSS platform device is the component | |
881 | * master that adds MDP5 and other display interface components to | |
882 | * itself. | |
883 | */ | |
884 | if (of_device_is_compatible(np, "qcom,mdp4")) | |
885 | master_dev = mdp_dev; | |
886 | else | |
887 | master_dev = mdp_dev->parent; | |
812070eb AT |
888 | |
889 | for_each_endpoint_of_node(np, ep_node) { | |
890 | struct device_node *intf; | |
891 | struct of_endpoint ep; | |
892 | int ret; | |
893 | ||
894 | ret = of_graph_parse_endpoint(ep_node, &ep); | |
895 | if (ret) { | |
896 | dev_err(mdp_dev, "unable to parse port endpoint\n"); | |
897 | of_node_put(ep_node); | |
898 | return ret; | |
899 | } | |
900 | ||
901 | /* | |
902 | * The LCDC/LVDS port on MDP4 is a speacial case where the | |
903 | * remote-endpoint isn't a component that we need to add | |
904 | */ | |
905 | if (of_device_is_compatible(np, "qcom,mdp4") && | |
906 | ep.port == 0) { | |
907 | of_node_put(ep_node); | |
908 | continue; | |
909 | } | |
910 | ||
911 | /* | |
912 | * It's okay if some of the ports don't have a remote endpoint | |
913 | * specified. It just means that the port isn't connected to | |
914 | * any external interface. | |
915 | */ | |
916 | intf = of_graph_get_remote_port_parent(ep_node); | |
917 | if (!intf) { | |
918 | of_node_put(ep_node); | |
919 | continue; | |
920 | } | |
921 | ||
54011e26 | 922 | component_match_add(master_dev, matchptr, compare_of, intf); |
812070eb AT |
923 | |
924 | of_node_put(intf); | |
925 | of_node_put(ep_node); | |
926 | } | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
54011e26 AT |
931 | static int compare_name_mdp(struct device *dev, void *data) |
932 | { | |
933 | return (strstr(dev_name(dev), "mdp") != NULL); | |
934 | } | |
935 | ||
7d526fcf AT |
936 | static int add_display_components(struct device *dev, |
937 | struct component_match **matchptr) | |
938 | { | |
54011e26 AT |
939 | struct device *mdp_dev; |
940 | int ret; | |
941 | ||
942 | /* | |
943 | * MDP5 based devices don't have a flat hierarchy. There is a top level | |
944 | * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the | |
945 | * children devices, find the MDP5 node, and then add the interfaces | |
946 | * to our components list. | |
947 | */ | |
948 | if (of_device_is_compatible(dev->of_node, "qcom,mdss")) { | |
949 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); | |
950 | if (ret) { | |
951 | dev_err(dev, "failed to populate children devices\n"); | |
952 | return ret; | |
953 | } | |
954 | ||
955 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); | |
956 | if (!mdp_dev) { | |
957 | dev_err(dev, "failed to find MDSS MDP node\n"); | |
958 | of_platform_depopulate(dev); | |
959 | return -ENODEV; | |
960 | } | |
961 | ||
962 | put_device(mdp_dev); | |
963 | ||
964 | /* add the MDP component itself */ | |
965 | component_match_add(dev, matchptr, compare_of, | |
966 | mdp_dev->of_node); | |
967 | } else { | |
968 | /* MDP4 */ | |
969 | mdp_dev = dev; | |
970 | } | |
971 | ||
972 | ret = add_components_mdp(mdp_dev, matchptr); | |
973 | if (ret) | |
974 | of_platform_depopulate(dev); | |
975 | ||
976 | return ret; | |
7d526fcf AT |
977 | } |
978 | ||
dc3ea265 AT |
979 | /* |
980 | * We don't know what's the best binding to link the gpu with the drm device. | |
981 | * Fow now, we just hunt for all the possible gpus that we support, and add them | |
982 | * as components. | |
983 | */ | |
984 | static const struct of_device_id msm_gpu_match[] = { | |
985 | { .compatible = "qcom,adreno-3xx" }, | |
986 | { .compatible = "qcom,kgsl-3d0" }, | |
987 | { }, | |
988 | }; | |
989 | ||
7d526fcf AT |
990 | static int add_gpu_components(struct device *dev, |
991 | struct component_match **matchptr) | |
992 | { | |
dc3ea265 AT |
993 | struct device_node *np; |
994 | ||
995 | np = of_find_matching_node(NULL, msm_gpu_match); | |
996 | if (!np) | |
997 | return 0; | |
998 | ||
999 | component_match_add(dev, matchptr, compare_of, np); | |
1000 | ||
1001 | of_node_put(np); | |
1002 | ||
1003 | return 0; | |
7d526fcf AT |
1004 | } |
1005 | ||
84448288 RK |
1006 | static int msm_drm_bind(struct device *dev) |
1007 | { | |
2b669875 | 1008 | return msm_drm_init(dev, &msm_driver); |
84448288 RK |
1009 | } |
1010 | ||
1011 | static void msm_drm_unbind(struct device *dev) | |
1012 | { | |
2b669875 | 1013 | msm_drm_uninit(dev); |
84448288 RK |
1014 | } |
1015 | ||
1016 | static const struct component_master_ops msm_drm_ops = { | |
1017 | .bind = msm_drm_bind, | |
1018 | .unbind = msm_drm_unbind, | |
1019 | }; | |
1020 | ||
1021 | /* | |
1022 | * Platform driver: | |
1023 | */ | |
060530f1 | 1024 | |
84448288 | 1025 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1026 | { |
84448288 | 1027 | struct component_match *match = NULL; |
7d526fcf AT |
1028 | int ret; |
1029 | ||
1030 | ret = add_display_components(&pdev->dev, &match); | |
1031 | if (ret) | |
1032 | return ret; | |
e9fbdaf2 | 1033 | |
7d526fcf AT |
1034 | ret = add_gpu_components(&pdev->dev, &match); |
1035 | if (ret) | |
1036 | return ret; | |
060530f1 | 1037 | |
871d812a | 1038 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 1039 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1040 | } |
1041 | ||
1042 | static int msm_pdev_remove(struct platform_device *pdev) | |
1043 | { | |
060530f1 | 1044 | component_master_del(&pdev->dev, &msm_drm_ops); |
54011e26 | 1045 | of_platform_depopulate(&pdev->dev); |
c8afe684 RC |
1046 | |
1047 | return 0; | |
1048 | } | |
1049 | ||
06c0dd96 | 1050 | static const struct of_device_id dt_match[] = { |
96a611b5 AT |
1051 | { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */ |
1052 | { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */ | |
06c0dd96 RC |
1053 | {} |
1054 | }; | |
1055 | MODULE_DEVICE_TABLE(of, dt_match); | |
1056 | ||
c8afe684 RC |
1057 | static struct platform_driver msm_platform_driver = { |
1058 | .probe = msm_pdev_probe, | |
1059 | .remove = msm_pdev_remove, | |
1060 | .driver = { | |
c8afe684 | 1061 | .name = "msm", |
06c0dd96 | 1062 | .of_match_table = dt_match, |
c8afe684 RC |
1063 | .pm = &msm_pm_ops, |
1064 | }, | |
c8afe684 RC |
1065 | }; |
1066 | ||
1067 | static int __init msm_drm_register(void) | |
1068 | { | |
1069 | DBG("init"); | |
1dd0a0b1 | 1070 | msm_mdp_register(); |
d5af49c9 | 1071 | msm_dsi_register(); |
00453981 | 1072 | msm_edp_register(); |
fcda50c8 | 1073 | msm_hdmi_register(); |
bfd28b13 | 1074 | adreno_register(); |
c8afe684 RC |
1075 | return platform_driver_register(&msm_platform_driver); |
1076 | } | |
1077 | ||
1078 | static void __exit msm_drm_unregister(void) | |
1079 | { | |
1080 | DBG("fini"); | |
1081 | platform_driver_unregister(&msm_platform_driver); | |
fcda50c8 | 1082 | msm_hdmi_unregister(); |
bfd28b13 | 1083 | adreno_unregister(); |
00453981 | 1084 | msm_edp_unregister(); |
d5af49c9 | 1085 | msm_dsi_unregister(); |
1dd0a0b1 | 1086 | msm_mdp_unregister(); |
c8afe684 RC |
1087 | } |
1088 | ||
1089 | module_init(msm_drm_register); | |
1090 | module_exit(msm_drm_unregister); | |
1091 | ||
1092 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1093 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1094 | MODULE_LICENSE("GPL"); |