[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / copy / nvc0.c

/*
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <linux/firmware.h>
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_util.h"
#include <core/ramht.h>
#include "fuc/nvc0.fuc.h"

struct nvc0_copy_engine {
	struct nouveau_exec_engine base;
	u32 irq;
	u32 pmc;
	u32 fuc;
	u32 ctx;
};

struct nvc0_copy_chan {
	struct nouveau_gpuobj *mem;
	struct nouveau_vma vma;
};

static int
nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
{
	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
	struct nvc0_copy_chan *cctx;
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj *ramin = chan->ramin;
	int ret;

	cctx = chan->engctx[engine] = kzalloc(sizeof(*cctx), GFP_KERNEL);
	if (!cctx)
		return -ENOMEM;

	ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
				 NVOBJ_FLAG_ZERO_ALLOC, &cctx->mem);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_map_vm(cctx->mem, chan->vm, NV_MEM_ACCESS_RW,
				   &cctx->vma);
	if (ret)
		return ret;

	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(cctx->vma.offset));
	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(cctx->vma.offset));
	nvimem_flush(dev);
	return 0;
}

static int
nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
		     u32 handle, u16 class)
{
	return 0;
}

static void
nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
{
	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
	struct nvc0_copy_chan *cctx = chan->engctx[engine];
	struct drm_device *dev = chan->dev;
	u32 inst;

	inst  = (chan->ramin->addr >> 12);
	inst |= 0x40000000;

	/* disable fifo access */
	nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
	/* mark channel as unloaded if it's currently active */
	if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
		nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
	/* mark next channel as invalid if it's about to be loaded */
	if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
		nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
	/* restore fifo access */
	nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);

	nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
	nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);

	nouveau_gpuobj_unmap(&cctx->vma);
	nouveau_gpuobj_ref(NULL, &cctx->mem);

	kfree(cctx);
	chan->engctx[engine] = NULL;
}

static int
nvc0_copy_init(struct drm_device *dev, int engine)
{
	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
	int i;

	nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
	nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
	nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);

	nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
	for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
		nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);

	nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
	for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
		if ((i & 0x3f) == 0)
			nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
		nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
	}

	nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
	nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
	nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
	nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
	return 0;
}

static int
nvc0_copy_fini(struct drm_device *dev, int engine, bool suspend)
{
	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);

	nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);

	/* trigger fuc context unload */
	nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
	nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
	nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
	nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);

	nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
	return 0;
}

static struct nouveau_enum nvc0_copy_isr_error_name[] = {
	{ 0x0001, "ILLEGAL_MTHD" },
	{ 0x0002, "INVALID_ENUM" },
	{ 0x0003, "INVALID_BITFIELD" },
	{}
};

static void
nvc0_copy_isr(struct drm_device *dev, int engine)
{
	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
	u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
	u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
	u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
	u32 chid = nvc0_graph_isr_chid(dev, inst);
	u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
	u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
	u32 mthd = (addr & 0x07ff) << 2;
	u32 subc = (addr & 0x3800) >> 11;
	u32 data = nv_rd32(dev, pcopy->fuc + 0x044);

	if (stat & 0x00000040) {
		NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
		nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
		printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
			chid, inst, subc, mthd, data);
		nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
		stat &= ~0x00000040;
	}

	if (stat) {
		NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
		nv_wr32(dev, pcopy->fuc + 0x004, stat);
	}
}

static void
nvc0_copy_isr_0(struct drm_device *dev)
{
	nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
}

static void
nvc0_copy_isr_1(struct drm_device *dev)
{
	nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
}

static void
nvc0_copy_destroy(struct drm_device *dev, int engine)
{
	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);

	nouveau_irq_unregister(dev, pcopy->irq);

	if (engine == NVOBJ_ENGINE_COPY0)
		NVOBJ_ENGINE_DEL(dev, COPY0);
	else
		NVOBJ_ENGINE_DEL(dev, COPY1);
	kfree(pcopy);
}

int
nvc0_copy_create(struct drm_device *dev, int engine)
{
	struct nvc0_copy_engine *pcopy;

	pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
	if (!pcopy)
		return -ENOMEM;

	pcopy->base.destroy = nvc0_copy_destroy;
	pcopy->base.init = nvc0_copy_init;
	pcopy->base.fini = nvc0_copy_fini;
	pcopy->base.context_new = nvc0_copy_context_new;
	pcopy->base.context_del = nvc0_copy_context_del;
	pcopy->base.object_new = nvc0_copy_object_new;

	if (engine == 0) {
		pcopy->irq = 5;
		pcopy->pmc = 0x00000040;
		pcopy->fuc = 0x104000;
		pcopy->ctx = 0x0230;
		nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
		NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
		NVOBJ_CLASS(dev, 0x90b5, COPY0);
	} else {
		pcopy->irq = 6;
		pcopy->pmc = 0x00000080;
		pcopy->fuc = 0x105000;
		pcopy->ctx = 0x0240;
		nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
		NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
		NVOBJ_CLASS(dev, 0x90b8, COPY1);
	}

	return 0;
}
Commit	Line	Data
d5a27370 BS	1	/*
	2	* Copyright 2011 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <linux/firmware.h>
	26	#include "drmP.h"
	27	#include "nouveau_drv.h"
	28	#include "nouveau_util.h"
02a841d4 BS	29	#include <core/ramht.h>
02a841d4 BS	30	#include "fuc/nvc0.fuc.h"
d5a27370 BS	31
	32	struct nvc0_copy_engine {
	33	struct nouveau_exec_engine base;
	34	u32 irq;
	35	u32 pmc;
	36	u32 fuc;
	37	u32 ctx;
	38	};
	39
73a60c0d BS	40	struct nvc0_copy_chan {
	41	struct nouveau_gpuobj *mem;
	42	struct nouveau_vma vma;
	43	};
	44
d5a27370 BS	45	static int
	46	nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
	47	{
	48	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
73a60c0d	49	struct nvc0_copy_chan *cctx;
d5a27370	50	struct drm_device *dev = chan->dev;
d5a27370	51	struct nouveau_gpuobj *ramin = chan->ramin;
d5a27370 BS	52	int ret;
d5a27370 BS	53
73a60c0d BS	54	cctx = chan->engctx[engine] = kzalloc(sizeof(*cctx), GFP_KERNEL);
	55	if (!cctx)
	56	return -ENOMEM;
	57
	58	ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
	59	NVOBJ_FLAG_ZERO_ALLOC, &cctx->mem);
d5a27370 BS	60	if (ret)
	61	return ret;
	62
3863c9bc	63	ret = nouveau_gpuobj_map_vm(cctx->mem, chan->vm, NV_MEM_ACCESS_RW,
73a60c0d BS	64	&cctx->vma);
	65	if (ret)
	66	return ret;
d5a27370	67
73a60c0d BS	68	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(cctx->vma.offset));
73a60c0d BS	69	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(cctx->vma.offset));
3863c9bc	70	nvimem_flush(dev);
d5a27370 BS	71	return 0;
	72	}
	73
	74	static int
	75	nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
	76	u32 handle, u16 class)
	77	{
	78	return 0;
	79	}
	80
	81	static void
	82	nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
	83	{
	84	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
73a60c0d	85	struct nvc0_copy_chan *cctx = chan->engctx[engine];
d5a27370 BS	86	struct drm_device *dev = chan->dev;
	87	u32 inst;
	88
3863c9bc	89	inst = (chan->ramin->addr >> 12);
d5a27370 BS	90	inst \|= 0x40000000;
	91
	92	/* disable fifo access */
	93	nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
	94	/* mark channel as unloaded if it's currently active */
	95	if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
	96	nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
	97	/* mark next channel as invalid if it's about to be loaded */
	98	if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
	99	nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
	100	/* restore fifo access */
	101	nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
	102
	103	nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
	104	nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
d5a27370	105
73a60c0d BS	106	nouveau_gpuobj_unmap(&cctx->vma);
	107	nouveau_gpuobj_ref(NULL, &cctx->mem);
	108
	109	kfree(cctx);
	110	chan->engctx[engine] = NULL;
d5a27370 BS	111	}
	112
	113	static int
	114	nvc0_copy_init(struct drm_device *dev, int engine)
	115	{
	116	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
	117	int i;
	118
	119	nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
	120	nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
	121	nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
	122
	123	nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
	124	for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
	125	nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
	126
	127	nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
	128	for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
	129	if ((i & 0x3f) == 0)
	130	nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
	131	nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
	132	}
	133
	134	nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
	135	nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
	136	nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
	137	nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
	138	return 0;
	139	}
	140
	141	static int
6c320fef	142	nvc0_copy_fini(struct drm_device *dev, int engine, bool suspend)
d5a27370 BS	143	{
	144	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
	145
	146	nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
	147
	148	/* trigger fuc context unload */
	149	nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
	150	nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
	151	nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
	152	nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
	153
	154	nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
	155	return 0;
	156	}
	157
	158	static struct nouveau_enum nvc0_copy_isr_error_name[] = {
	159	{ 0x0001, "ILLEGAL_MTHD" },
	160	{ 0x0002, "INVALID_ENUM" },
	161	{ 0x0003, "INVALID_BITFIELD" },
	162	{}
	163	};
	164
	165	static void
	166	nvc0_copy_isr(struct drm_device *dev, int engine)
	167	{
	168	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
	169	u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
	170	u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
	171	u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
	172	u32 chid = nvc0_graph_isr_chid(dev, inst);
	173	u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
	174	u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
	175	u32 mthd = (addr & 0x07ff) << 2;
	176	u32 subc = (addr & 0x3800) >> 11;
	177	u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
	178
	179	if (stat & 0x00000040) {
	180	NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
	181	nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
	182	printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
	183	chid, inst, subc, mthd, data);
	184	nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
	185	stat &= ~0x00000040;
	186	}
	187
	188	if (stat) {
	189	NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
	190	nv_wr32(dev, pcopy->fuc + 0x004, stat);
	191	}
	192	}
	193
	194	static void
	195	nvc0_copy_isr_0(struct drm_device *dev)
	196	{
	197	nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
	198	}
	199
	200	static void
	201	nvc0_copy_isr_1(struct drm_device *dev)
	202	{
	203	nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
	204	}
	205
	206	static void
207	nvc0_copy_destroy(struct drm_device *dev, int engine)
208	{
209	struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
210
211	nouveau_irq_unregister(dev, pcopy->irq);
212
213	if (engine == NVOBJ_ENGINE_COPY0)
214	NVOBJ_ENGINE_DEL(dev, COPY0);
215	else
216	NVOBJ_ENGINE_DEL(dev, COPY1);
217	kfree(pcopy);
218	}
219
220	int
221	nvc0_copy_create(struct drm_device *dev, int engine)
222	{
223	struct nvc0_copy_engine *pcopy;
224
225	pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
226	if (!pcopy)
227	return -ENOMEM;
228
229	pcopy->base.destroy = nvc0_copy_destroy;
230	pcopy->base.init = nvc0_copy_init;
231	pcopy->base.fini = nvc0_copy_fini;
232	pcopy->base.context_new = nvc0_copy_context_new;
233	pcopy->base.context_del = nvc0_copy_context_del;
234	pcopy->base.object_new = nvc0_copy_object_new;
235
236	if (engine == 0) {
237	pcopy->irq = 5;
238	pcopy->pmc = 0x00000040;
239	pcopy->fuc = 0x104000;
240	pcopy->ctx = 0x0230;
241	nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
242	NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
243	NVOBJ_CLASS(dev, 0x90b5, COPY0);
244	} else {
245	pcopy->irq = 6;
246	pcopy->pmc = 0x00000080;
247	pcopy->fuc = 0x105000;
248	pcopy->ctx = 0x0240;
249	nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
250	NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
251	NVOBJ_CLASS(dev, 0x90b8, COPY1);
252	}
253
254	return 0;
255	}