drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / crypt / nv98.c
CommitLineData
8f27c543 1/*
ebb945a9 2 * Copyright 2012 Red Hat Inc.
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3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
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25#include <core/os.h>
26#include <core/enum.h>
27#include <core/class.h>
28#include <core/engctx.h>
b3550969 29
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30#include <subdev/timer.h>
31#include <subdev/fb.h>
32
33#include <engine/crypt.h>
8f27c543 34
02a841d4 35#include "fuc/nv98.fuc.h"
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36
37struct nv98_crypt_priv {
ebb945a9 38 struct nouveau_crypt base;
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39};
40
b3550969 41struct nv98_crypt_chan {
ebb945a9 42 struct nouveau_crypt_chan base;
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43};
44
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45/*******************************************************************************
46 * Crypt object classes
47 ******************************************************************************/
b3550969 48
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49static struct nouveau_oclass
50nv98_crypt_sclass[] = {
51 { 0x88b4, &nouveau_object_ofuncs },
52 {},
53};
b3550969 54
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55/*******************************************************************************
56 * PCRYPT context
57 ******************************************************************************/
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58
59static int
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60nv98_crypt_context_ctor(struct nouveau_object *parent,
61 struct nouveau_object *engine,
62 struct nouveau_oclass *oclass, void *data, u32 size,
63 struct nouveau_object **pobject)
8f27c543 64{
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65 struct nv98_crypt_chan *priv;
66 int ret;
8f27c543 67
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68 ret = nouveau_crypt_context_create(parent, engine, oclass, NULL, 256,
69 256, NVOBJ_FLAG_ZERO_ALLOC, &priv);
70 *pobject = nv_object(priv);
71 if (ret)
72 return ret;
b3550969 73
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74 return 0;
75}
76
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77static struct nouveau_oclass
78nv98_crypt_cclass = {
79 .handle = NV_ENGCTX(CRYPT, 0x98),
80 .ofuncs = &(struct nouveau_ofuncs) {
81 .ctor = nv98_crypt_context_ctor,
82 .dtor = _nouveau_crypt_context_dtor,
83 .init = _nouveau_crypt_context_init,
84 .fini = _nouveau_crypt_context_fini,
85 .rd32 = _nouveau_crypt_context_rd32,
86 .wr32 = _nouveau_crypt_context_wr32,
87 },
88};
b3550969 89
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90/*******************************************************************************
91 * PCRYPT engine/subdev functions
92 ******************************************************************************/
8f27c543 93
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94static struct nouveau_enum nv98_crypt_isr_error_name[] = {
95 { 0x0000, "ILLEGAL_MTHD" },
96 { 0x0001, "INVALID_BITFIELD" },
97 { 0x0002, "INVALID_ENUM" },
98 { 0x0003, "QUERY" },
99 {}
100};
101
102static void
ebb945a9 103nv98_crypt_intr(struct nouveau_subdev *subdev)
b3550969 104{
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105 struct nv98_crypt_priv *priv = (void *)subdev;
106 u32 disp = nv_rd32(priv, 0x08701c);
107 u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
108 u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
109 u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff;
110 u32 addr = nv_rd32(priv, 0x087040) >> 16;
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111 u32 mthd = (addr & 0x07ff) << 2;
112 u32 subc = (addr & 0x3800) >> 11;
ebb945a9 113 u32 data = nv_rd32(priv, 0x087044);
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114
115 if (stat & 0x00000040) {
ebb945a9 116 nv_error(priv, "DISPATCH_ERROR [");
b3550969 117 nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
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118 printk("] ch 0x%08x subc %d mthd 0x%04x data 0x%08x\n",
119 inst, subc, mthd, data);
120 nv_wr32(priv, 0x087004, 0x00000040);
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121 stat &= ~0x00000040;
122 }
123
124 if (stat) {
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125 nv_error(priv, "unhandled intr 0x%08x\n", stat);
126 nv_wr32(priv, 0x087004, stat);
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127 }
128
ebb945a9 129 nv50_fb_trap(nouveau_fb(priv), 1);
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130}
131
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132static int
133nv98_crypt_tlb_flush(struct nouveau_engine *engine)
8f27c543 134{
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135 nv50_vm_flush_engine(&engine->base, 0x0a);
136 return 0;
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137}
138
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139static int
140nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
141 struct nouveau_oclass *oclass, void *data, u32 size,
142 struct nouveau_object **pobject)
8f27c543 143{
b3550969 144 struct nv98_crypt_priv *priv;
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145 int ret;
146
147 ret = nouveau_crypt_create(parent, engine, oclass, &priv);
148 *pobject = nv_object(priv);
149 if (ret)
150 return ret;
151
152 nv_subdev(priv)->unit = 0x00004000;
153 nv_subdev(priv)->intr = nv98_crypt_intr;
154 nv_engine(priv)->cclass = &nv98_crypt_cclass;
155 nv_engine(priv)->sclass = nv98_crypt_sclass;
156 nv_engine(priv)->tlb_flush = nv98_crypt_tlb_flush;
157 return 0;
158}
159
160static int
161nv98_crypt_init(struct nouveau_object *object)
162{
163 struct nv98_crypt_priv *priv = (void *)object;
164 int ret, i;
165
166 ret = nouveau_crypt_init(&priv->base);
167 if (ret)
168 return ret;
8f27c543 169
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170 /* wait for exit interrupt to signal */
171 nv_wait(priv, 0x087008, 0x00000010, 0x00000010);
172 nv_wr32(priv, 0x087004, 0x00000010);
8f27c543 173
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174 /* upload microcode code and data segments */
175 nv_wr32(priv, 0x087ff8, 0x00100000);
176 for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_code); i++)
177 nv_wr32(priv, 0x087ff4, nv98_pcrypt_code[i]);
b3550969 178
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179 nv_wr32(priv, 0x087ff8, 0x00000000);
180 for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_data); i++)
181 nv_wr32(priv, 0x087ff4, nv98_pcrypt_data[i]);
8f27c543 182
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183 /* start it running */
184 nv_wr32(priv, 0x08710c, 0x00000000);
185 nv_wr32(priv, 0x087104, 0x00000000); /* ENTRY */
186 nv_wr32(priv, 0x087100, 0x00000002); /* TRIGGER */
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187 return 0;
188}
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189
190struct nouveau_oclass
191nv98_crypt_oclass = {
192 .handle = NV_ENGINE(CRYPT, 0x98),
193 .ofuncs = &(struct nouveau_ofuncs) {
194 .ctor = nv98_crypt_ctor,
195 .dtor = _nouveau_crypt_dtor,
196 .init = nv98_crypt_init,
197 .fini = _nouveau_crypt_fini,
198 },
199};
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