drm/nv50/disp: allow PCI_US pushbuf binding
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / nvd0.c
CommitLineData
ebb945a9
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/bar.h>
26
27#include <engine/software.h>
28#include <engine/disp.h>
29
30struct nvd0_disp_priv {
31 struct nouveau_disp base;
32};
33
34static struct nouveau_oclass
35nvd0_disp_sclass[] = {
36 {},
37};
38
39static void
40nvd0_disp_intr_vblank(struct nvd0_disp_priv *priv, int crtc)
41{
42 struct nouveau_bar *bar = nouveau_bar(priv);
43 struct nouveau_disp *disp = &priv->base;
44 struct nouveau_software_chan *chan, *temp;
45 unsigned long flags;
46
47 spin_lock_irqsave(&disp->vblank.lock, flags);
48 list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
49 if (chan->vblank.crtc != crtc)
50 continue;
51
52 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
53 bar->flush(bar);
54 nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset));
55 nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset));
56 nv_wr32(priv, 0x060014, chan->vblank.value);
57
58 list_del(&chan->vblank.head);
59 if (disp->vblank.put)
60 disp->vblank.put(disp->vblank.data, crtc);
61 }
62 spin_unlock_irqrestore(&disp->vblank.lock, flags);
63
64 if (disp->vblank.notify)
65 disp->vblank.notify(disp->vblank.data, crtc);
66}
67
68static void
69nvd0_disp_intr(struct nouveau_subdev *subdev)
70{
71 struct nvd0_disp_priv *priv = (void *)subdev;
72 u32 intr = nv_rd32(priv, 0x610088);
73 int i;
74
75 for (i = 0; i < 4; i++) {
76 u32 mask = 0x01000000 << i;
77 if (mask & intr) {
78 u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
79 if (stat & 0x00000001)
80 nvd0_disp_intr_vblank(priv, i);
81 nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
82 nv_rd32(priv, 0x6100c0 + (i * 0x800));
83 }
84 }
85}
86
87static int
88nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
89 struct nouveau_oclass *oclass, void *data, u32 size,
90 struct nouveau_object **pobject)
91{
92 struct nvd0_disp_priv *priv;
93 int ret;
94
95 ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
96 "display", &priv);
97 *pobject = nv_object(priv);
98 if (ret)
99 return ret;
100
101 nv_engine(priv)->sclass = nvd0_disp_sclass;
102 nv_subdev(priv)->intr = nvd0_disp_intr;
103
104 INIT_LIST_HEAD(&priv->base.vblank.list);
105 spin_lock_init(&priv->base.vblank.lock);
106 return 0;
107}
108
109struct nouveau_oclass
110nvd0_disp_oclass = {
111 .handle = NV_ENGINE(DISP, 0xd0),
112 .ofuncs = &(struct nouveau_ofuncs) {
113 .ctor = nvd0_disp_ctor,
114 .dtor = _nouveau_disp_dtor,
115 .init = _nouveau_disp_init,
116 .fini = _nouveau_disp_fini,
117 },
118};
This page took 0.058438 seconds and 5 git commands to generate.