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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <core/os.h> | |
26 | #include <core/class.h> | |
27 | ||
28 | #include <subdev/bios.h> | |
29 | #include <subdev/bios/dcb.h> | |
74b66850 | 30 | #include <subdev/timer.h> |
6c5a0424 BS |
31 | |
32 | #include "nv50.h" | |
33 | ||
74b66850 BS |
34 | int |
35 | nv50_sor_power(struct nv50_disp_priv *priv, int or, u32 data) | |
36 | { | |
37 | const u32 stat = data & NV50_DISP_SOR_PWR_STATE; | |
38 | const u32 soff = (or * 0x800); | |
39 | nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); | |
40 | nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); | |
41 | nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); | |
42 | nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000); | |
43 | return 0; | |
44 | } | |
45 | ||
6c5a0424 BS |
46 | int |
47 | nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) | |
48 | { | |
49 | struct nv50_disp_priv *priv = (void *)object->engine; | |
ebd6acbb | 50 | const u8 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12; |
6c5a0424 | 51 | const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3; |
ebd6acbb | 52 | const u8 link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2; |
6c5a0424 | 53 | const u8 or = (mthd & NV50_DISP_SOR_MTHD_OR); |
ebd6acbb BS |
54 | const u16 mask = (0x0100 << head) | (0x0040 << link) | (0x0001 << or); |
55 | struct nvkm_output *outp = NULL, *temp; | |
6c5a0424 BS |
56 | u32 data; |
57 | int ret = -EINVAL; | |
58 | ||
59 | if (size < sizeof(u32)) | |
60 | return -EINVAL; | |
75f8693f | 61 | data = *(u32 *)args; |
6c5a0424 | 62 | |
ebd6acbb BS |
63 | list_for_each_entry(temp, &priv->base.outp, head) { |
64 | if ((temp->info.hasht & 0xff) == type && | |
65 | (temp->info.hashm & mask) == mask) { | |
66 | outp = temp; | |
67 | break; | |
68 | } | |
69 | } | |
6c5a0424 | 70 | |
6c5a0424 | 71 | switch (mthd & ~0x3f) { |
74b66850 BS |
72 | case NV50_DISP_SOR_PWR: |
73 | ret = priv->sor.power(priv, or, data); | |
74 | break; | |
0a9e2b95 BS |
75 | case NVA3_DISP_SOR_HDA_ELD: |
76 | ret = priv->sor.hda_eld(priv, or, args, size); | |
77 | break; | |
1c30cd09 BS |
78 | case NV84_DISP_SOR_HDMI_PWR: |
79 | ret = priv->sor.hdmi(priv, head, or, data); | |
80 | break; | |
4a230fa6 BS |
81 | case NV50_DISP_SOR_LVDS_SCRIPT: |
82 | priv->sor.lvdsconf = data & NV50_DISP_SOR_LVDS_SCRIPT_ID; | |
83 | ret = 0; | |
84 | break; | |
ebd6acbb BS |
85 | case NV94_DISP_SOR_DP_PWR: |
86 | if (outp) { | |
87 | struct nvkm_output_dp *outpdp = (void *)outp; | |
88 | switch (data) { | |
89 | case NV94_DISP_SOR_DP_PWR_STATE_OFF: | |
7fac4933 | 90 | nouveau_event_put(outpdp->irq); |
ebd6acbb BS |
91 | ((struct nvkm_output_dp_impl *)nv_oclass(outp)) |
92 | ->lnk_pwr(outpdp, 0); | |
93 | atomic_set(&outpdp->lt.done, 0); | |
94 | break; | |
95 | case NV94_DISP_SOR_DP_PWR_STATE_ON: | |
96 | nvkm_output_dp_train(&outpdp->base, 0, true); | |
97 | break; | |
98 | default: | |
99 | return -EINVAL; | |
100 | } | |
101 | } | |
102 | break; | |
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103 | default: |
104 | BUG_ON(1); | |
105 | } | |
106 | ||
107 | return ret; | |
108 | } |