[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / fifo / nv17.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/os.h>
#include <core/class.h>
#include <core/engctx.h>
#include <core/ramht.h>

#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
#include <subdev/fb.h>

#include <engine/fifo.h>

#include "nv04.h"

static struct ramfc_desc
nv17_ramfc[] = {
	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
	{ 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
	{ 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
	{ 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
	{}
};

/*******************************************************************************
 * FIFO channel objects
 ******************************************************************************/

static int
nv17_fifo_chan_ctor(struct nouveau_object *parent,
		    struct nouveau_object *engine,
		    struct nouveau_oclass *oclass, void *data, u32 size,
		    struct nouveau_object **pobject)
{
	struct nv04_fifo_priv *priv = (void *)engine;
	struct nv04_fifo_chan *chan;
	struct nv_channel_dma_class *args = data;
	int ret;

	if (size < sizeof(*args))
		return -EINVAL;

	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
					  0x10000, args->pushbuf,
					  (1 << NVDEV_ENGINE_DMAOBJ) |
					  (1 << NVDEV_ENGINE_SW) |
					  (1 << NVDEV_ENGINE_GR) |
					  (1 << NVDEV_ENGINE_MPEG), /* NV31- */
					  &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
	chan->ramfc = chan->base.chid * 64;

	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
	nv_wo32(priv->ramfc, chan->ramfc + 0x14,
			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
#ifdef __BIG_ENDIAN
			     NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
			     NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
	return 0;
}

static struct nouveau_ofuncs
nv17_fifo_ofuncs = {
	.ctor = nv17_fifo_chan_ctor,
	.dtor = nv04_fifo_chan_dtor,
	.init = nv04_fifo_chan_init,
	.fini = nv04_fifo_chan_fini,
	.rd32 = _nouveau_fifo_channel_rd32,
	.wr32 = _nouveau_fifo_channel_wr32,
};

static struct nouveau_oclass
nv17_fifo_sclass[] = {
	{ 0x006e, &nv17_fifo_ofuncs },
	{}
};

/*******************************************************************************
 * FIFO context - basically just the instmem reserved for the channel
 ******************************************************************************/

static struct nouveau_oclass
nv17_fifo_cclass = {
	.handle = NV_ENGCTX(FIFO, 0x17),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_fifo_context_ctor,
		.dtor = _nouveau_fifo_context_dtor,
		.init = _nouveau_fifo_context_init,
		.fini = _nouveau_fifo_context_fini,
		.rd32 = _nouveau_fifo_context_rd32,
		.wr32 = _nouveau_fifo_context_wr32,
	},
};

/*******************************************************************************
 * PFIFO engine
 ******************************************************************************/

static int
nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv04_instmem_priv *imem = nv04_instmem(parent);
	struct nv04_fifo_priv *priv;
	int ret;

	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nouveau_ramht_ref(imem->ramht, &priv->ramht);
	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);

	nv_subdev(priv)->unit = 0x00000100;
	nv_subdev(priv)->intr = nv04_fifo_intr;
	nv_engine(priv)->cclass = &nv17_fifo_cclass;
	nv_engine(priv)->sclass = nv17_fifo_sclass;
	priv->base.pause = nv04_fifo_pause;
	priv->base.start = nv04_fifo_start;
	priv->ramfc_desc = nv17_ramfc;
	return 0;
}

static int
nv17_fifo_init(struct nouveau_object *object)
{
	struct nv04_fifo_priv *priv = (void *)object;
	int ret;

	ret = nouveau_fifo_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
	nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);

	nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
				       ((priv->ramht->bits - 9) << 16) |
				        (priv->ramht->base.addr >> 8));
	nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
	nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000);

	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);

	nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
	nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);

	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
	return 0;
}

struct nouveau_oclass
nv17_fifo_oclass = {
	.handle = NV_ENGINE(FIFO, 0x17),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv17_fifo_ctor,
		.dtor = nv04_fifo_dtor,
		.init = nv17_fifo_init,
		.fini = _nouveau_fifo_fini,
	},
};
Commit	Line	Data
c420b2dc	1	/*
ebb945a9	2	* Copyright 2012 Red Hat Inc.
c420b2dc	3	*
ebb945a9 BS	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
c420b2dc	10	*
ebb945a9 BS	11	* The above copyright notice and this permission notice shall be included in
ebb945a9 BS	12	* all copies or substantial portions of the Software.
c420b2dc	13	*
ebb945a9 BS	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
c420b2dc	21	*
ebb945a9	22	* Authors: Ben Skeggs
c420b2dc BS	23	*/
c420b2dc BS	24
ebb945a9 BS	25	#include <core/os.h>
	26	#include <core/class.h>
	27	#include <core/engctx.h>
02a841d4	28	#include <core/ramht.h>
c420b2dc	29
ebb945a9 BS	30	#include <subdev/instmem.h>
	31	#include <subdev/instmem/nv04.h>
	32	#include <subdev/fb.h>
	33
	34	#include <engine/fifo.h>
	35
	36	#include "nv04.h"
	37
	38	static struct ramfc_desc
	39	nv17_ramfc[] = {
c420b2dc BS	40	{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
	41	{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
	42	{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
	43	{ 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
	44	{ 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
	45	{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
	46	{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
	47	{ 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
	48	{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
	49	{ 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
	50	{ 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
	51	{ 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
	52	{ 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
	53	{ 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
	54	{}
	55	};
	56
ebb945a9 BS	57	/*******************************************************************************
	58	* FIFO channel objects
	59	******************************************************************************/
c420b2dc BS	60
c420b2dc BS	61	static int
ebb945a9 BS	62	nv17_fifo_chan_ctor(struct nouveau_object *parent,
	63	struct nouveau_object *engine,
	64	struct nouveau_oclass oclass, void data, u32 size,
	65	struct nouveau_object **pobject)
c420b2dc	66	{
ebb945a9 BS	67	struct nv04_fifo_priv priv = (void )engine;
	68	struct nv04_fifo_chan *chan;
	69	struct nv_channel_dma_class *args = data;
c420b2dc BS	70	int ret;
c420b2dc BS	71
ebb945a9 BS	72	if (size < sizeof(*args))
	73	return -EINVAL;
	74
	75	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
	76	0x10000, args->pushbuf,
	77	(1 << NVDEV_ENGINE_DMAOBJ) \|
	78	(1 << NVDEV_ENGINE_SW) \|
	79	(1 << NVDEV_ENGINE_GR) \|
	80	(1 << NVDEV_ENGINE_MPEG), /* NV31- */
	81	&chan);
	82	*pobject = nv_object(chan);
	83	if (ret)
	84	return ret;
	85
	86	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
	87	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
	88	chan->ramfc = chan->base.chid * 64;
	89
	90	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
	91	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
	92	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
	93	nv_wo32(priv->ramfc, chan->ramfc + 0x14,
70ee6f1c BS	94	NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES \|
70ee6f1c BS	95	NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES \|
c420b2dc	96	#ifdef __BIG_ENDIAN
70ee6f1c	97	NV_PFIFO_CACHE1_BIG_ENDIAN \|
c420b2dc	98	#endif
70ee6f1c	99	NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
ebb945a9 BS	100	return 0;
ebb945a9 BS	101	}
c420b2dc	102
ebb945a9 BS	103	static struct nouveau_ofuncs
	104	nv17_fifo_ofuncs = {
	105	.ctor = nv17_fifo_chan_ctor,
	106	.dtor = nv04_fifo_chan_dtor,
	107	.init = nv04_fifo_chan_init,
	108	.fini = nv04_fifo_chan_fini,
	109	.rd32 = _nouveau_fifo_channel_rd32,
	110	.wr32 = _nouveau_fifo_channel_wr32,
	111	};
c420b2dc	112
ebb945a9 BS	113	static struct nouveau_oclass
	114	nv17_fifo_sclass[] = {
	115	{ 0x006e, &nv17_fifo_ofuncs },
	116	{}
	117	};
	118
	119	/*******************************************************************************
	120	* FIFO context - basically just the instmem reserved for the channel
	121	******************************************************************************/
	122
	123	static struct nouveau_oclass
	124	nv17_fifo_cclass = {
	125	.handle = NV_ENGCTX(FIFO, 0x17),
	126	.ofuncs = &(struct nouveau_ofuncs) {
	127	.ctor = nv04_fifo_context_ctor,
	128	.dtor = _nouveau_fifo_context_dtor,
	129	.init = _nouveau_fifo_context_init,
	130	.fini = _nouveau_fifo_context_fini,
	131	.rd32 = _nouveau_fifo_context_rd32,
	132	.wr32 = _nouveau_fifo_context_wr32,
	133	},
	134	};
	135
	136	/*******************************************************************************
	137	* PFIFO engine
	138	******************************************************************************/
c420b2dc BS	139
c420b2dc BS	140	static int
ebb945a9 BS	141	nv17_fifo_ctor(struct nouveau_object parent, struct nouveau_object engine,
	142	struct nouveau_oclass oclass, void data, u32 size,
	143	struct nouveau_object **pobject)
c420b2dc	144	{
ebb945a9 BS	145	struct nv04_instmem_priv *imem = nv04_instmem(parent);
	146	struct nv04_fifo_priv *priv;
	147	int ret;
c420b2dc	148
ebb945a9 BS	149	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
	150	*pobject = nv_object(priv);
	151	if (ret)
	152	return ret;
	153
	154	nouveau_ramht_ref(imem->ramht, &priv->ramht);
	155	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
	156	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
	157
	158	nv_subdev(priv)->unit = 0x00000100;
	159	nv_subdev(priv)->intr = nv04_fifo_intr;
	160	nv_engine(priv)->cclass = &nv17_fifo_cclass;
	161	nv_engine(priv)->sclass = nv17_fifo_sclass;
	162	priv->base.pause = nv04_fifo_pause;
	163	priv->base.start = nv04_fifo_start;
	164	priv->ramfc_desc = nv17_ramfc;
	165	return 0;
	166	}
c420b2dc	167
ebb945a9 BS	168	static int
	169	nv17_fifo_init(struct nouveau_object *object)
	170	{
	171	struct nv04_fifo_priv priv = (void )object;
	172	int ret;
c420b2dc	173
ebb945a9 BS	174	ret = nouveau_fifo_init(&priv->base);
	175	if (ret)
	176	return ret;
c420b2dc	177
ebb945a9 BS	178	nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
ebb945a9 BS	179	nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
c420b2dc	180
ebb945a9 BS	181	nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ \|
	182	((priv->ramht->bits - 9) << 16) \|
	183	(priv->ramht->base.addr >> 8));
	184	nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
	185	nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 \| 0x00010000);
c420b2dc	186
ebb945a9	187	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
c420b2dc	188
ebb945a9 BS	189	nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
ebb945a9 BS	190	nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
c420b2dc	191
ebb945a9 BS	192	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
	193	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
	194	nv_wr32(priv, NV03_PFIFO_CACHES, 1);
c420b2dc BS	195	return 0;
	196	}
	197
ebb945a9 BS	198	struct nouveau_oclass
	199	nv17_fifo_oclass = {
	200	.handle = NV_ENGINE(FIFO, 0x17),
	201	.ofuncs = &(struct nouveau_ofuncs) {
	202	.ctor = nv17_fifo_ctor,
	203	.dtor = nv04_fifo_dtor,
	204	.init = nv17_fifo_init,
	205	.fini = _nouveau_fifo_fini,
	206	},
	207	};