[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / nv20.c

#include <core/client.h>
#include <core/os.h>
#include <core/class.h>
#include <core/engctx.h>
#include <core/handle.h>
#include <core/enum.h>

#include <subdev/timer.h>
#include <subdev/fb.h>

#include <engine/graph.h>
#include <engine/fifo.h>

#include "nv20.h"
#include "regs.h"

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static struct nouveau_oclass
nv20_graph_sclass[] = {
	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv20_graph_context_ctor(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nv20_graph_chan *chan;
	int ret, i;

	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
					   0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
					   &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nouveau_fifo_chan(parent)->chid;

	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
	nv_wo32(chan, 0x033c, 0xffff0000);
	nv_wo32(chan, 0x03a0, 0x0fff0000);
	nv_wo32(chan, 0x03a4, 0x0fff0000);
	nv_wo32(chan, 0x047c, 0x00000101);
	nv_wo32(chan, 0x0490, 0x00000111);
	nv_wo32(chan, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nv_wo32(chan, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nv_wo32(chan, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nv_wo32(chan, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nv_wo32(chan, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nv_wo32(chan, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nv_wo32(chan, i, 0x07ff0000);
	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	nv_wo32(chan, 0x05fc, 0x00000001);
	nv_wo32(chan, 0x0604, 0x00004000);
	nv_wo32(chan, 0x0610, 0x00000001);
	nv_wo32(chan, 0x0618, 0x00040000);
	nv_wo32(chan, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nv_wo32(chan, (i + 0), 0x10700ff9);
		nv_wo32(chan, (i + 4), 0x0436086c);
		nv_wo32(chan, (i + 8), 0x000c001b);
	}
	nv_wo32(chan, 0x281c, 0x3f800000);
	nv_wo32(chan, 0x2830, 0x3f800000);
	nv_wo32(chan, 0x285c, 0x40000000);
	nv_wo32(chan, 0x2860, 0x3f800000);
	nv_wo32(chan, 0x2864, 0x3f000000);
	nv_wo32(chan, 0x286c, 0x40000000);
	nv_wo32(chan, 0x2870, 0x3f800000);
	nv_wo32(chan, 0x2878, 0xbf800000);
	nv_wo32(chan, 0x2880, 0xbf800000);
	nv_wo32(chan, 0x34a4, 0x000fe000);
	nv_wo32(chan, 0x3530, 0x000003f8);
	nv_wo32(chan, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nv_wo32(chan, i, 0x001c527c);
	return 0;
}

int
nv20_graph_context_init(struct nouveau_object *object)
{
	struct nv20_graph_priv *priv = (void *)object->engine;
	struct nv20_graph_chan *chan = (void *)object;
	int ret;

	ret = nouveau_graph_context_init(&chan->base);
	if (ret)
		return ret;

	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
	return 0;
}

int
nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
{
	struct nv20_graph_priv *priv = (void *)object->engine;
	struct nv20_graph_chan *chan = (void *)object;
	int chid = -1;

	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	if (nv_rd32(priv, 0x400144) & 0x00010000)
		chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
		nv_wr32(priv, 0x400788, 0x00000002);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
		nv_wr32(priv, 0x400144, 0x10000000);
		nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
	}
	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);

	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
	return nouveau_graph_context_fini(&chan->base, suspend);
}

static struct nouveau_oclass
nv20_graph_cclass = {
	.handle = NV_ENGCTX(GR, 0x20),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv20_graph_context_ctor,
		.dtor = _nouveau_graph_context_dtor,
		.init = nv20_graph_context_init,
		.fini = nv20_graph_context_fini,
		.rd32 = _nouveau_graph_context_rd32,
		.wr32 = _nouveau_graph_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
{
	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	struct nv20_graph_priv *priv = (void *)engine;
	unsigned long flags;

	pfifo->pause(pfifo, &flags);
	nv04_graph_idle(priv);

	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);

	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (nv_device(engine)->chipset != 0x34) {
		nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	pfifo->start(pfifo, &flags);
}

void
nv20_graph_intr(struct nouveau_subdev *subdev)
{
	struct nouveau_engine *engine = nv_engine(subdev);
	struct nouveau_object *engctx;
	struct nouveau_handle *handle;
	struct nv20_graph_priv *priv = (void *)subdev;
	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
	u32 show = stat;

	engctx = nouveau_engctx_get(engine, chid);
	if (stat & NV_PGRAPH_INTR_ERROR) {
		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
			handle = nouveau_handle_get_class(engctx, class);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~NV_PGRAPH_INTR_ERROR;
			nouveau_handle_put(handle);
		}
	}

	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nv_error(priv, "%s", "");
		nouveau_bitfield_print(nv10_graph_intr_name, show);
		pr_cont(" nsource:");
		nouveau_bitfield_print(nv04_graph_nsource, nsource);
		pr_cont(" nstatus:");
		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
		pr_cont("\n");
		nv_error(priv,
			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
			 chid, nouveau_client_name(engctx), subc, class, mthd,
			 data);
	}

	nouveau_engctx_put(engctx);
}

static int
nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv20_graph_priv *priv;
	int ret;

	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_graph_intr;
	nv_engine(priv)->cclass = &nv20_graph_cclass;
	nv_engine(priv)->sclass = nv20_graph_sclass;
	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
	return 0;
}

void
nv20_graph_dtor(struct nouveau_object *object)
{
	struct nv20_graph_priv *priv = (void *)object;
	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
	nouveau_graph_destroy(&priv->base);
}

int
nv20_graph_init(struct nouveau_object *object)
{
	struct nouveau_engine *engine = nv_engine(object);
	struct nv20_graph_priv *priv = (void *)engine;
	struct nouveau_fb *pfb = nouveau_fb(object);
	u32 tmp, vramsz;
	int ret, i;

	ret = nouveau_graph_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);

	if (nv_device(priv)->chipset == 0x20) {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	} else {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	}

	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nv_wr32(priv, 0x40009C           , 0x00000040);

	if (nv_device(priv)->chipset >= 0x25) {
		nv_wr32(priv, 0x400890, 0x00a8cfff);
		nv_wr32(priv, 0x400610, 0x304B1FB6);
		nv_wr32(priv, 0x400B80, 0x1cbd3883);
		nv_wr32(priv, 0x400B84, 0x44000000);
		nv_wr32(priv, 0x400098, 0x40000080);
		nv_wr32(priv, 0x400B88, 0x000000ff);

	} else {
		nv_wr32(priv, 0x400880, 0x0008c7df);
		nv_wr32(priv, 0x400094, 0x00000005);
		nv_wr32(priv, 0x400B80, 0x45eae20e);
		nv_wr32(priv, 0x400B84, 0x24000000);
		nv_wr32(priv, 0x400098, 0x00000040);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));

	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	nv_wr32(priv, 0x400820, 0);
	nv_wr32(priv, 0x400824, 0);
	nv_wr32(priv, 0x400864, vramsz - 1);
	nv_wr32(priv, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nv_wr32(priv, 0x400B20, 0x00000000);
	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);

	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

struct nouveau_oclass
nv20_graph_oclass = {
	.handle = NV_ENGINE(GR, 0x20),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv20_graph_ctor,
		.dtor = nv20_graph_dtor,
		.init = nv20_graph_init,
		.fini = _nouveau_graph_fini,
	},
};
Commit	Line	Data
93260d3c	1	#include <core/client.h>
ebb945a9 BS	2	#include <core/os.h>
	3	#include <core/class.h>
	4	#include <core/engctx.h>
	5	#include <core/handle.h>
	6	#include <core/enum.h>
	7
	8	#include <subdev/timer.h>
	9	#include <subdev/fb.h>
	10
	11	#include <engine/graph.h>
	12	#include <engine/fifo.h>
	13
	14	#include "nv20.h"
	15	#include "regs.h"
	16
	17	/*******************************************************************************
	18	* Graphics object classes
	19	******************************************************************************/
	20
	21	static struct nouveau_oclass
	22	nv20_graph_sclass[] = {
	23	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
	24	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
	25	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
	26	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
	27	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
	28	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
	29	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
	30	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
	31	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
	32	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
	33	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
	34	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
	35	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
	36	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
	37	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
	38	{},
a0b1de84 BS	39	};
a0b1de84 BS	40
ebb945a9 BS	41	/*******************************************************************************
	42	* PGRAPH context
	43	******************************************************************************/
6ee73861	44
ebb945a9 BS	45	static int
	46	nv20_graph_context_ctor(struct nouveau_object *parent,
	47	struct nouveau_object *engine,
	48	struct nouveau_oclass oclass, void data, u32 size,
	49	struct nouveau_object **pobject)
a0b1de84	50	{
ebb945a9 BS	51	struct nv20_graph_chan *chan;
ebb945a9 BS	52	int ret, i;
a0b1de84	53
ebb945a9 BS	54	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
	55	0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
	56	&chan);
	57	*pobject = nv_object(chan);
	58	if (ret)
	59	return ret;
a0b1de84	60
ebb945a9	61	chan->chid = nouveau_fifo_chan(parent)->chid;
b8c157d3	62
ebb945a9 BS	63	nv_wo32(chan, 0x0000, 0x00000001 \| (chan->chid << 24));
	64	nv_wo32(chan, 0x033c, 0xffff0000);
	65	nv_wo32(chan, 0x03a0, 0x0fff0000);
	66	nv_wo32(chan, 0x03a4, 0x0fff0000);
	67	nv_wo32(chan, 0x047c, 0x00000101);
	68	nv_wo32(chan, 0x0490, 0x00000111);
	69	nv_wo32(chan, 0x04a8, 0x44400000);
6ee73861	70	for (i = 0x04d4; i <= 0x04e0; i += 4)
ebb945a9	71	nv_wo32(chan, i, 0x00030303);
6ee73861	72	for (i = 0x04f4; i <= 0x0500; i += 4)
ebb945a9	73	nv_wo32(chan, i, 0x00080000);
6ee73861	74	for (i = 0x050c; i <= 0x0518; i += 4)
ebb945a9	75	nv_wo32(chan, i, 0x01012000);
6ee73861	76	for (i = 0x051c; i <= 0x0528; i += 4)
ebb945a9	77	nv_wo32(chan, i, 0x000105b8);
6ee73861	78	for (i = 0x052c; i <= 0x0538; i += 4)
ebb945a9	79	nv_wo32(chan, i, 0x00080008);
6ee73861	80	for (i = 0x055c; i <= 0x0598; i += 4)
ebb945a9 BS	81	nv_wo32(chan, i, 0x07ff0000);
	82	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	83	nv_wo32(chan, 0x05fc, 0x00000001);
	84	nv_wo32(chan, 0x0604, 0x00004000);
	85	nv_wo32(chan, 0x0610, 0x00000001);
	86	nv_wo32(chan, 0x0618, 0x00040000);
	87	nv_wo32(chan, 0x061c, 0x00010000);
6ee73861	88	for (i = 0x1c1c; i <= 0x248c; i += 16) {
ebb945a9 BS	89	nv_wo32(chan, (i + 0), 0x10700ff9);
	90	nv_wo32(chan, (i + 4), 0x0436086c);
	91	nv_wo32(chan, (i + 8), 0x000c001b);
6ee73861	92	}
ebb945a9 BS	93	nv_wo32(chan, 0x281c, 0x3f800000);
	94	nv_wo32(chan, 0x2830, 0x3f800000);
	95	nv_wo32(chan, 0x285c, 0x40000000);
	96	nv_wo32(chan, 0x2860, 0x3f800000);
	97	nv_wo32(chan, 0x2864, 0x3f000000);
	98	nv_wo32(chan, 0x286c, 0x40000000);
	99	nv_wo32(chan, 0x2870, 0x3f800000);
	100	nv_wo32(chan, 0x2878, 0xbf800000);
	101	nv_wo32(chan, 0x2880, 0xbf800000);
	102	nv_wo32(chan, 0x34a4, 0x000fe000);
	103	nv_wo32(chan, 0x3530, 0x000003f8);
	104	nv_wo32(chan, 0x3540, 0x002fe000);
6ee73861	105	for (i = 0x355c; i <= 0x3578; i += 4)
ebb945a9 BS	106	nv_wo32(chan, i, 0x001c527c);
ebb945a9 BS	107	return 0;
6ee73861 BS	108	}
6ee73861 BS	109
ebb945a9 BS	110	int
ebb945a9 BS	111	nv20_graph_context_init(struct nouveau_object *object)
6ee73861	112	{
ebb945a9 BS	113	struct nv20_graph_priv priv = (void )object->engine;
	114	struct nv20_graph_chan chan = (void )object;
	115	int ret;
6ee73861	116
ebb945a9 BS	117	ret = nouveau_graph_context_init(&chan->base);
	118	if (ret)
	119	return ret;
6ee73861	120
ebb945a9 BS	121	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
ebb945a9 BS	122	return 0;
6ee73861 BS	123	}
6ee73861 BS	124
ebb945a9 BS	125	int
ebb945a9 BS	126	nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
6ee73861	127	{
ebb945a9 BS	128	struct nv20_graph_priv priv = (void )object->engine;
	129	struct nv20_graph_chan chan = (void )object;
	130	int chid = -1;
	131
	132	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	133	if (nv_rd32(priv, 0x400144) & 0x00010000)
	134	chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	135	if (chan->chid == chid) {
	136	nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
	137	nv_wr32(priv, 0x400788, 0x00000002);
	138	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	139	nv_wr32(priv, 0x400144, 0x10000000);
	140	nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
6ee73861	141	}
ebb945a9	142	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
6ee73861	143
ebb945a9 BS	144	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
ebb945a9 BS	145	return nouveau_graph_context_fini(&chan->base, suspend);
6ee73861 BS	146	}
6ee73861 BS	147
ebb945a9 BS	148	static struct nouveau_oclass
	149	nv20_graph_cclass = {
	150	.handle = NV_ENGCTX(GR, 0x20),
	151	.ofuncs = &(struct nouveau_ofuncs) {
	152	.ctor = nv20_graph_context_ctor,
	153	.dtor = _nouveau_graph_context_dtor,
	154	.init = nv20_graph_context_init,
	155	.fini = nv20_graph_context_fini,
	156	.rd32 = _nouveau_graph_context_rd32,
	157	.wr32 = _nouveau_graph_context_wr32,
	158	},
	159	};
6ee73861	160
ebb945a9 BS	161	/*******************************************************************************
	162	* PGRAPH engine/subdev functions
	163	******************************************************************************/
6ee73861 BS	164
6ee73861 BS	165	void
ebb945a9	166	nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
6ee73861	167	{
ebb945a9 BS	168	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	169	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	170	struct nv20_graph_priv priv = (void )engine;
3945e475	171	unsigned long flags;
6ee73861	172
ebb945a9 BS	173	pfifo->pause(pfifo, &flags);
ebb945a9 BS	174	nv04_graph_idle(priv);
3945e475	175
ebb945a9 BS	176	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	177	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	178	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	179
ebb945a9 BS	180	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	181	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	182	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	183	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	184	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	185	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	186
fafa0cb3	187	if (nv_device(engine)->chipset != 0x34) {
ebb945a9 BS	188	nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	189	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	190	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	191	}
6ee73861	192
ebb945a9	193	pfifo->start(pfifo, &flags);
6ee73861 BS	194	}
6ee73861 BS	195
ebb945a9 BS	196	void
ebb945a9 BS	197	nv20_graph_intr(struct nouveau_subdev *subdev)
0d87c100	198	{
ebb945a9	199	struct nouveau_engine *engine = nv_engine(subdev);
72a14827 BS	200	struct nouveau_object *engctx;
	201	struct nouveau_handle *handle;
	202	struct nv20_graph_priv priv = (void )subdev;
ebb945a9 BS	203	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	204	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	205	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	206	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	207	u32 chid = (addr & 0x01f00000) >> 20;
	208	u32 subc = (addr & 0x00070000) >> 16;
	209	u32 mthd = (addr & 0x00001ffc);
	210	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	211	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
ebb945a9 BS	212	u32 show = stat;
ebb945a9 BS	213
72a14827	214	engctx = nouveau_engctx_get(engine, chid);
ebb945a9 BS	215	if (stat & NV_PGRAPH_INTR_ERROR) {
ebb945a9 BS	216	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
72a14827	217	handle = nouveau_handle_get_class(engctx, class);
ebb945a9 BS	218	if (handle && !nv_call(handle->object, mthd, data))
ebb945a9 BS	219	show &= ~NV_PGRAPH_INTR_ERROR;
72a14827	220	nouveau_handle_put(handle);
ebb945a9	221	}
87a326a3	222	}
87a326a3	223
ebb945a9 BS	224	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	225	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
	226
	227	if (show) {
950fbfab	228	nv_error(priv, "%s", "");
ebb945a9	229	nouveau_bitfield_print(nv10_graph_intr_name, show);
f533da10	230	pr_cont(" nsource:");
ebb945a9	231	nouveau_bitfield_print(nv04_graph_nsource, nsource);
f533da10	232	pr_cont(" nstatus:");
ebb945a9	233	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
f533da10	234	pr_cont("\n");
93260d3c MS	235	nv_error(priv,
	236	"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
	237	chid, nouveau_client_name(engctx), subc, class, mthd,
	238	data);
6ee73861	239	}
72a14827 BS	240
72a14827 BS	241	nouveau_engctx_put(engctx);
ebb945a9	242	}
6ee73861	243
ebb945a9 BS	244	static int
	245	nv20_graph_ctor(struct nouveau_object parent, struct nouveau_object engine,
	246	struct nouveau_oclass oclass, void data, u32 size,
	247	struct nouveau_object **pobject)
	248	{
	249	struct nv20_graph_priv *priv;
	250	int ret;
6ee73861	251
ebb945a9 BS	252	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	253	*pobject = nv_object(priv);
	254	if (ret)
	255	return ret;
6ee73861	256
a3e6789a	257	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
ebb945a9 BS	258	NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	259	if (ret)
	260	return ret;
6ee73861	261
ebb945a9 BS	262	nv_subdev(priv)->unit = 0x00001000;
	263	nv_subdev(priv)->intr = nv20_graph_intr;
	264	nv_engine(priv)->cclass = &nv20_graph_cclass;
	265	nv_engine(priv)->sclass = nv20_graph_sclass;
	266	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
6ee73861 BS	267	return 0;
	268	}
	269
ebb945a9 BS	270	void
ebb945a9 BS	271	nv20_graph_dtor(struct nouveau_object *object)
6ee73861	272	{
ebb945a9 BS	273	struct nv20_graph_priv priv = (void )object;
	274	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
	275	nouveau_graph_destroy(&priv->base);
	276	}
6ee73861	277
ebb945a9 BS	278	int
	279	nv20_graph_init(struct nouveau_object *object)
	280	{
	281	struct nouveau_engine *engine = nv_engine(object);
	282	struct nv20_graph_priv priv = (void )engine;
	283	struct nouveau_fb *pfb = nouveau_fb(object);
	284	u32 tmp, vramsz;
	285	int ret, i;
6ee73861	286
ebb945a9 BS	287	ret = nouveau_graph_init(&priv->base);
	288	if (ret)
	289	return ret;
6ee73861	290
ebb945a9	291	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
6ee73861	292
ebb945a9 BS	293	if (nv_device(priv)->chipset == 0x20) {
	294	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
	295	for (i = 0; i < 15; i++)
	296	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	297	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	298	} else {
	299	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
	300	for (i = 0; i < 32; i++)
	301	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	302	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
6ee73861 BS	303	}
6ee73861 BS	304
ebb945a9 BS	305	nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
ebb945a9 BS	306	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	307
ebb945a9 BS	308	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	309	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	310	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	311	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	312	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	313	nv_wr32(priv, 0x40009C , 0x00000040);
274fec93	314
ebb945a9 BS	315	if (nv_device(priv)->chipset >= 0x25) {
	316	nv_wr32(priv, 0x400890, 0x00a8cfff);
	317	nv_wr32(priv, 0x400610, 0x304B1FB6);
	318	nv_wr32(priv, 0x400B80, 0x1cbd3883);
	319	nv_wr32(priv, 0x400B84, 0x44000000);
	320	nv_wr32(priv, 0x400098, 0x40000080);
	321	nv_wr32(priv, 0x400B88, 0x000000ff);
274fec93	322
ebb945a9 BS	323	} else {
	324	nv_wr32(priv, 0x400880, 0x0008c7df);
	325	nv_wr32(priv, 0x400094, 0x00000005);
	326	nv_wr32(priv, 0x400B80, 0x45eae20e);
	327	nv_wr32(priv, 0x400B84, 0x24000000);
	328	nv_wr32(priv, 0x400098, 0x00000040);
	329	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	330	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	331	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	332	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	333	}
a0b1de84	334
ebb945a9 BS	335	/* Turn all the tiling regions off. */
	336	for (i = 0; i < pfb->tile.regions; i++)
	337	engine->tile_prog(engine, i);
a0b1de84	338
ebb945a9 BS	339	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	340	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	341	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
a0b1de84	342
ebb945a9 BS	343	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
ebb945a9 BS	344	nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	345
ebb945a9 BS	346	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	347	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	348	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) \| 0x00020100;
	349	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	350
ebb945a9	351	/* begin RAM config */
420b9469	352	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
ebb945a9 BS	353	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	354	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	355	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	356	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	357	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	358	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	359	nv_wr32(priv, 0x400820, 0);
	360	nv_wr32(priv, 0x400824, 0);
	361	nv_wr32(priv, 0x400864, vramsz - 1);
	362	nv_wr32(priv, 0x400868, vramsz - 1);
a0b1de84	363
ebb945a9 BS	364	/* interesting.. the below overwrites some of the tile setup above.. */
	365	nv_wr32(priv, 0x400B20, 0x00000000);
	366	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
a0b1de84	367
ebb945a9 BS	368	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	369	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	370	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	371	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	372	return 0;
a0b1de84 BS	373	}
ebb945a9 BS	374
	375	struct nouveau_oclass
	376	nv20_graph_oclass = {
	377	.handle = NV_ENGINE(GR, 0x20),
	378	.ofuncs = &(struct nouveau_ofuncs) {
	379	.ctor = nv20_graph_ctor,
	380	.dtor = nv20_graph_dtor,
	381	.init = nv20_graph_init,
	382	.fini = _nouveau_graph_fini,
	383	},
	384	};