Commit | Line | Data |
---|---|---|
6ee73861 | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
6ee73861 | 3 | * |
ebb945a9 BS |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
6ee73861 | 10 | * |
ebb945a9 BS |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
6ee73861 | 13 | * |
ebb945a9 BS |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
6ee73861 | 21 | * |
ebb945a9 | 22 | * Authors: Ben Skeggs |
6ee73861 BS |
23 | */ |
24 | ||
ebb945a9 BS |
25 | #include <core/os.h> |
26 | #include <core/class.h> | |
93260d3c | 27 | #include <core/client.h> |
ebb945a9 BS |
28 | #include <core/handle.h> |
29 | #include <core/engctx.h> | |
30 | #include <core/enum.h> | |
304424e1 | 31 | |
ebb945a9 BS |
32 | #include <subdev/fb.h> |
33 | #include <subdev/vm.h> | |
34 | #include <subdev/timer.h> | |
6ee73861 | 35 | |
72a14827 | 36 | #include <engine/fifo.h> |
ebb945a9 | 37 | #include <engine/graph.h> |
6d6538a0 | 38 | |
ebb945a9 | 39 | #include "nv50.h" |
304424e1 | 40 | |
ebb945a9 BS |
41 | struct nv50_graph_priv { |
42 | struct nouveau_graph base; | |
43 | spinlock_t lock; | |
44 | u32 size; | |
45 | }; | |
6ee73861 | 46 | |
ebb945a9 BS |
47 | struct nv50_graph_chan { |
48 | struct nouveau_graph_chan base; | |
49 | }; | |
6d6538a0 | 50 | |
7e22e71e CB |
51 | static u64 |
52 | nv50_graph_units(struct nouveau_graph *graph) | |
53 | { | |
54 | struct nv50_graph_priv *priv = (void *)graph; | |
55 | ||
56 | return nv_rd32(priv, 0x1540); | |
57 | } | |
58 | ||
ebb945a9 BS |
59 | /******************************************************************************* |
60 | * Graphics object classes | |
61 | ******************************************************************************/ | |
562af10c | 62 | |
ebb945a9 BS |
63 | static int |
64 | nv50_graph_object_ctor(struct nouveau_object *parent, | |
65 | struct nouveau_object *engine, | |
66 | struct nouveau_oclass *oclass, void *data, u32 size, | |
67 | struct nouveau_object **pobject) | |
68 | { | |
69 | struct nouveau_gpuobj *obj; | |
70 | int ret; | |
562af10c | 71 | |
ebb945a9 BS |
72 | ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, |
73 | 16, 16, 0, &obj); | |
74 | *pobject = nv_object(obj); | |
75 | if (ret) | |
76 | return ret; | |
6ee73861 | 77 | |
ebb945a9 BS |
78 | nv_wo32(obj, 0x00, nv_mclass(obj)); |
79 | nv_wo32(obj, 0x04, 0x00000000); | |
80 | nv_wo32(obj, 0x08, 0x00000000); | |
81 | nv_wo32(obj, 0x0c, 0x00000000); | |
6ee73861 BS |
82 | return 0; |
83 | } | |
84 | ||
5b8a43ae | 85 | static struct nouveau_ofuncs |
ebb945a9 BS |
86 | nv50_graph_ofuncs = { |
87 | .ctor = nv50_graph_object_ctor, | |
88 | .dtor = _nouveau_gpuobj_dtor, | |
89 | .init = _nouveau_gpuobj_init, | |
90 | .fini = _nouveau_gpuobj_fini, | |
91 | .rd32 = _nouveau_gpuobj_rd32, | |
92 | .wr32 = _nouveau_gpuobj_wr32, | |
93 | }; | |
6ee73861 | 94 | |
ebb945a9 BS |
95 | static struct nouveau_oclass |
96 | nv50_graph_sclass[] = { | |
97 | { 0x0030, &nv50_graph_ofuncs }, | |
98 | { 0x502d, &nv50_graph_ofuncs }, | |
99 | { 0x5039, &nv50_graph_ofuncs }, | |
100 | { 0x5097, &nv50_graph_ofuncs }, | |
101 | { 0x50c0, &nv50_graph_ofuncs }, | |
102 | {} | |
103 | }; | |
6ee73861 | 104 | |
ebb945a9 BS |
105 | static struct nouveau_oclass |
106 | nv84_graph_sclass[] = { | |
107 | { 0x0030, &nv50_graph_ofuncs }, | |
108 | { 0x502d, &nv50_graph_ofuncs }, | |
109 | { 0x5039, &nv50_graph_ofuncs }, | |
110 | { 0x50c0, &nv50_graph_ofuncs }, | |
111 | { 0x8297, &nv50_graph_ofuncs }, | |
112 | {} | |
113 | }; | |
6ee73861 | 114 | |
ebb945a9 BS |
115 | static struct nouveau_oclass |
116 | nva0_graph_sclass[] = { | |
117 | { 0x0030, &nv50_graph_ofuncs }, | |
118 | { 0x502d, &nv50_graph_ofuncs }, | |
119 | { 0x5039, &nv50_graph_ofuncs }, | |
120 | { 0x50c0, &nv50_graph_ofuncs }, | |
121 | { 0x8397, &nv50_graph_ofuncs }, | |
122 | {} | |
123 | }; | |
6ee73861 | 124 | |
ebb945a9 BS |
125 | static struct nouveau_oclass |
126 | nva3_graph_sclass[] = { | |
127 | { 0x0030, &nv50_graph_ofuncs }, | |
128 | { 0x502d, &nv50_graph_ofuncs }, | |
129 | { 0x5039, &nv50_graph_ofuncs }, | |
130 | { 0x50c0, &nv50_graph_ofuncs }, | |
131 | { 0x8597, &nv50_graph_ofuncs }, | |
132 | { 0x85c0, &nv50_graph_ofuncs }, | |
133 | {} | |
134 | }; | |
2703c21a | 135 | |
ebb945a9 BS |
136 | static struct nouveau_oclass |
137 | nvaf_graph_sclass[] = { | |
138 | { 0x0030, &nv50_graph_ofuncs }, | |
139 | { 0x502d, &nv50_graph_ofuncs }, | |
140 | { 0x5039, &nv50_graph_ofuncs }, | |
141 | { 0x50c0, &nv50_graph_ofuncs }, | |
142 | { 0x85c0, &nv50_graph_ofuncs }, | |
143 | { 0x8697, &nv50_graph_ofuncs }, | |
144 | {} | |
145 | }; | |
6ee73861 | 146 | |
ebb945a9 BS |
147 | /******************************************************************************* |
148 | * PGRAPH context | |
149 | ******************************************************************************/ | |
6ee73861 BS |
150 | |
151 | static int | |
ebb945a9 BS |
152 | nv50_graph_context_ctor(struct nouveau_object *parent, |
153 | struct nouveau_object *engine, | |
154 | struct nouveau_oclass *oclass, void *data, u32 size, | |
155 | struct nouveau_object **pobject) | |
4ea52f89 | 156 | { |
ebb945a9 BS |
157 | struct nv50_graph_priv *priv = (void *)engine; |
158 | struct nv50_graph_chan *chan; | |
4ea52f89 BS |
159 | int ret; |
160 | ||
ebb945a9 BS |
161 | ret = nouveau_graph_context_create(parent, engine, oclass, NULL, |
162 | priv->size, 0, | |
163 | NVOBJ_FLAG_ZERO_ALLOC, &chan); | |
164 | *pobject = nv_object(chan); | |
4ea52f89 BS |
165 | if (ret) |
166 | return ret; | |
4ea52f89 | 167 | |
ebb945a9 BS |
168 | nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); |
169 | return 0; | |
4ea52f89 BS |
170 | } |
171 | ||
ebb945a9 BS |
172 | static struct nouveau_oclass |
173 | nv50_graph_cclass = { | |
174 | .handle = NV_ENGCTX(GR, 0x50), | |
175 | .ofuncs = &(struct nouveau_ofuncs) { | |
176 | .ctor = nv50_graph_context_ctor, | |
177 | .dtor = _nouveau_graph_context_dtor, | |
178 | .init = _nouveau_graph_context_init, | |
179 | .fini = _nouveau_graph_context_fini, | |
180 | .rd32 = _nouveau_graph_context_rd32, | |
181 | .wr32 = _nouveau_graph_context_wr32, | |
182 | }, | |
183 | }; | |
184 | ||
185 | /******************************************************************************* | |
186 | * PGRAPH engine/subdev functions | |
187 | ******************************************************************************/ | |
188 | ||
189 | static int | |
190 | nv50_graph_tlb_flush(struct nouveau_engine *engine) | |
56ac7475 | 191 | { |
ebb945a9 BS |
192 | nv50_vm_flush_engine(&engine->base, 0x00); |
193 | return 0; | |
56ac7475 BS |
194 | } |
195 | ||
d432a2db MS |
196 | static const struct nouveau_bitfield nv50_pgraph_status[] = { |
197 | { 0x00000001, "BUSY" }, /* set when any bit is set */ | |
198 | { 0x00000002, "DISPATCH" }, | |
199 | { 0x00000004, "UNK2" }, | |
200 | { 0x00000008, "UNK3" }, | |
201 | { 0x00000010, "UNK4" }, | |
202 | { 0x00000020, "UNK5" }, | |
203 | { 0x00000040, "M2MF" }, | |
204 | { 0x00000080, "UNK7" }, | |
205 | { 0x00000100, "CTXPROG" }, | |
206 | { 0x00000200, "VFETCH" }, | |
207 | { 0x00000400, "CCACHE_UNK4" }, | |
208 | { 0x00000800, "STRMOUT_GSCHED_UNK5" }, | |
209 | { 0x00001000, "UNK14XX" }, | |
210 | { 0x00002000, "UNK24XX_CSCHED" }, | |
211 | { 0x00004000, "UNK1CXX" }, | |
212 | { 0x00008000, "CLIPID" }, | |
213 | { 0x00010000, "ZCULL" }, | |
214 | { 0x00020000, "ENG2D" }, | |
215 | { 0x00040000, "UNK34XX" }, | |
216 | { 0x00080000, "TPRAST" }, | |
217 | { 0x00100000, "TPROP" }, | |
218 | { 0x00200000, "TEX" }, | |
219 | { 0x00400000, "TPVP" }, | |
220 | { 0x00800000, "MP" }, | |
221 | { 0x01000000, "ROP" }, | |
222 | {} | |
223 | }; | |
224 | ||
225 | static const char *const nv50_pgraph_vstatus_0[] = { | |
226 | "VFETCH", "CCACHE", "UNK4", "UNK5", "GSCHED", "STRMOUT", "UNK14XX", NULL | |
227 | }; | |
228 | ||
229 | static const char *const nv50_pgraph_vstatus_1[] = { | |
230 | "TPRAST", "TPROP", "TEXTURE", "TPVP", "MP", NULL | |
231 | }; | |
232 | ||
233 | static const char *const nv50_pgraph_vstatus_2[] = { | |
234 | "UNK24XX", "CSCHED", "UNK1CXX", "CLIPID", "ZCULL", "ENG2D", "UNK34XX", | |
235 | "ROP", NULL | |
236 | }; | |
237 | ||
238 | static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, | |
239 | const char *const units[], u32 status) | |
240 | { | |
241 | int i; | |
242 | ||
243 | nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); | |
244 | ||
245 | for (i = 0; units[i] && status; i++) { | |
246 | if ((status & 7) == 1) | |
247 | pr_cont(" %s", units[i]); | |
248 | status >>= 3; | |
249 | } | |
250 | if (status) | |
251 | pr_cont(" (invalid: 0x%x)", status); | |
252 | pr_cont("\n"); | |
253 | } | |
254 | ||
ebb945a9 BS |
255 | static int |
256 | nv84_graph_tlb_flush(struct nouveau_engine *engine) | |
56ac7475 | 257 | { |
ebb945a9 BS |
258 | struct nouveau_timer *ptimer = nouveau_timer(engine); |
259 | struct nv50_graph_priv *priv = (void *)engine; | |
56ac7475 BS |
260 | bool idle, timeout = false; |
261 | unsigned long flags; | |
262 | u64 start; | |
263 | u32 tmp; | |
264 | ||
ebb945a9 BS |
265 | spin_lock_irqsave(&priv->lock, flags); |
266 | nv_mask(priv, 0x400500, 0x00000001, 0x00000000); | |
56ac7475 | 267 | |
ebb945a9 | 268 | start = ptimer->read(ptimer); |
56ac7475 BS |
269 | do { |
270 | idle = true; | |
271 | ||
ebb945a9 | 272 | for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { |
56ac7475 BS |
273 | if ((tmp & 7) == 1) |
274 | idle = false; | |
275 | } | |
276 | ||
ebb945a9 | 277 | for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { |
56ac7475 BS |
278 | if ((tmp & 7) == 1) |
279 | idle = false; | |
280 | } | |
281 | ||
ebb945a9 | 282 | for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { |
56ac7475 BS |
283 | if ((tmp & 7) == 1) |
284 | idle = false; | |
285 | } | |
ebb945a9 BS |
286 | } while (!idle && |
287 | !(timeout = ptimer->read(ptimer) - start > 2000000000)); | |
56ac7475 BS |
288 | |
289 | if (timeout) { | |
d432a2db MS |
290 | nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); |
291 | ||
292 | tmp = nv_rd32(priv, 0x400700); | |
293 | nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); | |
294 | nouveau_bitfield_print(nv50_pgraph_status, tmp); | |
295 | pr_cont("\n"); | |
296 | ||
297 | nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, | |
298 | nv_rd32(priv, 0x400380)); | |
299 | nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, | |
300 | nv_rd32(priv, 0x400384)); | |
301 | nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, | |
302 | nv_rd32(priv, 0x400388)); | |
56ac7475 BS |
303 | } |
304 | ||
ebb945a9 | 305 | nv50_vm_flush_engine(&engine->base, 0x00); |
56ac7475 | 306 | |
ebb945a9 BS |
307 | nv_mask(priv, 0x400500, 0x00000001, 0x00000001); |
308 | spin_unlock_irqrestore(&priv->lock, flags); | |
309 | return timeout ? -EBUSY : 0; | |
56ac7475 | 310 | } |
274fec93 | 311 | |
e6626254 | 312 | static const struct nouveau_enum nv50_mp_exec_error_names[] = { |
bb9b18a3 BS |
313 | { 3, "STACK_UNDERFLOW", NULL }, |
314 | { 4, "QUADON_ACTIVE", NULL }, | |
315 | { 8, "TIMEOUT", NULL }, | |
316 | { 0x10, "INVALID_OPCODE", NULL }, | |
317 | { 0x40, "BREAKPOINT", NULL }, | |
274fec93 BS |
318 | {} |
319 | }; | |
320 | ||
e6626254 | 321 | static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { |
274fec93 BS |
322 | { 0x00000001, "NOTIFY" }, |
323 | { 0x00000002, "IN" }, | |
324 | { 0x00000004, "OUT" }, | |
325 | {} | |
326 | }; | |
327 | ||
e6626254 | 328 | static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { |
274fec93 BS |
329 | { 0x00000001, "FAULT" }, |
330 | {} | |
331 | }; | |
332 | ||
e6626254 | 333 | static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { |
274fec93 BS |
334 | { 0x00000001, "FAULT" }, |
335 | {} | |
336 | }; | |
337 | ||
e6626254 | 338 | static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { |
274fec93 BS |
339 | { 0x00000001, "FAULT" }, |
340 | {} | |
341 | }; | |
342 | ||
343 | /* There must be a *lot* of these. Will take some time to gather them up. */ | |
e6626254 | 344 | const struct nouveau_enum nv50_data_error_names[] = { |
887cd788 | 345 | { 0x00000003, "INVALID_OPERATION", NULL }, |
bb9b18a3 BS |
346 | { 0x00000004, "INVALID_VALUE", NULL }, |
347 | { 0x00000005, "INVALID_ENUM", NULL }, | |
348 | { 0x00000008, "INVALID_OBJECT", NULL }, | |
349 | { 0x00000009, "READ_ONLY_OBJECT", NULL }, | |
350 | { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, | |
351 | { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, | |
352 | { 0x0000000c, "INVALID_BITFIELD", NULL }, | |
353 | { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, | |
354 | { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, | |
355 | { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, | |
356 | { 0x00000010, "RT_DOUBLE_BIND", NULL }, | |
357 | { 0x00000011, "RT_TYPES_MISMATCH", NULL }, | |
358 | { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, | |
359 | { 0x00000015, "FP_TOO_FEW_REGS", NULL }, | |
360 | { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, | |
361 | { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, | |
362 | { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, | |
363 | { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, | |
364 | { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, | |
365 | { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, | |
366 | { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, | |
367 | { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, | |
368 | { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, | |
369 | { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, | |
370 | { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, | |
547e6c7f | 371 | { 0x00000024, "VP_ZERO_INPUTS", NULL }, |
bb9b18a3 BS |
372 | { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, |
373 | { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, | |
374 | { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, | |
375 | { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, | |
376 | { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, | |
377 | { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, | |
378 | { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, | |
379 | { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, | |
380 | { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, | |
381 | { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, | |
382 | { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, | |
383 | { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, | |
384 | { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, | |
385 | { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, | |
386 | { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, | |
274fec93 BS |
387 | {} |
388 | }; | |
389 | ||
e6626254 | 390 | static const struct nouveau_bitfield nv50_graph_intr_name[] = { |
274fec93 BS |
391 | { 0x00000001, "NOTIFY" }, |
392 | { 0x00000002, "COMPUTE_QUERY" }, | |
393 | { 0x00000010, "ILLEGAL_MTHD" }, | |
394 | { 0x00000020, "ILLEGAL_CLASS" }, | |
395 | { 0x00000040, "DOUBLE_NOTIFY" }, | |
396 | { 0x00001000, "CONTEXT_SWITCH" }, | |
397 | { 0x00010000, "BUFFER_NOTIFY" }, | |
398 | { 0x00100000, "DATA_ERROR" }, | |
399 | { 0x00200000, "TRAP" }, | |
400 | { 0x01000000, "SINGLE_STEP" }, | |
401 | {} | |
402 | }; | |
403 | ||
404 | static void | |
ebb945a9 | 405 | nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) |
274fec93 | 406 | { |
ebb945a9 BS |
407 | u32 units = nv_rd32(priv, 0x1540); |
408 | u32 addr, mp10, status, pc, oplow, ophigh; | |
274fec93 BS |
409 | int i; |
410 | int mps = 0; | |
411 | for (i = 0; i < 4; i++) { | |
412 | if (!(units & 1 << (i+24))) | |
413 | continue; | |
ebb945a9 | 414 | if (nv_device(priv)->chipset < 0xa0) |
274fec93 BS |
415 | addr = 0x408200 + (tpid << 12) + (i << 7); |
416 | else | |
417 | addr = 0x408100 + (tpid << 11) + (i << 7); | |
ebb945a9 BS |
418 | mp10 = nv_rd32(priv, addr + 0x10); |
419 | status = nv_rd32(priv, addr + 0x14); | |
274fec93 BS |
420 | if (!status) |
421 | continue; | |
422 | if (display) { | |
ebb945a9 BS |
423 | nv_rd32(priv, addr + 0x20); |
424 | pc = nv_rd32(priv, addr + 0x24); | |
425 | oplow = nv_rd32(priv, addr + 0x70); | |
426 | ophigh = nv_rd32(priv, addr + 0x74); | |
427 | nv_error(priv, "TRAP_MP_EXEC - " | |
274fec93 BS |
428 | "TP %d MP %d: ", tpid, i); |
429 | nouveau_enum_print(nv50_mp_exec_error_names, status); | |
f533da10 | 430 | pr_cont(" at %06x warp %d, opcode %08x %08x\n", |
274fec93 BS |
431 | pc&0xffffff, pc >> 24, |
432 | oplow, ophigh); | |
433 | } | |
ebb945a9 BS |
434 | nv_wr32(priv, addr + 0x10, mp10); |
435 | nv_wr32(priv, addr + 0x14, 0); | |
274fec93 BS |
436 | mps++; |
437 | } | |
438 | if (!mps && display) | |
ebb945a9 | 439 | nv_error(priv, "TRAP_MP_EXEC - TP %d: " |
274fec93 BS |
440 | "No MPs claiming errors?\n", tpid); |
441 | } | |
442 | ||
443 | static void | |
ebb945a9 BS |
444 | nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, |
445 | u32 ustatus_new, int display, const char *name) | |
274fec93 | 446 | { |
274fec93 | 447 | int tps = 0; |
ebb945a9 | 448 | u32 units = nv_rd32(priv, 0x1540); |
274fec93 | 449 | int i, r; |
ebb945a9 | 450 | u32 ustatus_addr, ustatus; |
274fec93 BS |
451 | for (i = 0; i < 16; i++) { |
452 | if (!(units & (1 << i))) | |
453 | continue; | |
ebb945a9 | 454 | if (nv_device(priv)->chipset < 0xa0) |
274fec93 BS |
455 | ustatus_addr = ustatus_old + (i << 12); |
456 | else | |
457 | ustatus_addr = ustatus_new + (i << 11); | |
ebb945a9 | 458 | ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; |
274fec93 BS |
459 | if (!ustatus) |
460 | continue; | |
461 | tps++; | |
462 | switch (type) { | |
463 | case 6: /* texture error... unknown for now */ | |
274fec93 | 464 | if (display) { |
ebb945a9 | 465 | nv_error(priv, "magic set %d:\n", i); |
274fec93 | 466 | for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) |
ebb945a9 BS |
467 | nv_error(priv, "\t0x%08x: 0x%08x\n", r, |
468 | nv_rd32(priv, r)); | |
274fec93 BS |
469 | } |
470 | break; | |
471 | case 7: /* MP error */ | |
c983e6f6 | 472 | if (ustatus & 0x04030000) { |
ebb945a9 | 473 | nv50_priv_mp_trap(priv, i, display); |
c983e6f6 | 474 | ustatus &= ~0x04030000; |
274fec93 BS |
475 | } |
476 | break; | |
477 | case 8: /* TPDMA error */ | |
478 | { | |
ebb945a9 BS |
479 | u32 e0c = nv_rd32(priv, ustatus_addr + 4); |
480 | u32 e10 = nv_rd32(priv, ustatus_addr + 8); | |
481 | u32 e14 = nv_rd32(priv, ustatus_addr + 0xc); | |
482 | u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); | |
483 | u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); | |
484 | u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); | |
485 | u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); | |
274fec93 BS |
486 | /* 2d engine destination */ |
487 | if (ustatus & 0x00000010) { | |
488 | if (display) { | |
ebb945a9 | 489 | nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n", |
274fec93 | 490 | i, e14, e10); |
ebb945a9 | 491 | nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", |
274fec93 BS |
492 | i, e0c, e18, e1c, e20, e24); |
493 | } | |
494 | ustatus &= ~0x00000010; | |
495 | } | |
496 | /* Render target */ | |
497 | if (ustatus & 0x00000040) { | |
498 | if (display) { | |
ebb945a9 | 499 | nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n", |
274fec93 | 500 | i, e14, e10); |
ebb945a9 | 501 | nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", |
274fec93 BS |
502 | i, e0c, e18, e1c, e20, e24); |
503 | } | |
504 | ustatus &= ~0x00000040; | |
505 | } | |
506 | /* CUDA memory: l[], g[] or stack. */ | |
507 | if (ustatus & 0x00000080) { | |
508 | if (display) { | |
509 | if (e18 & 0x80000000) { | |
510 | /* g[] read fault? */ | |
ebb945a9 | 511 | nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n", |
274fec93 BS |
512 | i, e14, e10 | ((e18 >> 24) & 0x1f)); |
513 | e18 &= ~0x1f000000; | |
514 | } else if (e18 & 0xc) { | |
515 | /* g[] write fault? */ | |
ebb945a9 | 516 | nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n", |
274fec93 BS |
517 | i, e14, e10 | ((e18 >> 7) & 0x1f)); |
518 | e18 &= ~0x00000f80; | |
519 | } else { | |
ebb945a9 | 520 | nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n", |
274fec93 BS |
521 | i, e14, e10); |
522 | } | |
ebb945a9 | 523 | nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", |
274fec93 BS |
524 | i, e0c, e18, e1c, e20, e24); |
525 | } | |
526 | ustatus &= ~0x00000080; | |
527 | } | |
528 | } | |
529 | break; | |
530 | } | |
531 | if (ustatus) { | |
532 | if (display) | |
ae4ba737 | 533 | nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); |
274fec93 | 534 | } |
ebb945a9 | 535 | nv_wr32(priv, ustatus_addr, 0xc0000000); |
274fec93 BS |
536 | } |
537 | ||
538 | if (!tps && display) | |
ae4ba737 | 539 | nv_warn(priv, "%s - No TPs claiming errors?\n", name); |
274fec93 BS |
540 | } |
541 | ||
542 | static int | |
72a14827 | 543 | nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, |
93260d3c | 544 | int chid, u64 inst, struct nouveau_object *engctx) |
274fec93 | 545 | { |
ebb945a9 | 546 | u32 status = nv_rd32(priv, 0x400108); |
274fec93 BS |
547 | u32 ustatus; |
548 | ||
549 | if (!status && display) { | |
ebb945a9 | 550 | nv_error(priv, "TRAP: no units reporting traps?\n"); |
274fec93 BS |
551 | return 1; |
552 | } | |
553 | ||
554 | /* DISPATCH: Relays commands to other units and handles NOTIFY, | |
555 | * COND, QUERY. If you get a trap from it, the command is still stuck | |
556 | * in DISPATCH and you need to do something about it. */ | |
557 | if (status & 0x001) { | |
ebb945a9 | 558 | ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; |
274fec93 | 559 | if (!ustatus && display) { |
ebb945a9 | 560 | nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); |
274fec93 BS |
561 | } |
562 | ||
ebb945a9 | 563 | nv_wr32(priv, 0x400500, 0x00000000); |
274fec93 BS |
564 | |
565 | /* Known to be triggered by screwed up NOTIFY and COND... */ | |
566 | if (ustatus & 0x00000001) { | |
ebb945a9 | 567 | u32 addr = nv_rd32(priv, 0x400808); |
274fec93 BS |
568 | u32 subc = (addr & 0x00070000) >> 16; |
569 | u32 mthd = (addr & 0x00001ffc); | |
ebb945a9 BS |
570 | u32 datal = nv_rd32(priv, 0x40080c); |
571 | u32 datah = nv_rd32(priv, 0x400810); | |
572 | u32 class = nv_rd32(priv, 0x400814); | |
573 | u32 r848 = nv_rd32(priv, 0x400848); | |
274fec93 | 574 | |
ebb945a9 | 575 | nv_error(priv, "TRAP DISPATCH_FAULT\n"); |
274fec93 | 576 | if (display && (addr & 0x80000000)) { |
93260d3c MS |
577 | nv_error(priv, |
578 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", | |
579 | chid, inst, | |
580 | nouveau_client_name(engctx), subc, | |
581 | class, mthd, datah, datal, addr, r848); | |
274fec93 BS |
582 | } else |
583 | if (display) { | |
ebb945a9 | 584 | nv_error(priv, "no stuck command?\n"); |
274fec93 BS |
585 | } |
586 | ||
ebb945a9 BS |
587 | nv_wr32(priv, 0x400808, 0); |
588 | nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); | |
589 | nv_wr32(priv, 0x400848, 0); | |
274fec93 BS |
590 | ustatus &= ~0x00000001; |
591 | } | |
592 | ||
593 | if (ustatus & 0x00000002) { | |
ebb945a9 | 594 | u32 addr = nv_rd32(priv, 0x40084c); |
274fec93 BS |
595 | u32 subc = (addr & 0x00070000) >> 16; |
596 | u32 mthd = (addr & 0x00001ffc); | |
ebb945a9 BS |
597 | u32 data = nv_rd32(priv, 0x40085c); |
598 | u32 class = nv_rd32(priv, 0x400814); | |
274fec93 | 599 | |
ebb945a9 | 600 | nv_error(priv, "TRAP DISPATCH_QUERY\n"); |
274fec93 | 601 | if (display && (addr & 0x80000000)) { |
93260d3c MS |
602 | nv_error(priv, |
603 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", | |
604 | chid, inst, | |
605 | nouveau_client_name(engctx), subc, | |
606 | class, mthd, data, addr); | |
274fec93 BS |
607 | } else |
608 | if (display) { | |
ebb945a9 | 609 | nv_error(priv, "no stuck command?\n"); |
274fec93 BS |
610 | } |
611 | ||
ebb945a9 | 612 | nv_wr32(priv, 0x40084c, 0); |
274fec93 BS |
613 | ustatus &= ~0x00000002; |
614 | } | |
615 | ||
616 | if (ustatus && display) { | |
ebb945a9 | 617 | nv_error(priv, "TRAP_DISPATCH (unknown " |
274fec93 BS |
618 | "0x%08x)\n", ustatus); |
619 | } | |
620 | ||
ebb945a9 BS |
621 | nv_wr32(priv, 0x400804, 0xc0000000); |
622 | nv_wr32(priv, 0x400108, 0x001); | |
274fec93 BS |
623 | status &= ~0x001; |
624 | if (!status) | |
625 | return 0; | |
626 | } | |
627 | ||
628 | /* M2MF: Memory to memory copy engine. */ | |
629 | if (status & 0x002) { | |
ebb945a9 | 630 | u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; |
274fec93 | 631 | if (display) { |
ebb945a9 | 632 | nv_error(priv, "TRAP_M2MF"); |
274fec93 | 633 | nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); |
f533da10 | 634 | pr_cont("\n"); |
ebb945a9 BS |
635 | nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", |
636 | nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), | |
637 | nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); | |
274fec93 BS |
638 | |
639 | } | |
640 | ||
641 | /* No sane way found yet -- just reset the bugger. */ | |
ebb945a9 BS |
642 | nv_wr32(priv, 0x400040, 2); |
643 | nv_wr32(priv, 0x400040, 0); | |
644 | nv_wr32(priv, 0x406800, 0xc0000000); | |
645 | nv_wr32(priv, 0x400108, 0x002); | |
274fec93 BS |
646 | status &= ~0x002; |
647 | } | |
648 | ||
649 | /* VFETCH: Fetches data from vertex buffers. */ | |
650 | if (status & 0x004) { | |
ebb945a9 | 651 | u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; |
274fec93 | 652 | if (display) { |
ebb945a9 | 653 | nv_error(priv, "TRAP_VFETCH"); |
274fec93 | 654 | nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); |
f533da10 | 655 | pr_cont("\n"); |
ebb945a9 BS |
656 | nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", |
657 | nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), | |
658 | nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); | |
274fec93 BS |
659 | } |
660 | ||
ebb945a9 BS |
661 | nv_wr32(priv, 0x400c04, 0xc0000000); |
662 | nv_wr32(priv, 0x400108, 0x004); | |
274fec93 BS |
663 | status &= ~0x004; |
664 | } | |
665 | ||
666 | /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ | |
667 | if (status & 0x008) { | |
ebb945a9 | 668 | ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; |
274fec93 | 669 | if (display) { |
ebb945a9 | 670 | nv_error(priv, "TRAP_STRMOUT"); |
274fec93 | 671 | nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); |
f533da10 | 672 | pr_cont("\n"); |
ebb945a9 BS |
673 | nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", |
674 | nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), | |
675 | nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); | |
274fec93 BS |
676 | |
677 | } | |
678 | ||
679 | /* No sane way found yet -- just reset the bugger. */ | |
ebb945a9 BS |
680 | nv_wr32(priv, 0x400040, 0x80); |
681 | nv_wr32(priv, 0x400040, 0); | |
682 | nv_wr32(priv, 0x401800, 0xc0000000); | |
683 | nv_wr32(priv, 0x400108, 0x008); | |
274fec93 BS |
684 | status &= ~0x008; |
685 | } | |
686 | ||
687 | /* CCACHE: Handles code and c[] caches and fills them. */ | |
688 | if (status & 0x010) { | |
ebb945a9 | 689 | ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; |
274fec93 | 690 | if (display) { |
ebb945a9 | 691 | nv_error(priv, "TRAP_CCACHE"); |
274fec93 | 692 | nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); |
f533da10 | 693 | pr_cont("\n"); |
ebb945a9 | 694 | nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" |
274fec93 | 695 | " %08x %08x %08x\n", |
ebb945a9 BS |
696 | nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), |
697 | nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), | |
698 | nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), | |
699 | nv_rd32(priv, 0x40501c)); | |
274fec93 BS |
700 | |
701 | } | |
702 | ||
ebb945a9 BS |
703 | nv_wr32(priv, 0x405018, 0xc0000000); |
704 | nv_wr32(priv, 0x400108, 0x010); | |
274fec93 BS |
705 | status &= ~0x010; |
706 | } | |
707 | ||
708 | /* Unknown, not seen yet... 0x402000 is the only trap status reg | |
709 | * remaining, so try to handle it anyway. Perhaps related to that | |
710 | * unknown DMA slot on tesla? */ | |
711 | if (status & 0x20) { | |
ebb945a9 | 712 | ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; |
274fec93 | 713 | if (display) |
ebb945a9 BS |
714 | nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); |
715 | nv_wr32(priv, 0x402000, 0xc0000000); | |
274fec93 BS |
716 | /* no status modifiction on purpose */ |
717 | } | |
718 | ||
719 | /* TEXTURE: CUDA texturing units */ | |
720 | if (status & 0x040) { | |
ebb945a9 BS |
721 | nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, |
722 | "TRAP_TEXTURE"); | |
723 | nv_wr32(priv, 0x400108, 0x040); | |
274fec93 BS |
724 | status &= ~0x040; |
725 | } | |
726 | ||
727 | /* MP: CUDA execution engines. */ | |
728 | if (status & 0x080) { | |
ebb945a9 BS |
729 | nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, |
730 | "TRAP_MP"); | |
731 | nv_wr32(priv, 0x400108, 0x080); | |
274fec93 BS |
732 | status &= ~0x080; |
733 | } | |
734 | ||
735 | /* TPDMA: Handles TP-initiated uncached memory accesses: | |
736 | * l[], g[], stack, 2d surfaces, render targets. */ | |
737 | if (status & 0x100) { | |
ebb945a9 BS |
738 | nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, |
739 | "TRAP_TPDMA"); | |
740 | nv_wr32(priv, 0x400108, 0x100); | |
274fec93 BS |
741 | status &= ~0x100; |
742 | } | |
743 | ||
744 | if (status) { | |
745 | if (display) | |
ebb945a9 BS |
746 | nv_error(priv, "TRAP: unknown 0x%08x\n", status); |
747 | nv_wr32(priv, 0x400108, status); | |
274fec93 BS |
748 | } |
749 | ||
750 | return 1; | |
751 | } | |
752 | ||
ebb945a9 BS |
753 | static void |
754 | nv50_graph_intr(struct nouveau_subdev *subdev) | |
274fec93 | 755 | { |
72a14827 | 756 | struct nouveau_fifo *pfifo = nouveau_fifo(subdev); |
ebb945a9 | 757 | struct nouveau_engine *engine = nv_engine(subdev); |
72a14827 | 758 | struct nouveau_object *engctx; |
ebb945a9 | 759 | struct nouveau_handle *handle = NULL; |
72a14827 | 760 | struct nv50_graph_priv *priv = (void *)subdev; |
ebb945a9 | 761 | u32 stat = nv_rd32(priv, 0x400100); |
72a14827 | 762 | u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; |
ebb945a9 BS |
763 | u32 addr = nv_rd32(priv, 0x400704); |
764 | u32 subc = (addr & 0x00070000) >> 16; | |
765 | u32 mthd = (addr & 0x00001ffc); | |
766 | u32 data = nv_rd32(priv, 0x400708); | |
767 | u32 class = nv_rd32(priv, 0x400814); | |
768 | u32 show = stat; | |
72a14827 BS |
769 | int chid; |
770 | ||
771 | engctx = nouveau_engctx_get(engine, inst); | |
772 | chid = pfifo->chid(pfifo, engctx); | |
ebb945a9 BS |
773 | |
774 | if (stat & 0x00000010) { | |
72a14827 | 775 | handle = nouveau_handle_get_class(engctx, class); |
ebb945a9 BS |
776 | if (handle && !nv_call(handle->object, mthd, data)) |
777 | show &= ~0x00000010; | |
72a14827 | 778 | nouveau_handle_put(handle); |
ebb945a9 | 779 | } |
274fec93 | 780 | |
ebb945a9 BS |
781 | if (show & 0x00100000) { |
782 | u32 ecode = nv_rd32(priv, 0x400110); | |
783 | nv_error(priv, "DATA_ERROR "); | |
784 | nouveau_enum_print(nv50_data_error_names, ecode); | |
f533da10 | 785 | pr_cont("\n"); |
ebb945a9 | 786 | } |
274fec93 | 787 | |
ebb945a9 | 788 | if (stat & 0x00200000) { |
93260d3c MS |
789 | if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, |
790 | engctx)) | |
ebb945a9 BS |
791 | show &= ~0x00200000; |
792 | } | |
793 | ||
794 | nv_wr32(priv, 0x400100, stat); | |
795 | nv_wr32(priv, 0x400500, 0x00010001); | |
796 | ||
797 | if (show) { | |
950fbfab | 798 | nv_error(priv, "%s", ""); |
ebb945a9 | 799 | nouveau_bitfield_print(nv50_graph_intr_name, show); |
f533da10 | 800 | pr_cont("\n"); |
93260d3c MS |
801 | nv_error(priv, |
802 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", | |
803 | chid, (u64)inst << 12, nouveau_client_name(engctx), | |
804 | subc, class, mthd, data); | |
274fec93 | 805 | } |
ebb945a9 BS |
806 | |
807 | if (nv_rd32(priv, 0x400824) & (1 << 31)) | |
808 | nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); | |
72a14827 BS |
809 | |
810 | nouveau_engctx_put(engctx); | |
274fec93 BS |
811 | } |
812 | ||
ebb945a9 BS |
813 | static int |
814 | nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
815 | struct nouveau_oclass *oclass, void *data, u32 size, | |
816 | struct nouveau_object **pobject) | |
274fec93 | 817 | { |
ebb945a9 BS |
818 | struct nv50_graph_priv *priv; |
819 | int ret; | |
274fec93 | 820 | |
ebb945a9 BS |
821 | ret = nouveau_graph_create(parent, engine, oclass, true, &priv); |
822 | *pobject = nv_object(priv); | |
823 | if (ret) | |
824 | return ret; | |
274fec93 | 825 | |
ebb945a9 BS |
826 | nv_subdev(priv)->unit = 0x00201000; |
827 | nv_subdev(priv)->intr = nv50_graph_intr; | |
828 | nv_engine(priv)->cclass = &nv50_graph_cclass; | |
274fec93 | 829 | |
7e22e71e CB |
830 | priv->base.units = nv50_graph_units; |
831 | ||
ebb945a9 BS |
832 | switch (nv_device(priv)->chipset) { |
833 | case 0x50: | |
834 | nv_engine(priv)->sclass = nv50_graph_sclass; | |
835 | break; | |
836 | case 0x84: | |
837 | case 0x86: | |
838 | case 0x92: | |
839 | case 0x94: | |
840 | case 0x96: | |
841 | case 0x98: | |
842 | nv_engine(priv)->sclass = nv84_graph_sclass; | |
843 | break; | |
844 | case 0xa0: | |
845 | case 0xaa: | |
846 | case 0xac: | |
847 | nv_engine(priv)->sclass = nva0_graph_sclass; | |
848 | break; | |
849 | case 0xa3: | |
850 | case 0xa5: | |
851 | case 0xa8: | |
852 | nv_engine(priv)->sclass = nva3_graph_sclass; | |
853 | break; | |
854 | case 0xaf: | |
855 | nv_engine(priv)->sclass = nvaf_graph_sclass; | |
856 | break; | |
274fec93 | 857 | |
ebb945a9 | 858 | }; |
274fec93 | 859 | |
ebb945a9 BS |
860 | if (nv_device(priv)->chipset == 0x50 || |
861 | nv_device(priv)->chipset == 0xac) | |
862 | nv_engine(priv)->tlb_flush = nv50_graph_tlb_flush; | |
863 | else | |
864 | nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; | |
274fec93 | 865 | |
ebb945a9 BS |
866 | spin_lock_init(&priv->lock); |
867 | return 0; | |
274fec93 | 868 | } |
2703c21a | 869 | |
ebb945a9 BS |
870 | static int |
871 | nv50_graph_init(struct nouveau_object *object) | |
2703c21a | 872 | { |
ebb945a9 BS |
873 | struct nv50_graph_priv *priv = (void *)object; |
874 | int ret, units, i; | |
2703c21a | 875 | |
ebb945a9 BS |
876 | ret = nouveau_graph_init(&priv->base); |
877 | if (ret) | |
878 | return ret; | |
2703c21a | 879 | |
ebb945a9 BS |
880 | /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ |
881 | nv_wr32(priv, 0x40008c, 0x00000004); | |
2703c21a | 882 | |
ebb945a9 BS |
883 | /* reset/enable traps and interrupts */ |
884 | nv_wr32(priv, 0x400804, 0xc0000000); | |
885 | nv_wr32(priv, 0x406800, 0xc0000000); | |
886 | nv_wr32(priv, 0x400c04, 0xc0000000); | |
887 | nv_wr32(priv, 0x401800, 0xc0000000); | |
888 | nv_wr32(priv, 0x405018, 0xc0000000); | |
889 | nv_wr32(priv, 0x402000, 0xc0000000); | |
890 | ||
891 | units = nv_rd32(priv, 0x001540); | |
892 | for (i = 0; i < 16; i++) { | |
893 | if (!(units & (1 << i))) | |
894 | continue; | |
2703c21a | 895 | |
ebb945a9 BS |
896 | if (nv_device(priv)->chipset < 0xa0) { |
897 | nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); | |
898 | nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); | |
899 | nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); | |
900 | } else { | |
901 | nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); | |
902 | nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); | |
903 | nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); | |
904 | } | |
2703c21a BS |
905 | } |
906 | ||
ebb945a9 BS |
907 | nv_wr32(priv, 0x400108, 0xffffffff); |
908 | nv_wr32(priv, 0x400138, 0xffffffff); | |
909 | nv_wr32(priv, 0x400100, 0xffffffff); | |
910 | nv_wr32(priv, 0x40013c, 0xffffffff); | |
911 | nv_wr32(priv, 0x400500, 0x00010001); | |
2703c21a | 912 | |
ebb945a9 BS |
913 | /* upload context program, initialise ctxctl defaults */ |
914 | ret = nv50_grctx_init(nv_device(priv), &priv->size); | |
915 | if (ret) | |
916 | return ret; | |
2703c21a | 917 | |
ebb945a9 BS |
918 | nv_wr32(priv, 0x400824, 0x00000000); |
919 | nv_wr32(priv, 0x400828, 0x00000000); | |
920 | nv_wr32(priv, 0x40082c, 0x00000000); | |
921 | nv_wr32(priv, 0x400830, 0x00000000); | |
ebb945a9 | 922 | nv_wr32(priv, 0x40032c, 0x00000000); |
f63740fd | 923 | nv_wr32(priv, 0x400330, 0x00000000); |
2703c21a | 924 | |
ebb945a9 BS |
925 | /* some unknown zcull magic */ |
926 | switch (nv_device(priv)->chipset & 0xf0) { | |
927 | case 0x50: | |
928 | case 0x80: | |
929 | case 0x90: | |
930 | nv_wr32(priv, 0x402ca8, 0x00000800); | |
931 | break; | |
932 | case 0xa0: | |
933 | default: | |
934 | nv_wr32(priv, 0x402cc0, 0x00000000); | |
935 | if (nv_device(priv)->chipset == 0xa0 || | |
936 | nv_device(priv)->chipset == 0xaa || | |
937 | nv_device(priv)->chipset == 0xac) { | |
938 | nv_wr32(priv, 0x402ca8, 0x00000802); | |
939 | } else { | |
940 | nv_wr32(priv, 0x402cc0, 0x00000000); | |
941 | nv_wr32(priv, 0x402ca8, 0x00000002); | |
2703c21a | 942 | } |
2703c21a | 943 | |
ebb945a9 BS |
944 | break; |
945 | } | |
2703c21a | 946 | |
ebb945a9 BS |
947 | /* zero out zcull regions */ |
948 | for (i = 0; i < 8; i++) { | |
949 | nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); | |
950 | nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); | |
951 | nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); | |
952 | nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); | |
953 | } | |
2703c21a BS |
954 | return 0; |
955 | } | |
ebb945a9 BS |
956 | |
957 | struct nouveau_oclass | |
958 | nv50_graph_oclass = { | |
959 | .handle = NV_ENGINE(GR, 0x50), | |
960 | .ofuncs = &(struct nouveau_ofuncs) { | |
961 | .ctor = nv50_graph_ctor, | |
962 | .dtor = _nouveau_graph_dtor, | |
963 | .init = nv50_graph_init, | |
964 | .fini = _nouveau_graph_fini, | |
965 | }, | |
966 | }; |