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drm/nouveau: split fifo interrupt handler
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / nv50.c
CommitLineData
6ee73861 1/*
ebb945a9 2 * Copyright 2012 Red Hat Inc.
6ee73861 3 *
ebb945a9
BS		 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
6ee73861 10 *
ebb945a9
BS		 11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
6ee73861 13 *
ebb945a9
BS		 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
6ee73861 21 *
ebb945a9 22 * Authors: Ben Skeggs
6ee73861
BS		 23 */
24
ebb945a9
BS		 25#include <core/os.h>
26#include <core/class.h>
27#include <core/handle.h>
28#include <core/engctx.h>
29#include <core/enum.h>
304424e1 30
ebb945a9
BS		 31#include <subdev/fb.h>
32#include <subdev/vm.h>
33#include <subdev/timer.h>
6ee73861 34
72a14827 35#include <engine/fifo.h>
ebb945a9 36#include <engine/graph.h>
6d6538a0 37
ebb945a9 38#include "nv50.h"
304424e1 39
ebb945a9
BS		 40struct nv50_graph_priv {
41 struct nouveau_graph base;
42 spinlock_t lock;
43 u32 size;
44};
6ee73861 45
ebb945a9
BS		 46struct nv50_graph_chan {
47 struct nouveau_graph_chan base;
48};
6d6538a0 49
ebb945a9
BS		 50/*******************************************************************************
51 * Graphics object classes
52 ******************************************************************************/
562af10c 53
ebb945a9
BS		 54static int
55nv50_graph_object_ctor(struct nouveau_object *parent,
56 struct nouveau_object *engine,
57 struct nouveau_oclass *oclass, void *data, u32 size,
58 struct nouveau_object **pobject)
59{
60 struct nouveau_gpuobj *obj;
61 int ret;
562af10c 62
ebb945a9
BS		 63 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
64 16, 16, 0, &obj);
65 *pobject = nv_object(obj);
66 if (ret)
67 return ret;
6ee73861 68
ebb945a9
BS		 69 nv_wo32(obj, 0x00, nv_mclass(obj));
70 nv_wo32(obj, 0x04, 0x00000000);
71 nv_wo32(obj, 0x08, 0x00000000);
72 nv_wo32(obj, 0x0c, 0x00000000);
6ee73861
BS		 73 return 0;
74}
75
5b8a43ae 76static struct nouveau_ofuncs
ebb945a9
BS		 77nv50_graph_ofuncs = {
78 .ctor = nv50_graph_object_ctor,
79 .dtor = _nouveau_gpuobj_dtor,
80 .init = _nouveau_gpuobj_init,
81 .fini = _nouveau_gpuobj_fini,
82 .rd32 = _nouveau_gpuobj_rd32,
83 .wr32 = _nouveau_gpuobj_wr32,
84};
6ee73861 85
ebb945a9
BS		 86static struct nouveau_oclass
87nv50_graph_sclass[] = {
88 { 0x0030, &nv50_graph_ofuncs },
89 { 0x502d, &nv50_graph_ofuncs },
90 { 0x5039, &nv50_graph_ofuncs },
91 { 0x5097, &nv50_graph_ofuncs },
92 { 0x50c0, &nv50_graph_ofuncs },
93 {}
94};
6ee73861 95
ebb945a9
BS		 96static struct nouveau_oclass
97nv84_graph_sclass[] = {
98 { 0x0030, &nv50_graph_ofuncs },
99 { 0x502d, &nv50_graph_ofuncs },
100 { 0x5039, &nv50_graph_ofuncs },
101 { 0x50c0, &nv50_graph_ofuncs },
102 { 0x8297, &nv50_graph_ofuncs },
103 {}
104};
6ee73861 105
ebb945a9
BS		 106static struct nouveau_oclass
107nva0_graph_sclass[] = {
108 { 0x0030, &nv50_graph_ofuncs },
109 { 0x502d, &nv50_graph_ofuncs },
110 { 0x5039, &nv50_graph_ofuncs },
111 { 0x50c0, &nv50_graph_ofuncs },
112 { 0x8397, &nv50_graph_ofuncs },
113 {}
114};
6ee73861 115
ebb945a9
BS		 116static struct nouveau_oclass
117nva3_graph_sclass[] = {
118 { 0x0030, &nv50_graph_ofuncs },
119 { 0x502d, &nv50_graph_ofuncs },
120 { 0x5039, &nv50_graph_ofuncs },
121 { 0x50c0, &nv50_graph_ofuncs },
122 { 0x8597, &nv50_graph_ofuncs },
123 { 0x85c0, &nv50_graph_ofuncs },
124 {}
125};
2703c21a 126
ebb945a9
BS		 127static struct nouveau_oclass
128nvaf_graph_sclass[] = {
129 { 0x0030, &nv50_graph_ofuncs },
130 { 0x502d, &nv50_graph_ofuncs },
131 { 0x5039, &nv50_graph_ofuncs },
132 { 0x50c0, &nv50_graph_ofuncs },
133 { 0x85c0, &nv50_graph_ofuncs },
134 { 0x8697, &nv50_graph_ofuncs },
135 {}
136};
6ee73861 137
ebb945a9
BS		 138/*******************************************************************************
139 * PGRAPH context
140 ******************************************************************************/
6ee73861
BS		 141
142static int
ebb945a9
BS		 143nv50_graph_context_ctor(struct nouveau_object *parent,
144 struct nouveau_object *engine,
145 struct nouveau_oclass *oclass, void *data, u32 size,
146 struct nouveau_object **pobject)
4ea52f89 147{
ebb945a9
BS		 148 struct nv50_graph_priv *priv = (void *)engine;
149 struct nv50_graph_chan *chan;
4ea52f89
BS		 150 int ret;
151
ebb945a9
BS		 152 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
153 priv->size, 0,
154 NVOBJ_FLAG_ZERO_ALLOC, &chan);
155 *pobject = nv_object(chan);
4ea52f89
BS		 156 if (ret)
157 return ret;
4ea52f89 158
ebb945a9
BS		 159 nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
160 return 0;
4ea52f89
BS		 161}
162
ebb945a9
BS		 163static struct nouveau_oclass
164nv50_graph_cclass = {
165 .handle = NV_ENGCTX(GR, 0x50),
166 .ofuncs = &(struct nouveau_ofuncs) {
167 .ctor = nv50_graph_context_ctor,
168 .dtor = _nouveau_graph_context_dtor,
169 .init = _nouveau_graph_context_init,
170 .fini = _nouveau_graph_context_fini,
171 .rd32 = _nouveau_graph_context_rd32,
172 .wr32 = _nouveau_graph_context_wr32,
173 },
174};
175
176/*******************************************************************************
177 * PGRAPH engine/subdev functions
178 ******************************************************************************/
179
180static int
181nv50_graph_tlb_flush(struct nouveau_engine *engine)
56ac7475 182{
ebb945a9
BS		 183 nv50_vm_flush_engine(&engine->base, 0x00);
184 return 0;
56ac7475
BS		 185}
186
d432a2db
MS		 187static const struct nouveau_bitfield nv50_pgraph_status[] = {
188 { 0x00000001, "BUSY" }, /* set when any bit is set */
189 { 0x00000002, "DISPATCH" },
190 { 0x00000004, "UNK2" },
191 { 0x00000008, "UNK3" },
192 { 0x00000010, "UNK4" },
193 { 0x00000020, "UNK5" },
194 { 0x00000040, "M2MF" },
195 { 0x00000080, "UNK7" },
196 { 0x00000100, "CTXPROG" },
197 { 0x00000200, "VFETCH" },
198 { 0x00000400, "CCACHE_UNK4" },
199 { 0x00000800, "STRMOUT_GSCHED_UNK5" },
200 { 0x00001000, "UNK14XX" },
201 { 0x00002000, "UNK24XX_CSCHED" },
202 { 0x00004000, "UNK1CXX" },
203 { 0x00008000, "CLIPID" },
204 { 0x00010000, "ZCULL" },
205 { 0x00020000, "ENG2D" },
206 { 0x00040000, "UNK34XX" },
207 { 0x00080000, "TPRAST" },
208 { 0x00100000, "TPROP" },
209 { 0x00200000, "TEX" },
210 { 0x00400000, "TPVP" },
211 { 0x00800000, "MP" },
212 { 0x01000000, "ROP" },
213 {}
214};
215
216static const char *const nv50_pgraph_vstatus_0[] = {
217 "VFETCH", "CCACHE", "UNK4", "UNK5", "GSCHED", "STRMOUT", "UNK14XX", NULL
218};
219
220static const char *const nv50_pgraph_vstatus_1[] = {
221 "TPRAST", "TPROP", "TEXTURE", "TPVP", "MP", NULL
222};
223
224static const char *const nv50_pgraph_vstatus_2[] = {
225 "UNK24XX", "CSCHED", "UNK1CXX", "CLIPID", "ZCULL", "ENG2D", "UNK34XX",
226 "ROP", NULL
227};
228
229static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
230 const char *const units[], u32 status)
231{
232 int i;
233
234 nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
235
236 for (i = 0; units[i] && status; i++) {
237 if ((status & 7) == 1)
238 pr_cont(" %s", units[i]);
239 status >>= 3;
240 }
241 if (status)
242 pr_cont(" (invalid: 0x%x)", status);
243 pr_cont("\n");
244}
245
ebb945a9
BS		 246static int
247nv84_graph_tlb_flush(struct nouveau_engine *engine)
56ac7475 248{
ebb945a9
BS		 249 struct nouveau_timer *ptimer = nouveau_timer(engine);
250 struct nv50_graph_priv *priv = (void *)engine;
56ac7475
BS		 251 bool idle, timeout = false;
252 unsigned long flags;
253 u64 start;
254 u32 tmp;
255
ebb945a9
BS		 256 spin_lock_irqsave(&priv->lock, flags);
257 nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
56ac7475 258
ebb945a9 259 start = ptimer->read(ptimer);
56ac7475
BS		 260 do {
261 idle = true;
262
ebb945a9 263 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
56ac7475
BS		 264 if ((tmp & 7) == 1)
265 idle = false;
266 }
267
ebb945a9 268 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
56ac7475
BS		 269 if ((tmp & 7) == 1)
270 idle = false;
271 }
272
ebb945a9 273 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
56ac7475
BS		 274 if ((tmp & 7) == 1)
275 idle = false;
276 }
ebb945a9
BS		 277 } while (!idle &&
278 !(timeout = ptimer->read(ptimer) - start > 2000000000));
56ac7475
BS		 279
280 if (timeout) {
d432a2db
MS		 281 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
282
283 tmp = nv_rd32(priv, 0x400700);
284 nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
285 nouveau_bitfield_print(nv50_pgraph_status, tmp);
286 pr_cont("\n");
287
288 nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
289 nv_rd32(priv, 0x400380));
290 nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
291 nv_rd32(priv, 0x400384));
292 nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
293 nv_rd32(priv, 0x400388));
56ac7475
BS		 294 }
295
ebb945a9 296 nv50_vm_flush_engine(&engine->base, 0x00);
56ac7475 297
ebb945a9
BS		 298 nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
299 spin_unlock_irqrestore(&priv->lock, flags);
300 return timeout ? -EBUSY : 0;
56ac7475 301}
274fec93 302
e6626254 303static const struct nouveau_enum nv50_mp_exec_error_names[] = {
bb9b18a3
BS		 304 { 3, "STACK_UNDERFLOW", NULL },
305 { 4, "QUADON_ACTIVE", NULL },
306 { 8, "TIMEOUT", NULL },
307 { 0x10, "INVALID_OPCODE", NULL },
308 { 0x40, "BREAKPOINT", NULL },
274fec93
BS		 309 {}
310};
311
e6626254 312static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
274fec93
BS		 313 { 0x00000001, "NOTIFY" },
314 { 0x00000002, "IN" },
315 { 0x00000004, "OUT" },
316 {}
317};
318
e6626254 319static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
274fec93
BS		 320 { 0x00000001, "FAULT" },
321 {}
322};
323
e6626254 324static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
274fec93
BS		 325 { 0x00000001, "FAULT" },
326 {}
327};
328
e6626254 329static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
274fec93
BS		 330 { 0x00000001, "FAULT" },
331 {}
332};
333
334/* There must be a *lot* of these. Will take some time to gather them up. */
e6626254 335const struct nouveau_enum nv50_data_error_names[] = {
887cd788 336 { 0x00000003, "INVALID_OPERATION", NULL },
bb9b18a3
BS		 337 { 0x00000004, "INVALID_VALUE", NULL },
338 { 0x00000005, "INVALID_ENUM", NULL },
339 { 0x00000008, "INVALID_OBJECT", NULL },
340 { 0x00000009, "READ_ONLY_OBJECT", NULL },
341 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
342 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
343 { 0x0000000c, "INVALID_BITFIELD", NULL },
344 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
345 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
346 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
347 { 0x00000010, "RT_DOUBLE_BIND", NULL },
348 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
349 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
350 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
351 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
352 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
353 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
354 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
355 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
356 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
357 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
358 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
359 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
360 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
361 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
547e6c7f 362 { 0x00000024, "VP_ZERO_INPUTS", NULL },
bb9b18a3
BS		 363 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
364 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
365 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
366 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
367 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
368 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
369 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
370 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
371 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
372 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
373 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
374 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
375 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
376 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
377 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
274fec93
BS		 378 {}
379};
380
e6626254 381static const struct nouveau_bitfield nv50_graph_intr_name[] = {
274fec93
BS		 382 { 0x00000001, "NOTIFY" },
383 { 0x00000002, "COMPUTE_QUERY" },
384 { 0x00000010, "ILLEGAL_MTHD" },
385 { 0x00000020, "ILLEGAL_CLASS" },
386 { 0x00000040, "DOUBLE_NOTIFY" },
387 { 0x00001000, "CONTEXT_SWITCH" },
388 { 0x00010000, "BUFFER_NOTIFY" },
389 { 0x00100000, "DATA_ERROR" },
390 { 0x00200000, "TRAP" },
391 { 0x01000000, "SINGLE_STEP" },
392 {}
393};
394
395static void
ebb945a9 396nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
274fec93 397{
ebb945a9
BS		 398 u32 units = nv_rd32(priv, 0x1540);
399 u32 addr, mp10, status, pc, oplow, ophigh;
274fec93
BS		 400 int i;
401 int mps = 0;
402 for (i = 0; i < 4; i++) {
403 if (!(units & 1 << (i+24)))
404 continue;
ebb945a9 405 if (nv_device(priv)->chipset < 0xa0)
274fec93
BS		 406 addr = 0x408200 + (tpid << 12) + (i << 7);
407 else
408 addr = 0x408100 + (tpid << 11) + (i << 7);
ebb945a9
BS		 409 mp10 = nv_rd32(priv, addr + 0x10);
410 status = nv_rd32(priv, addr + 0x14);
274fec93
BS		 411 if (!status)
412 continue;
413 if (display) {
ebb945a9
BS		 414 nv_rd32(priv, addr + 0x20);
415 pc = nv_rd32(priv, addr + 0x24);
416 oplow = nv_rd32(priv, addr + 0x70);
417 ophigh = nv_rd32(priv, addr + 0x74);
418 nv_error(priv, "TRAP_MP_EXEC - "
274fec93
BS		 419 "TP %d MP %d: ", tpid, i);
420 nouveau_enum_print(nv50_mp_exec_error_names, status);
421 printk(" at %06x warp %d, opcode %08x %08x\n",
422 pc&0xffffff, pc >> 24,
423 oplow, ophigh);
424 }
ebb945a9
BS		 425 nv_wr32(priv, addr + 0x10, mp10);
426 nv_wr32(priv, addr + 0x14, 0);
274fec93
BS		 427 mps++;
428 }
429 if (!mps && display)
ebb945a9 430 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
274fec93
BS		 431 "No MPs claiming errors?\n", tpid);
432}
433
434static void
ebb945a9
BS		 435nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
436 u32 ustatus_new, int display, const char *name)
274fec93 437{
274fec93 438 int tps = 0;
ebb945a9 439 u32 units = nv_rd32(priv, 0x1540);
274fec93 440 int i, r;
ebb945a9 441 u32 ustatus_addr, ustatus;
274fec93
BS		 442 for (i = 0; i < 16; i++) {
443 if (!(units & (1 << i)))
444 continue;
ebb945a9 445 if (nv_device(priv)->chipset < 0xa0)
274fec93
BS		 446 ustatus_addr = ustatus_old + (i << 12);
447 else
448 ustatus_addr = ustatus_new + (i << 11);
ebb945a9 449 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
274fec93
BS		 450 if (!ustatus)
451 continue;
452 tps++;
453 switch (type) {
454 case 6: /* texture error... unknown for now */
274fec93 455 if (display) {
ebb945a9 456 nv_error(priv, "magic set %d:\n", i);
274fec93 457 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
ebb945a9
BS		 458 nv_error(priv, "\t0x%08x: 0x%08x\n", r,
459 nv_rd32(priv, r));
274fec93
BS		 460 }
461 break;
462 case 7: /* MP error */
c983e6f6 463 if (ustatus & 0x04030000) {
ebb945a9 464 nv50_priv_mp_trap(priv, i, display);
c983e6f6 465 ustatus &= ~0x04030000;
274fec93
BS		 466 }
467 break;
468 case 8: /* TPDMA error */
469 {
ebb945a9
BS		 470 u32 e0c = nv_rd32(priv, ustatus_addr + 4);
471 u32 e10 = nv_rd32(priv, ustatus_addr + 8);
472 u32 e14 = nv_rd32(priv, ustatus_addr + 0xc);
473 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
474 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
475 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
476 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
274fec93
BS		 477 /* 2d engine destination */
478 if (ustatus & 0x00000010) {
479 if (display) {
ebb945a9 480 nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
274fec93 481 i, e14, e10);
ebb945a9 482 nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
274fec93
BS		 483 i, e0c, e18, e1c, e20, e24);
484 }
485 ustatus &= ~0x00000010;
486 }
487 /* Render target */
488 if (ustatus & 0x00000040) {
489 if (display) {
ebb945a9 490 nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
274fec93 491 i, e14, e10);
ebb945a9 492 nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
274fec93
BS		 493 i, e0c, e18, e1c, e20, e24);
494 }
495 ustatus &= ~0x00000040;
496 }
497 /* CUDA memory: l[], g[] or stack. */
498 if (ustatus & 0x00000080) {
499 if (display) {
500 if (e18 & 0x80000000) {
501 /* g[] read fault? */
ebb945a9 502 nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
274fec93
BS		 503 i, e14, e10 | ((e18 >> 24) & 0x1f));
504 e18 &= ~0x1f000000;
505 } else if (e18 & 0xc) {
506 /* g[] write fault? */
ebb945a9 507 nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
274fec93
BS		 508 i, e14, e10 | ((e18 >> 7) & 0x1f));
509 e18 &= ~0x00000f80;
510 } else {
ebb945a9 511 nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
274fec93
BS		 512 i, e14, e10);
513 }
ebb945a9 514 nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
274fec93
BS		 515 i, e0c, e18, e1c, e20, e24);
516 }
517 ustatus &= ~0x00000080;
518 }
519 }
520 break;
521 }
522 if (ustatus) {
523 if (display)
ae4ba737 524 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
274fec93 525 }
ebb945a9 526 nv_wr32(priv, ustatus_addr, 0xc0000000);
274fec93
BS		 527 }
528
529 if (!tps && display)
ae4ba737 530 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
274fec93
BS		 531}
532
533static int
72a14827
BS		 534nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
535 int chid, u64 inst)
274fec93 536{
ebb945a9 537 u32 status = nv_rd32(priv, 0x400108);
274fec93
BS		 538 u32 ustatus;
539
540 if (!status && display) {
ebb945a9 541 nv_error(priv, "TRAP: no units reporting traps?\n");
274fec93
BS		 542 return 1;
543 }
544
545 /* DISPATCH: Relays commands to other units and handles NOTIFY,
546 * COND, QUERY. If you get a trap from it, the command is still stuck
547 * in DISPATCH and you need to do something about it. */
548 if (status & 0x001) {
ebb945a9 549 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
274fec93 550 if (!ustatus && display) {
ebb945a9 551 nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
274fec93
BS		 552 }
553
ebb945a9 554 nv_wr32(priv, 0x400500, 0x00000000);
274fec93
BS		 555
556 /* Known to be triggered by screwed up NOTIFY and COND... */
557 if (ustatus & 0x00000001) {
ebb945a9 558 u32 addr = nv_rd32(priv, 0x400808);
274fec93
BS		 559 u32 subc = (addr & 0x00070000) >> 16;
560 u32 mthd = (addr & 0x00001ffc);
ebb945a9
BS		 561 u32 datal = nv_rd32(priv, 0x40080c);
562 u32 datah = nv_rd32(priv, 0x400810);
563 u32 class = nv_rd32(priv, 0x400814);
564 u32 r848 = nv_rd32(priv, 0x400848);
274fec93 565
ebb945a9 566 nv_error(priv, "TRAP DISPATCH_FAULT\n");
274fec93 567 if (display && (addr & 0x80000000)) {
72a14827 568 nv_error(priv, "ch %d [0x%010llx] "
274fec93
BS		 569 "subc %d class 0x%04x mthd 0x%04x "
570 "data 0x%08x%08x "
571 "400808 0x%08x 400848 0x%08x\n",
72a14827 572 chid, inst, subc, class, mthd, datah,
274fec93
BS		 573 datal, addr, r848);
574 } else
575 if (display) {
ebb945a9 576 nv_error(priv, "no stuck command?\n");
274fec93
BS		 577 }
578
ebb945a9
BS		 579 nv_wr32(priv, 0x400808, 0);
580 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
581 nv_wr32(priv, 0x400848, 0);
274fec93
BS		 582 ustatus &= ~0x00000001;
583 }
584
585 if (ustatus & 0x00000002) {
ebb945a9 586 u32 addr = nv_rd32(priv, 0x40084c);
274fec93
BS		 587 u32 subc = (addr & 0x00070000) >> 16;
588 u32 mthd = (addr & 0x00001ffc);
ebb945a9
BS		 589 u32 data = nv_rd32(priv, 0x40085c);
590 u32 class = nv_rd32(priv, 0x400814);
274fec93 591
ebb945a9 592 nv_error(priv, "TRAP DISPATCH_QUERY\n");
274fec93 593 if (display && (addr & 0x80000000)) {
72a14827 594 nv_error(priv, "ch %d [0x%010llx] "
274fec93
BS		 595 "subc %d class 0x%04x mthd 0x%04x "
596 "data 0x%08x 40084c 0x%08x\n",
72a14827 597 chid, inst, subc, class, mthd,
274fec93
BS		 598 data, addr);
599 } else
600 if (display) {
ebb945a9 601 nv_error(priv, "no stuck command?\n");
274fec93
BS		 602 }
603
ebb945a9 604 nv_wr32(priv, 0x40084c, 0);
274fec93
BS		 605 ustatus &= ~0x00000002;
606 }
607
608 if (ustatus && display) {
ebb945a9 609 nv_error(priv, "TRAP_DISPATCH (unknown "
274fec93
BS		 610 "0x%08x)\n", ustatus);
611 }
612
ebb945a9
BS		 613 nv_wr32(priv, 0x400804, 0xc0000000);
614 nv_wr32(priv, 0x400108, 0x001);
274fec93
BS		 615 status &= ~0x001;
616 if (!status)
617 return 0;
618 }
619
620 /* M2MF: Memory to memory copy engine. */
621 if (status & 0x002) {
ebb945a9 622 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
274fec93 623 if (display) {
ebb945a9 624 nv_error(priv, "TRAP_M2MF");
274fec93
BS		 625 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
626 printk("\n");
ebb945a9
BS		 627 nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
628 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
629 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
274fec93
BS		 630
631 }
632
633 /* No sane way found yet -- just reset the bugger. */
ebb945a9
BS		 634 nv_wr32(priv, 0x400040, 2);
635 nv_wr32(priv, 0x400040, 0);
636 nv_wr32(priv, 0x406800, 0xc0000000);
637 nv_wr32(priv, 0x400108, 0x002);
274fec93
BS		 638 status &= ~0x002;
639 }
640
641 /* VFETCH: Fetches data from vertex buffers. */
642 if (status & 0x004) {
ebb945a9 643 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
274fec93 644 if (display) {
ebb945a9 645 nv_error(priv, "TRAP_VFETCH");
274fec93
BS		 646 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
647 printk("\n");
ebb945a9
BS		 648 nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
649 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
650 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
274fec93
BS		 651 }
652
ebb945a9
BS		 653 nv_wr32(priv, 0x400c04, 0xc0000000);
654 nv_wr32(priv, 0x400108, 0x004);
274fec93
BS		 655 status &= ~0x004;
656 }
657
658 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
659 if (status & 0x008) {
ebb945a9 660 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
274fec93 661 if (display) {
ebb945a9 662 nv_error(priv, "TRAP_STRMOUT");
274fec93
BS		 663 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
664 printk("\n");
ebb945a9
BS		 665 nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
666 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
667 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
274fec93
BS		 668
669 }
670
671 /* No sane way found yet -- just reset the bugger. */
ebb945a9
BS		 672 nv_wr32(priv, 0x400040, 0x80);
673 nv_wr32(priv, 0x400040, 0);
674 nv_wr32(priv, 0x401800, 0xc0000000);
675 nv_wr32(priv, 0x400108, 0x008);
274fec93
BS		 676 status &= ~0x008;
677 }
678
679 /* CCACHE: Handles code and c[] caches and fills them. */
680 if (status & 0x010) {
ebb945a9 681 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
274fec93 682 if (display) {
ebb945a9 683 nv_error(priv, "TRAP_CCACHE");
274fec93
BS		 684 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
685 printk("\n");
ebb945a9 686 nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
274fec93 687 " %08x %08x %08x\n",
ebb945a9
BS		 688 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
689 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
690 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
691 nv_rd32(priv, 0x40501c));
274fec93
BS		 692
693 }
694
ebb945a9
BS		 695 nv_wr32(priv, 0x405018, 0xc0000000);
696 nv_wr32(priv, 0x400108, 0x010);
274fec93
BS		 697 status &= ~0x010;
698 }
699
700 /* Unknown, not seen yet... 0x402000 is the only trap status reg
701 * remaining, so try to handle it anyway. Perhaps related to that
702 * unknown DMA slot on tesla? */
703 if (status & 0x20) {
ebb945a9 704 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
274fec93 705 if (display)
ebb945a9
BS		 706 nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
707 nv_wr32(priv, 0x402000, 0xc0000000);
274fec93
BS		 708 /* no status modifiction on purpose */
709 }
710
711 /* TEXTURE: CUDA texturing units */
712 if (status & 0x040) {
ebb945a9
BS		 713 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
714 "TRAP_TEXTURE");
715 nv_wr32(priv, 0x400108, 0x040);
274fec93
BS		 716 status &= ~0x040;
717 }
718
719 /* MP: CUDA execution engines. */
720 if (status & 0x080) {
ebb945a9
BS		 721 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
722 "TRAP_MP");
723 nv_wr32(priv, 0x400108, 0x080);
274fec93
BS		 724 status &= ~0x080;
725 }
726
727 /* TPDMA: Handles TP-initiated uncached memory accesses:
728 * l[], g[], stack, 2d surfaces, render targets. */
729 if (status & 0x100) {
ebb945a9
BS		 730 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
731 "TRAP_TPDMA");
732 nv_wr32(priv, 0x400108, 0x100);
274fec93
BS		 733 status &= ~0x100;
734 }
735
736 if (status) {
737 if (display)
ebb945a9
BS		 738 nv_error(priv, "TRAP: unknown 0x%08x\n", status);
739 nv_wr32(priv, 0x400108, status);
274fec93
BS		 740 }
741
742 return 1;
743}
744
ebb945a9
BS		 745static void
746nv50_graph_intr(struct nouveau_subdev *subdev)
274fec93 747{
72a14827 748 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
ebb945a9 749 struct nouveau_engine *engine = nv_engine(subdev);
72a14827 750 struct nouveau_object *engctx;
ebb945a9 751 struct nouveau_handle *handle = NULL;
72a14827 752 struct nv50_graph_priv *priv = (void *)subdev;
ebb945a9 753 u32 stat = nv_rd32(priv, 0x400100);
72a14827 754 u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
ebb945a9
BS		 755 u32 addr = nv_rd32(priv, 0x400704);
756 u32 subc = (addr & 0x00070000) >> 16;
757 u32 mthd = (addr & 0x00001ffc);
758 u32 data = nv_rd32(priv, 0x400708);
759 u32 class = nv_rd32(priv, 0x400814);
760 u32 show = stat;
72a14827
BS		 761 int chid;
762
763 engctx = nouveau_engctx_get(engine, inst);
764 chid = pfifo->chid(pfifo, engctx);
ebb945a9
BS		 765
766 if (stat & 0x00000010) {
72a14827 767 handle = nouveau_handle_get_class(engctx, class);
ebb945a9
BS		 768 if (handle && !nv_call(handle->object, mthd, data))
769 show &= ~0x00000010;
72a14827 770 nouveau_handle_put(handle);
ebb945a9 771 }
274fec93 772
ebb945a9
BS		 773 if (show & 0x00100000) {
774 u32 ecode = nv_rd32(priv, 0x400110);
775 nv_error(priv, "DATA_ERROR ");
776 nouveau_enum_print(nv50_data_error_names, ecode);
777 printk("\n");
778 }
274fec93 779
ebb945a9 780 if (stat & 0x00200000) {
72a14827 781 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12))
ebb945a9
BS		 782 show &= ~0x00200000;
783 }
784
785 nv_wr32(priv, 0x400100, stat);
786 nv_wr32(priv, 0x400500, 0x00010001);
787
788 if (show) {
ae4ba737 789 nv_error(priv, "");
ebb945a9
BS		 790 nouveau_bitfield_print(nv50_graph_intr_name, show);
791 printk("\n");
72a14827 792 nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x "
ebb945a9 793 "mthd 0x%04x data 0x%08x\n",
72a14827 794 chid, (u64)inst << 12, subc, class, mthd, data);
274fec93 795 }
ebb945a9
BS		 796
797 if (nv_rd32(priv, 0x400824) & (1 << 31))
798 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
72a14827
BS		 799
800 nouveau_engctx_put(engctx);
274fec93
BS		 801}
802
ebb945a9
BS		 803static int
804nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
805 struct nouveau_oclass *oclass, void *data, u32 size,
806 struct nouveau_object **pobject)
274fec93 807{
ebb945a9
BS		 808 struct nv50_graph_priv *priv;
809 int ret;
274fec93 810
ebb945a9
BS		 811 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
812 *pobject = nv_object(priv);
813 if (ret)
814 return ret;
274fec93 815
ebb945a9
BS		 816 nv_subdev(priv)->unit = 0x00201000;
817 nv_subdev(priv)->intr = nv50_graph_intr;
818 nv_engine(priv)->cclass = &nv50_graph_cclass;
274fec93 819
ebb945a9
BS		 820 switch (nv_device(priv)->chipset) {
821 case 0x50:
822 nv_engine(priv)->sclass = nv50_graph_sclass;
823 break;
824 case 0x84:
825 case 0x86:
826 case 0x92:
827 case 0x94:
828 case 0x96:
829 case 0x98:
830 nv_engine(priv)->sclass = nv84_graph_sclass;
831 break;
832 case 0xa0:
833 case 0xaa:
834 case 0xac:
835 nv_engine(priv)->sclass = nva0_graph_sclass;
836 break;
837 case 0xa3:
838 case 0xa5:
839 case 0xa8:
840 nv_engine(priv)->sclass = nva3_graph_sclass;
841 break;
842 case 0xaf:
843 nv_engine(priv)->sclass = nvaf_graph_sclass;
844 break;
274fec93 845
ebb945a9 846 };
274fec93 847
ebb945a9
BS		 848 if (nv_device(priv)->chipset == 0x50 ||
849 nv_device(priv)->chipset == 0xac)
850 nv_engine(priv)->tlb_flush = nv50_graph_tlb_flush;
851 else
852 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
274fec93 853
ebb945a9
BS		 854 spin_lock_init(&priv->lock);
855 return 0;
274fec93 856}
2703c21a 857
ebb945a9
BS		 858static int
859nv50_graph_init(struct nouveau_object *object)
2703c21a 860{
ebb945a9
BS		 861 struct nv50_graph_priv *priv = (void *)object;
862 int ret, units, i;
2703c21a 863
ebb945a9
BS		 864 ret = nouveau_graph_init(&priv->base);
865 if (ret)
866 return ret;
2703c21a 867
ebb945a9
BS		 868 /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
869 nv_wr32(priv, 0x40008c, 0x00000004);
2703c21a 870
ebb945a9
BS		 871 /* reset/enable traps and interrupts */
872 nv_wr32(priv, 0x400804, 0xc0000000);
873 nv_wr32(priv, 0x406800, 0xc0000000);
874 nv_wr32(priv, 0x400c04, 0xc0000000);
875 nv_wr32(priv, 0x401800, 0xc0000000);
876 nv_wr32(priv, 0x405018, 0xc0000000);
877 nv_wr32(priv, 0x402000, 0xc0000000);
878
879 units = nv_rd32(priv, 0x001540);
880 for (i = 0; i < 16; i++) {
881 if (!(units & (1 << i)))
882 continue;
2703c21a 883
ebb945a9
BS		 884 if (nv_device(priv)->chipset < 0xa0) {
885 nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
886 nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
887 nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
888 } else {
889 nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
890 nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
891 nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
892 }
2703c21a
BS		 893 }
894
ebb945a9
BS		 895 nv_wr32(priv, 0x400108, 0xffffffff);
896 nv_wr32(priv, 0x400138, 0xffffffff);
897 nv_wr32(priv, 0x400100, 0xffffffff);
898 nv_wr32(priv, 0x40013c, 0xffffffff);
899 nv_wr32(priv, 0x400500, 0x00010001);
2703c21a 900
ebb945a9
BS		 901 /* upload context program, initialise ctxctl defaults */
902 ret = nv50_grctx_init(nv_device(priv), &priv->size);
903 if (ret)
904 return ret;
2703c21a 905
ebb945a9
BS		 906 nv_wr32(priv, 0x400824, 0x00000000);
907 nv_wr32(priv, 0x400828, 0x00000000);
908 nv_wr32(priv, 0x40082c, 0x00000000);
909 nv_wr32(priv, 0x400830, 0x00000000);
910 nv_wr32(priv, 0x400724, 0x00000000);
911 nv_wr32(priv, 0x40032c, 0x00000000);
912 nv_wr32(priv, 0x400320, 4); /* CTXCTL_CMD = NEWCTXDMA */
2703c21a 913
ebb945a9
BS		 914 /* some unknown zcull magic */
915 switch (nv_device(priv)->chipset & 0xf0) {
916 case 0x50:
917 case 0x80:
918 case 0x90:
919 nv_wr32(priv, 0x402ca8, 0x00000800);
920 break;
921 case 0xa0:
922 default:
923 nv_wr32(priv, 0x402cc0, 0x00000000);
924 if (nv_device(priv)->chipset == 0xa0 ||
925 nv_device(priv)->chipset == 0xaa ||
926 nv_device(priv)->chipset == 0xac) {
927 nv_wr32(priv, 0x402ca8, 0x00000802);
928 } else {
929 nv_wr32(priv, 0x402cc0, 0x00000000);
930 nv_wr32(priv, 0x402ca8, 0x00000002);
2703c21a 931 }
2703c21a 932
ebb945a9
BS		 933 break;
934 }
2703c21a 935
ebb945a9
BS		 936 /* zero out zcull regions */
937 for (i = 0; i < 8; i++) {
938 nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000);
939 nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000);
940 nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000);
941 nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000);
942 }
2703c21a
BS		 943 return 0;
944}
ebb945a9
BS		 945
946struct nouveau_oclass
947nv50_graph_oclass = {
948 .handle = NV_ENGINE(GR, 0x50),
949 .ofuncs = &(struct nouveau_ofuncs) {
950 .ctor = nv50_graph_ctor,
951 .dtor = _nouveau_graph_dtor,
952 .init = nv50_graph_init,
953 .fini = _nouveau_graph_fini,
954 },
955};
Linux kernel - Deliverables
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