[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / mpeg / nv31.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/client.h>
#include <core/os.h>
#include <core/class.h>
#include <core/engctx.h>
#include <core/handle.h>

#include <subdev/fb.h>
#include <subdev/timer.h>
#include <subdev/instmem.h>

#include <engine/fifo.h>
#include <engine/mpeg.h>
#include <engine/graph/nv40.h>

struct nv31_mpeg_priv {
	struct nouveau_mpeg base;
	atomic_t refcount;
};

struct nv31_mpeg_chan {
	struct nouveau_object base;
};

/*******************************************************************************
 * MPEG object classes
 ******************************************************************************/

static int
nv31_mpeg_object_ctor(struct nouveau_object *parent,
		      struct nouveau_object *engine,
		      struct nouveau_oclass *oclass, void *data, u32 size,
		      struct nouveau_object **pobject)
{
	struct nouveau_gpuobj *obj;
	int ret;

	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
				    20, 16, 0, &obj);
	*pobject = nv_object(obj);
	if (ret)
		return ret;

	nv_wo32(obj, 0x00, nv_mclass(obj));
	nv_wo32(obj, 0x04, 0x00000000);
	nv_wo32(obj, 0x08, 0x00000000);
	nv_wo32(obj, 0x0c, 0x00000000);
	return 0;
}

static int
nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
{
	struct nouveau_instmem *imem = nouveau_instmem(object);
	struct nv31_mpeg_priv *priv = (void *)object->engine;
	u32 inst = *(u32 *)arg << 4;
	u32 dma0 = nv_ro32(imem, inst + 0);
	u32 dma1 = nv_ro32(imem, inst + 4);
	u32 dma2 = nv_ro32(imem, inst + 8);
	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
	u32 size = dma1 + 1;

	/* only allow linear DMA objects */
	if (!(dma0 & 0x00002000))
		return -EINVAL;

	if (mthd == 0x0190) {
		/* DMA_CMD */
		nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
		nv_wr32(priv, 0x00b334, base);
		nv_wr32(priv, 0x00b324, size);
	} else
	if (mthd == 0x01a0) {
		/* DMA_DATA */
		nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
		nv_wr32(priv, 0x00b360, base);
		nv_wr32(priv, 0x00b364, size);
	} else {
		/* DMA_IMAGE, VRAM only */
		if (dma0 & 0x000c0000)
			return -EINVAL;

		nv_wr32(priv, 0x00b370, base);
		nv_wr32(priv, 0x00b374, size);
	}

	return 0;
}

static struct nouveau_ofuncs
nv31_mpeg_ofuncs = {
	.ctor = nv31_mpeg_object_ctor,
	.dtor = _nouveau_gpuobj_dtor,
	.init = _nouveau_gpuobj_init,
	.fini = _nouveau_gpuobj_fini,
	.rd32 = _nouveau_gpuobj_rd32,
	.wr32 = _nouveau_gpuobj_wr32,
};

static struct nouveau_omthds
nv31_mpeg_omthds[] = {
	{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
	{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
	{ 0x01b0, 0x01b0, nv31_mpeg_mthd_dma },
	{}
};

struct nouveau_oclass
nv31_mpeg_sclass[] = {
	{ 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds },
	{}
};

/*******************************************************************************
 * PMPEG context
 ******************************************************************************/

static int
nv31_mpeg_context_ctor(struct nouveau_object *parent,
		       struct nouveau_object *engine,
		       struct nouveau_oclass *oclass, void *data, u32 size,
		       struct nouveau_object **pobject)
{
	struct nv31_mpeg_priv *priv = (void *)engine;
	struct nv31_mpeg_chan *chan;
	int ret;

	if (!atomic_add_unless(&priv->refcount, 1, 1))
		return -EBUSY;

	ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	return 0;
}

static void
nv31_mpeg_context_dtor(struct nouveau_object *object)
{
	struct nv31_mpeg_priv *priv = (void *)object->engine;
	struct nv31_mpeg_chan *chan = (void *)object;
	atomic_dec(&priv->refcount);
	nouveau_object_destroy(&chan->base);
}

static struct nouveau_oclass
nv31_mpeg_cclass = {
	.handle = NV_ENGCTX(MPEG, 0x31),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv31_mpeg_context_ctor,
		.dtor = nv31_mpeg_context_dtor,
		.init = nouveau_object_init,
		.fini = nouveau_object_fini,
	},
};

/*******************************************************************************
 * PMPEG engine/subdev functions
 ******************************************************************************/

void
nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
{
	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	struct nv31_mpeg_priv *priv = (void *)engine;

	nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch);
	nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit);
	nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr);
}

void
nv31_mpeg_intr(struct nouveau_subdev *subdev)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
	struct nouveau_engine *engine = nv_engine(subdev);
	struct nouveau_object *engctx;
	struct nouveau_handle *handle;
	struct nv31_mpeg_priv *priv = (void *)subdev;
	u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
	u32 stat = nv_rd32(priv, 0x00b100);
	u32 type = nv_rd32(priv, 0x00b230);
	u32 mthd = nv_rd32(priv, 0x00b234);
	u32 data = nv_rd32(priv, 0x00b238);
	u32 show = stat;
	int chid;

	engctx = nouveau_engctx_get(engine, inst);
	chid   = pfifo->chid(pfifo, engctx);

	if (stat & 0x01000000) {
		/* happens on initial binding of the object */
		if (type == 0x00000020 && mthd == 0x0000) {
			nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
			show &= ~0x01000000;
		}

		if (type == 0x00000010) {
			handle = nouveau_handle_get_class(engctx, 0x3174);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~0x01000000;
			nouveau_handle_put(handle);
		}
	}

	nv_wr32(priv, 0x00b100, stat);
	nv_wr32(priv, 0x00b230, 0x00000001);

	if (show) {
		nv_error(priv,
			 "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
			 chid, inst << 4, nouveau_client_name(engctx), stat,
			 type, mthd, data);
	}

	nouveau_engctx_put(engctx);
}

static int
nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv31_mpeg_priv *priv;
	int ret;

	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00000002;
	nv_subdev(priv)->intr = nv31_mpeg_intr;
	nv_engine(priv)->cclass = &nv31_mpeg_cclass;
	nv_engine(priv)->sclass = nv31_mpeg_sclass;
	nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
	return 0;
}

int
nv31_mpeg_init(struct nouveau_object *object)
{
	struct nouveau_engine *engine = nv_engine(object);
	struct nv31_mpeg_priv *priv = (void *)object;
	struct nouveau_fb *pfb = nouveau_fb(object);
	int ret, i;

	ret = nouveau_mpeg_init(&priv->base);
	if (ret)
		return ret;

	/* VPE init */
	nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
	nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */

	for (i = 0; i < pfb->tile.regions; i++)
		engine->tile_prog(engine, i);

	/* PMPEG init */
	nv_wr32(priv, 0x00b32c, 0x00000000);
	nv_wr32(priv, 0x00b314, 0x00000100);
	if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv))
		nv_wr32(priv, 0x00b220, 0x00000044);
	else
		nv_wr32(priv, 0x00b220, 0x00000031);
	nv_wr32(priv, 0x00b300, 0x02001ec1);
	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);

	nv_wr32(priv, 0x00b100, 0xffffffff);
	nv_wr32(priv, 0x00b140, 0xffffffff);

	if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
		nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
		return -EBUSY;
	}

	return 0;
}

struct nouveau_oclass
nv31_mpeg_oclass = {
	.handle = NV_ENGINE(MPEG, 0x31),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv31_mpeg_ctor,
		.dtor = _nouveau_mpeg_dtor,
		.init = nv31_mpeg_init,
		.fini = _nouveau_mpeg_fini,
	},
};
Commit	Line	Data
a02ccc7f	1	/*
ebb945a9	2	* Copyright 2012 Red Hat Inc.
a02ccc7f BS	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
93260d3c	25	#include <core/client.h>
ebb945a9 BS	26	#include <core/os.h>
	27	#include <core/class.h>
	28	#include <core/engctx.h>
	29	#include <core/handle.h>
a02ccc7f	30
ebb945a9 BS	31	#include <subdev/fb.h>
	32	#include <subdev/timer.h>
	33	#include <subdev/instmem.h>
52d07331	34
72a14827	35	#include <engine/fifo.h>
ebb945a9	36	#include <engine/mpeg.h>
72a14827	37	#include <engine/graph/nv40.h>
a02ccc7f	38
ebb945a9 BS	39	struct nv31_mpeg_priv {
	40	struct nouveau_mpeg base;
	41	atomic_t refcount;
	42	};
a02ccc7f	43
ebb945a9 BS	44	struct nv31_mpeg_chan {
	45	struct nouveau_object base;
	46	};
a02ccc7f	47
ebb945a9 BS	48	/*******************************************************************************
	49	* MPEG object classes
	50	******************************************************************************/
a02ccc7f BS	51
a02ccc7f BS	52	static int
ebb945a9 BS	53	nv31_mpeg_object_ctor(struct nouveau_object *parent,
	54	struct nouveau_object *engine,
	55	struct nouveau_oclass oclass, void data, u32 size,
	56	struct nouveau_object **pobject)
a02ccc7f	57	{
ebb945a9	58	struct nouveau_gpuobj *obj;
a02ccc7f BS	59	int ret;
a02ccc7f BS	60
ebb945a9 BS	61	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
	62	20, 16, 0, &obj);
	63	*pobject = nv_object(obj);
a02ccc7f BS	64	if (ret)
a02ccc7f BS	65	return ret;
a02ccc7f	66
ebb945a9 BS	67	nv_wo32(obj, 0x00, nv_mclass(obj));
	68	nv_wo32(obj, 0x04, 0x00000000);
	69	nv_wo32(obj, 0x08, 0x00000000);
	70	nv_wo32(obj, 0x0c, 0x00000000);
a02ccc7f BS	71	return 0;
	72	}
	73
	74	static int
ebb945a9	75	nv31_mpeg_mthd_dma(struct nouveau_object object, u32 mthd, void arg, u32 len)
a02ccc7f	76	{
ebb945a9 BS	77	struct nouveau_instmem *imem = nouveau_instmem(object);
	78	struct nv31_mpeg_priv priv = (void )object->engine;
	79	u32 inst = (u32 )arg << 4;
	80	u32 dma0 = nv_ro32(imem, inst + 0);
	81	u32 dma1 = nv_ro32(imem, inst + 4);
	82	u32 dma2 = nv_ro32(imem, inst + 8);
a02ccc7f BS	83	u32 base = (dma2 & 0xfffff000) \| (dma0 >> 20);
	84	u32 size = dma1 + 1;
	85
	86	/* only allow linear DMA objects */
	87	if (!(dma0 & 0x00002000))
	88	return -EINVAL;
	89
	90	if (mthd == 0x0190) {
	91	/* DMA_CMD */
ebb945a9 BS	92	nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
	93	nv_wr32(priv, 0x00b334, base);
	94	nv_wr32(priv, 0x00b324, size);
a02ccc7f BS	95	} else
	96	if (mthd == 0x01a0) {
	97	/* DMA_DATA */
ebb945a9 BS	98	nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
	99	nv_wr32(priv, 0x00b360, base);
	100	nv_wr32(priv, 0x00b364, size);
a02ccc7f BS	101	} else {
	102	/* DMA_IMAGE, VRAM only */
	103	if (dma0 & 0x000c0000)
	104	return -EINVAL;
	105
ebb945a9 BS	106	nv_wr32(priv, 0x00b370, base);
ebb945a9 BS	107	nv_wr32(priv, 0x00b374, size);
a02ccc7f BS	108	}
	109
	110	return 0;
	111	}
	112
5b8a43ae	113	static struct nouveau_ofuncs
ebb945a9 BS	114	nv31_mpeg_ofuncs = {
	115	.ctor = nv31_mpeg_object_ctor,
	116	.dtor = _nouveau_gpuobj_dtor,
	117	.init = _nouveau_gpuobj_init,
	118	.fini = _nouveau_gpuobj_fini,
	119	.rd32 = _nouveau_gpuobj_rd32,
	120	.wr32 = _nouveau_gpuobj_wr32,
	121	};
	122
5b8a43ae	123	static struct nouveau_omthds
ebb945a9	124	nv31_mpeg_omthds[] = {
fb445b3c BS	125	{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
	126	{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
	127	{ 0x01b0, 0x01b0, nv31_mpeg_mthd_dma },
ebb945a9 BS	128	{}
	129	};
	130
	131	struct nouveau_oclass
	132	nv31_mpeg_sclass[] = {
	133	{ 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds },
	134	{}
	135	};
	136
	137	/*******************************************************************************
	138	* PMPEG context
	139	******************************************************************************/
	140
a02ccc7f	141	static int
ebb945a9 BS	142	nv31_mpeg_context_ctor(struct nouveau_object *parent,
	143	struct nouveau_object *engine,
	144	struct nouveau_oclass oclass, void data, u32 size,
	145	struct nouveau_object **pobject)
a02ccc7f	146	{
ebb945a9 BS	147	struct nv31_mpeg_priv priv = (void )engine;
	148	struct nv31_mpeg_chan *chan;
	149	int ret;
	150
	151	if (!atomic_add_unless(&priv->refcount, 1, 1))
	152	return -EBUSY;
	153
	154	ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
	155	*pobject = nv_object(chan);
	156	if (ret)
	157	return ret;
	158
	159	return 0;
a02ccc7f BS	160	}
	161
	162	static void
ebb945a9	163	nv31_mpeg_context_dtor(struct nouveau_object *object)
a02ccc7f	164	{
ebb945a9 BS	165	struct nv31_mpeg_priv priv = (void )object->engine;
	166	struct nv31_mpeg_chan chan = (void )object;
	167	atomic_dec(&priv->refcount);
	168	nouveau_object_destroy(&chan->base);
a02ccc7f BS	169	}
a02ccc7f BS	170
ebb945a9 BS	171	static struct nouveau_oclass
	172	nv31_mpeg_cclass = {
	173	.handle = NV_ENGCTX(MPEG, 0x31),
	174	.ofuncs = &(struct nouveau_ofuncs) {
	175	.ctor = nv31_mpeg_context_ctor,
	176	.dtor = nv31_mpeg_context_dtor,
	177	.init = nouveau_object_init,
	178	.fini = nouveau_object_fini,
	179	},
	180	};
	181
	182	/*******************************************************************************
	183	* PMPEG engine/subdev functions
	184	******************************************************************************/
	185
	186	void
	187	nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
a02ccc7f	188	{
ebb945a9 BS	189	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	190	struct nv31_mpeg_priv priv = (void )engine;
	191
	192	nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch);
	193	nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit);
	194	nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr);
	195	}
	196
	197	void
	198	nv31_mpeg_intr(struct nouveau_subdev *subdev)
	199	{
72a14827	200	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
ebb945a9	201	struct nouveau_engine *engine = nv_engine(subdev);
72a14827 BS	202	struct nouveau_object *engctx;
	203	struct nouveau_handle *handle;
	204	struct nv31_mpeg_priv priv = (void )subdev;
	205	u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
ebb945a9 BS	206	u32 stat = nv_rd32(priv, 0x00b100);
	207	u32 type = nv_rd32(priv, 0x00b230);
	208	u32 mthd = nv_rd32(priv, 0x00b234);
	209	u32 data = nv_rd32(priv, 0x00b238);
a02ccc7f	210	u32 show = stat;
72a14827 BS	211	int chid;
	212
	213	engctx = nouveau_engctx_get(engine, inst);
	214	chid = pfifo->chid(pfifo, engctx);
a02ccc7f BS	215
	216	if (stat & 0x01000000) {
	217	/* happens on initial binding of the object */
72a14827	218	if (type == 0x00000020 && mthd == 0x0000) {
ebb945a9	219	nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
a02ccc7f BS	220	show &= ~0x01000000;
	221	}
	222
72a14827 BS	223	if (type == 0x00000010) {
	224	handle = nouveau_handle_get_class(engctx, 0x3174);
	225	if (handle && !nv_call(handle->object, mthd, data))
a02ccc7f	226	show &= ~0x01000000;
72a14827	227	nouveau_handle_put(handle);
a02ccc7f BS	228	}
	229	}
	230
ebb945a9 BS	231	nv_wr32(priv, 0x00b100, stat);
ebb945a9 BS	232	nv_wr32(priv, 0x00b230, 0x00000001);
a02ccc7f	233
ebb945a9	234	if (show) {
93260d3c MS	235	nv_error(priv,
	236	"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
	237	chid, inst << 4, nouveau_client_name(engctx), stat,
	238	type, mthd, data);
a02ccc7f	239	}
72a14827 BS	240
72a14827 BS	241	nouveau_engctx_put(engctx);
a02ccc7f BS	242	}
a02ccc7f BS	243
ebb945a9 BS	244	static int
	245	nv31_mpeg_ctor(struct nouveau_object parent, struct nouveau_object engine,
	246	struct nouveau_oclass oclass, void data, u32 size,
	247	struct nouveau_object **pobject)
a02ccc7f	248	{
ebb945a9 BS	249	struct nv31_mpeg_priv *priv;
ebb945a9 BS	250	int ret;
a02ccc7f	251
ebb945a9 BS	252	ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
	253	*pobject = nv_object(priv);
	254	if (ret)
	255	return ret;
	256
	257	nv_subdev(priv)->unit = 0x00000002;
	258	nv_subdev(priv)->intr = nv31_mpeg_intr;
	259	nv_engine(priv)->cclass = &nv31_mpeg_cclass;
	260	nv_engine(priv)->sclass = nv31_mpeg_sclass;
	261	nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
	262	return 0;
a02ccc7f BS	263	}
a02ccc7f BS	264
ebb945a9 BS	265	int
ebb945a9 BS	266	nv31_mpeg_init(struct nouveau_object *object)
a02ccc7f	267	{
18f35fa6 IM	268	struct nouveau_engine *engine = nv_engine(object);
18f35fa6 IM	269	struct nv31_mpeg_priv priv = (void )object;
ebb945a9 BS	270	struct nouveau_fb *pfb = nouveau_fb(object);
ebb945a9 BS	271	int ret, i;
a02ccc7f	272
ebb945a9 BS	273	ret = nouveau_mpeg_init(&priv->base);
	274	if (ret)
	275	return ret;
a02ccc7f	276
ebb945a9 BS	277	/* VPE init */
	278	nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
	279	nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
a02ccc7f	280
ebb945a9 BS	281	for (i = 0; i < pfb->tile.regions; i++)
	282	engine->tile_prog(engine, i);
	283
	284	/* PMPEG init */
	285	nv_wr32(priv, 0x00b32c, 0x00000000);
	286	nv_wr32(priv, 0x00b314, 0x00000100);
dc409df9 IM	287	if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv))
	288	nv_wr32(priv, 0x00b220, 0x00000044);
	289	else
	290	nv_wr32(priv, 0x00b220, 0x00000031);
ebb945a9 BS	291	nv_wr32(priv, 0x00b300, 0x02001ec1);
	292	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
	293
	294	nv_wr32(priv, 0x00b100, 0xffffffff);
	295	nv_wr32(priv, 0x00b140, 0xffffffff);
	296
	297	if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
	298	nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
	299	return -EBUSY;
52d07331	300	}
a02ccc7f	301
ebb945a9	302	return 0;
a02ccc7f	303	}
ebb945a9 BS	304
	305	struct nouveau_oclass
	306	nv31_mpeg_oclass = {
	307	.handle = NV_ENGINE(MPEG, 0x31),
	308	.ofuncs = &(struct nouveau_ofuncs) {
	309	.ctor = nv31_mpeg_ctor,
	310	.dtor = _nouveau_mpeg_dtor,
	311	.init = nv31_mpeg_init,
	312	.fini = _nouveau_mpeg_fini,
	313	},
	314	};